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Merge branch 'feature/esp32s31_dma2d_support' into 'master'

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feat(dma2d): add support for esp32s31

Closes IDF-14762

See merge request espressif/esp-idf!47168
This commit is contained in:
Song Ruo Jing
2026-04-10 19:14:33 +08:00
parent 37e7f60dcf ce1d910965
commit 321896bde6
15 changed files with 1452 additions and 262 deletions
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components/esp_driver_dma/src/dma2d.c
+27 -37
View File
@@ -378,7 +378,6 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl
pre_alloc_group->rx_channel_reserved_mask = dma2d_rx_channel_reserved_mask[group_id];
pre_alloc_group->tx_periph_m2m_free_id_mask = DMA2D_LL_TX_CHANNEL_PERIPH_M2M_AVAILABLE_ID_MASK;
pre_alloc_group->rx_periph_m2m_free_id_mask = DMA2D_LL_RX_CHANNEL_PERIPH_M2M_AVAILABLE_ID_MASK;
pre_alloc_group->intr_priority = -1;
for (int i = 0; i < DMA2D_LL_GET(TX_CHANS_PER_INST); i++) {
pre_alloc_group->tx_chans[i] = &pre_alloc_tx_channels[i];
dma2d_tx_channel_t *tx_chan = pre_alloc_group->tx_chans[i];
@@ -418,51 +417,38 @@ esp_err_t dma2d_acquire_pool(const dma2d_pool_config_t *config, dma2d_pool_handl
s_platform.group_ref_counts[group_id]++;
}
// Allocate interrupts
// First figure out the interrupt priority
bool intr_priority_conflict = false;
if (s_platform.groups[group_id]->intr_priority == -1) {
s_platform.groups[group_id]->intr_priority = config->intr_priority;
} else if (config->intr_priority != 0) {
intr_priority_conflict = (s_platform.groups[group_id]->intr_priority != config->intr_priority);
}
ESP_GOTO_ON_FALSE(!intr_priority_conflict, ESP_ERR_INVALID_ARG, wrap_up, TAG, "intr_priority conflict, already is %d but attempt to %" PRIu32, s_platform.groups[group_id]->intr_priority, config->intr_priority);
uint32_t intr_flags = DMA2D_INTR_ALLOC_FLAGS;
if (s_platform.groups[group_id]->intr_priority) {
intr_flags |= (1 << s_platform.groups[group_id]->intr_priority);
} else {
intr_flags |= ESP_INTR_FLAG_LOWMED;
}
// Allocate TX and RX interrupts
uint32_t intr_flags = DMA2D_INTR_ALLOC_FLAGS | (config->intr_priority ? (1 << config->intr_priority) : ESP_INTR_FLAG_LOWMED);
if (s_platform.groups[group_id]) {
for (int i = 0; i < DMA2D_LL_GET(RX_CHANS_PER_INST); i++) {
dma2d_rx_channel_t *rx_chan = s_platform.groups[group_id]->rx_chans[i];
if (rx_chan->base.intr == NULL) {
ret = esp_intr_alloc_intrstatus(dma2d_periph_signals.groups[group_id].rx_irq_id[i],
intr_flags,
(uint32_t)dma2d_ll_rx_get_interrupt_status_reg(s_platform.groups[group_id]->hal.dev, i),
DMA2D_LL_RX_EVENT_MASK, dma2d_default_isr, &rx_chan->base, &rx_chan->base.intr);
if (ret != ESP_OK) {
ret = ESP_FAIL;
ESP_LOGE(TAG, "alloc interrupt failed on rx channel (%d, %d)", group_id, i);
goto wrap_up;
}
esp_intr_alloc_info_t intr_info = {
.source = dma2d_periph_signals.groups[group_id].rx_irq_id[i],
.flags = intr_flags,
.intrstatusreg = (uint32_t)dma2d_ll_rx_get_interrupt_status_reg(s_platform.groups[group_id]->hal.dev, i),
.intrstatusmask = DMA2D_LL_RX_EVENT_MASK,
.handler = dma2d_default_isr,
.arg = &rx_chan->base,
.bind_by.name = dma2d_periph_signals.groups[group_id].module_name,
};
ESP_GOTO_ON_ERROR(esp_intr_alloc_info(&intr_info, &rx_chan->base.intr), wrap_up, TAG, "alloc interrupt failed on rx channel (%d, %d)", group_id, i);
}
}
for (int i = 0; i < DMA2D_LL_GET(TX_CHANS_PER_INST); i++) {
dma2d_tx_channel_t *tx_chan = s_platform.groups[group_id]->tx_chans[i];
if (tx_chan->base.intr == NULL) {
ret = esp_intr_alloc_intrstatus(dma2d_periph_signals.groups[group_id].tx_irq_id[i],
intr_flags,
(uint32_t)dma2d_ll_tx_get_interrupt_status_reg(s_platform.groups[group_id]->hal.dev, i),
DMA2D_LL_TX_EVENT_MASK, dma2d_default_isr, &tx_chan->base, &tx_chan->base.intr);
if (ret != ESP_OK) {
ret = ESP_FAIL;
ESP_LOGE(TAG, "alloc interrupt failed on tx channel (%d, %d)", group_id, i);
goto wrap_up;
}
esp_intr_alloc_info_t intr_info = {
.source = dma2d_periph_signals.groups[group_id].tx_irq_id[i],
.flags = intr_flags,
.intrstatusreg = (uint32_t)dma2d_ll_tx_get_interrupt_status_reg(s_platform.groups[group_id]->hal.dev, i),
.intrstatusmask = DMA2D_LL_TX_EVENT_MASK,
.handler = dma2d_default_isr,
.arg = &tx_chan->base,
.bind_by.name = dma2d_periph_signals.groups[group_id].module_name,
};
ESP_GOTO_ON_ERROR(esp_intr_alloc_info(&intr_info, &tx_chan->base.intr), wrap_up, TAG, "alloc interrupt failed on tx channel (%d, %d)", group_id, i);
}
}
}
@@ -713,9 +699,13 @@ esp_err_t dma2d_set_desc_addr(dma2d_channel_handle_t dma2d_chan, intptr_t desc_b
esp_err_t ret = ESP_OK;
ESP_GOTO_ON_FALSE_ISR(dma2d_chan && desc_base_addr, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
// 2D-DMA descriptor addr needs 8-byte alignment and not in SPM (addr not in SPM is IDF restriction)
ESP_GOTO_ON_FALSE_ISR((desc_base_addr & 0x7) == 0 && !esp_ptr_in_spm((void *)desc_base_addr), ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
bool addr_in_spm = false;
#if SOC_MEM_SPM_SUPPORTED
addr_in_spm = esp_ptr_in_spm((void *)desc_base_addr);
#endif
ESP_GOTO_ON_FALSE_ISR((desc_base_addr & 0x7) == 0 && !addr_in_spm, ESP_ERR_INVALID_ARG, err, TAG, "invalid descriptor base addr");
// When flash encryption is enabled, the descriptor must be in internal RAM because descriptor size is not 16-byte aligned, which breaks flash encryption alignment restriction
ESP_GOTO_ON_FALSE_ISR(!esp_efuse_is_flash_encryption_enabled() || esp_ptr_internal((void *)desc_base_addr), ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
ESP_GOTO_ON_FALSE_ISR(!esp_efuse_is_flash_encryption_enabled() || esp_ptr_internal((void *)desc_base_addr), ESP_ERR_INVALID_ARG, err, TAG, "invalid description base addr");
dma2d_group_t *group = dma2d_chan->group;
int channel_id = dma2d_chan->channel_id;
components/esp_driver_dma/src/dma2d_priv.h
+2 -3
View File
@@ -28,9 +28,9 @@ extern "C" {
#endif
#if CONFIG_DMA2D_ISR_IRAM_SAFE
#define DMA2D_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_IRAM)
#define DMA2D_INTR_ALLOC_FLAGS (ESP_INTR_FLAG_SHARED_PRIVATE | ESP_INTR_FLAG_IRAM)
#else
#define DMA2D_INTR_ALLOC_FLAGS ESP_INTR_FLAG_SHARED
#define DMA2D_INTR_ALLOC_FLAGS ESP_INTR_FLAG_SHARED_PRIVATE
#endif
#define DMA2D_RX_DEFAULT_INTR_FLAG (DMA2D_LL_EVENT_RX_SUC_EOF | DMA2D_LL_EVENT_RX_ERR_EOF | DMA2D_LL_EVENT_RX_DESC_ERROR)
@@ -59,7 +59,6 @@ struct dma2d_group_t {
uint32_t rx_periph_m2m_free_id_mask; // Bit mask indicating the available RX M2M peripheral selelction IDs at the moment
dma2d_tx_channel_t *tx_chans[DMA2D_LL_GET(TX_CHANS_PER_INST)]; // Handles of 2D-DMA TX channels
dma2d_rx_channel_t *rx_chans[DMA2D_LL_GET(RX_CHANS_PER_INST)]; // Handles of 2D-DMA RX channels
int intr_priority; // All channels in the same group should share the same interrupt priority
};
struct dma2d_channel_t {
components/esp_driver_dma/test_apps/dma2d/README.md
+2 -2
View File
@@ -1,2 +1,2 @@
| Supported Targets | ESP32-P4 |
| ----------------- | -------- |
| Supported Targets | ESP32-P4 | ESP32-S31 |
| ----------------- | -------- | --------- |
components/esp_driver_dma/test_apps/dma2d/pytest_dma2d.py
+1
View File
@@ -28,5 +28,6 @@ def test_dma2d(dut: Dut) -> None:
indirect=True,
)
@idf_parametrize('target', soc_filtered_targets('SOC_DMA2D_SUPPORTED == 1'), indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='TODO: IDFCI-10377 no runner yet')
def test_dma2d_flash_encryption(dut: Dut) -> None:
dut.run_all_single_board_cases()
components/esp_driver_dma/test_apps/dma2d/sdkconfig.defaults.esp32s31
+3
View File
@@ -0,0 +1,3 @@
CONFIG_SPIRAM=y
CONFIG_SPIRAM_MODE_OCT=y
CONFIG_SPIRAM_SPEED_250M=y
components/esp_hal_dma/dma2d_hal.c
+2
View File
@@ -10,6 +10,8 @@
void dma2d_hal_init(dma2d_hal_context_t *hal, int group_id)
{
hal->dev = DMA2D_LL_GET_HW(group_id);
dma2d_ll_mem_power_by_pmu(hal->dev);
dma2d_ll_mem_set_low_power_mode(hal->dev, DMA2D_LL_MEM_LP_MODE_SHUT_DOWN);
}
void dma2d_hal_tx_reset_channel(dma2d_hal_context_t *hal, uint32_t channel)
components/esp_hal_dma/esp32p4/dma2d_periph.c
+8 -1
View File
@@ -1,15 +1,22 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/dma2d_periph.h"
#include "hal/dma2d_types.h"
#include "soc/interrupts.h"
const int dma2d_csc_param_yuv2rgb_bt601_table[3][4] = DMA2D_COLOR_SPACE_CONV_PARAM_YUV2RGB_BT601;
const int dma2d_csc_param_yuv2rgb_bt709_table[3][4] = DMA2D_COLOR_SPACE_CONV_PARAM_YUV2RGB_BT709;
const int dma2d_csc_param_rgb2yuv_bt601_table[3][4] = DMA2D_COLOR_SPACE_CONV_PARAM_RGB2YUV_BT601;
const int dma2d_csc_param_rgb2yuv_bt709_table[3][4] = DMA2D_COLOR_SPACE_CONV_PARAM_RGB2YUV_BT709;
const dma2d_signal_conn_t dma2d_periph_signals = {
.groups = {
[0] = {
.module_name = "dma2d0",
.tx_irq_id = {
[0] = ETS_DMA2D_OUT_CH0_INTR_SOURCE,
[1] = ETS_DMA2D_OUT_CH1_INTR_SOURCE,
components/esp_hal_dma/esp32p4/include/hal/dma2d_ll.h
+75 -30
View File
@@ -8,6 +8,7 @@
#include <stddef.h> /* Required for NULL constant */
#include <stdint.h>
#include <stdbool.h>
#include "esp_attr.h"
#include "hal/dma2d_types.h"
#include "soc/dma2d_channel.h"
#include "soc/dma2d_struct.h"
@@ -35,10 +36,6 @@
#define DMA2D_LL_RX_CHANS_PER_INST 2
#endif
#ifdef __cplusplus
extern "C" {
#endif
// 2D-DMA interrupts
#define DMA2D_LL_RX_EVENT_MASK (0x3FFF)
#define DMA2D_LL_TX_EVENT_MASK (0x1FFF)
@@ -92,6 +89,20 @@ extern "C" {
#define DMA2D_LL_DESC_ALIGNMENT 8 // Descriptor must be aligned to 8 bytes
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
DMA2D_LL_MEM_LP_MODE_SHUT_DOWN, // power down memory during low power stage
} dma2d_ll_mem_lp_mode_t;
// COLOR SPACE CONVERSION TABLES
extern const int dma2d_csc_param_yuv2rgb_bt601_table[3][4];
extern const int dma2d_csc_param_yuv2rgb_bt709_table[3][4];
extern const int dma2d_csc_param_rgb2yuv_bt601_table[3][4];
extern const int dma2d_csc_param_rgb2yuv_bt709_table[3][4];
///////////////////////////////////// Common /////////////////////////////////////////
/**
* @brief Enable the bus clock for 2D-DMA module
@@ -141,6 +152,48 @@ static inline bool dma2d_ll_is_bus_clock_enabled(int group_id)
return HP_SYS_CLKRST.soc_clk_ctrl1.reg_dma2d_sys_clk_en;
}
/**
* @brief Force power on the DMA2D memory block, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void dma2d_ll_mem_force_power_on(dma2d_dev_t *dev)
{
(void)dev;
}
/**
* @brief Force the DMA2D memory block into low power mode, regardless of the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void dma2d_ll_mem_force_low_power(dma2d_dev_t *dev)
{
(void)dev;
}
/**
* @brief Power control the DMA2D memory block by the outside PMU logic
*
* @param dev Peripheral instance address
*/
static inline void dma2d_ll_mem_power_by_pmu(dma2d_dev_t *dev)
{
(void)dev;
}
/**
* @brief Set low power mode for DMA2D memory block
*
* @param dev Peripheral instance address
* @param mode DMA2D memory low power mode in low power stage
*/
static inline void dma2d_ll_mem_set_low_power_mode(dma2d_dev_t *dev, dma2d_ll_mem_lp_mode_t mode)
{
(void)dev;
HAL_ASSERT(mode == DMA2D_LL_MEM_LP_MODE_SHUT_DOWN);
}
/**
* @brief Enable 2D-DMA module
*/
@@ -488,13 +541,10 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint
uint32_t input_sel = 7; // Disable CSC
// L2
bool proc_en = false; // Disable generic color convert module between color input & color output
int (*table)[4] = NULL;
const int (*table)[4] = NULL;
// L3
uint32_t output_sel = 1; // Output directly
const int color_space_conv_param_yuv2rgb_bt601_table[3][4] = DMA2D_COLOR_SPACE_CONV_PARAM_YUV2RGB_BT601;
const int color_space_conv_param_yuv2rgb_bt709_table[3][4] = DMA2D_COLOR_SPACE_CONV_PARAM_YUV2RGB_BT709;
switch (csc_sel) {
case DMA2D_CSC_RX_NONE:
input_sel = 7;
@@ -525,52 +575,52 @@ static inline void dma2d_ll_rx_configure_color_space_conv(dma2d_dev_t *dev, uint
case DMA2D_CSC_RX_YUV422_TO_RGB888_601:
input_sel = 0;
proc_en = true;
table = (int (*)[4])color_space_conv_param_yuv2rgb_bt601_table;
table = dma2d_csc_param_yuv2rgb_bt601_table;
output_sel = 1;
break;
case DMA2D_CSC_RX_YUV420_TO_RGB565_601:
case DMA2D_CSC_RX_YUV422_TO_RGB565_601:
input_sel = 0;
proc_en = true;
table = (int (*)[4])color_space_conv_param_yuv2rgb_bt601_table;
table = dma2d_csc_param_yuv2rgb_bt601_table;
output_sel = 0;
break;
case DMA2D_CSC_RX_YUV420_TO_RGB888_709:
case DMA2D_CSC_RX_YUV422_TO_RGB888_709:
input_sel = 0;
proc_en = true;
table = (int (*)[4])color_space_conv_param_yuv2rgb_bt709_table;
table = dma2d_csc_param_yuv2rgb_bt709_table;
output_sel = 1;
break;
case DMA2D_CSC_RX_YUV420_TO_RGB565_709:
case DMA2D_CSC_RX_YUV422_TO_RGB565_709:
input_sel = 0;
proc_en = true;
table = (int (*)[4])color_space_conv_param_yuv2rgb_bt709_table;
table = dma2d_csc_param_yuv2rgb_bt709_table;
output_sel = 0;
break;
case DMA2D_CSC_RX_YUV444_TO_RGB888_601:
input_sel = 2;
proc_en = true;
table = (int (*)[4])color_space_conv_param_yuv2rgb_bt601_table;
table = dma2d_csc_param_yuv2rgb_bt601_table;
output_sel = 1;
break;
case DMA2D_CSC_RX_YUV444_TO_RGB565_601:
input_sel = 2;
proc_en = true;
table = (int (*)[4])color_space_conv_param_yuv2rgb_bt601_table;
table = dma2d_csc_param_yuv2rgb_bt601_table;
output_sel = 0;
break;
case DMA2D_CSC_RX_YUV444_TO_RGB888_709:
input_sel = 2;
proc_en = true;
table = (int (*)[4])color_space_conv_param_yuv2rgb_bt709_table;
table = dma2d_csc_param_yuv2rgb_bt709_table;
output_sel = 1;
break;
case DMA2D_CSC_RX_YUV444_TO_RGB565_709:
input_sel = 2;
proc_en = true;
table = (int (*)[4])color_space_conv_param_yuv2rgb_bt709_table;
table = dma2d_csc_param_yuv2rgb_bt709_table;
output_sel = 0;
break;
default:
@@ -994,15 +1044,10 @@ static inline void dma2d_ll_tx_configure_color_space_conv(dma2d_dev_t *dev, uint
uint32_t input_sel = 7; // Disable CSC
// L2
bool proc_en = false; // Disable generic color convert module between color input & color output
int (*table)[4] = NULL;
const int (*table)[4] = NULL;
// L3
uint32_t output_sel = 2; // Output directly
const int color_space_conv_param_rgb2yuv_bt601_table[3][4] = DMA2D_COLOR_SPACE_CONV_PARAM_RGB2YUV_BT601;
const int color_space_conv_param_rgb2yuv_bt709_table[3][4] = DMA2D_COLOR_SPACE_CONV_PARAM_RGB2YUV_BT709;
const int color_space_conv_param_yuv2rgb_bt601_table[3][4] = DMA2D_COLOR_SPACE_CONV_PARAM_YUV2RGB_BT601;
const int color_space_conv_param_yuv2rgb_bt709_table[3][4] = DMA2D_COLOR_SPACE_CONV_PARAM_YUV2RGB_BT709;
switch (csc_sel) {
case DMA2D_CSC_TX_NONE:
input_sel = 7;
@@ -1025,49 +1070,49 @@ static inline void dma2d_ll_tx_configure_color_space_conv(dma2d_dev_t *dev, uint
case DMA2D_CSC_TX_RGB888_TO_YUV444_601:
input_sel = 3;
proc_en = true;
table = (int (*)[4])color_space_conv_param_rgb2yuv_bt601_table;
table = dma2d_csc_param_rgb2yuv_bt601_table;
output_sel = 2;
break;
case DMA2D_CSC_TX_RGB888_TO_YUV444_709:
input_sel = 3;
proc_en = true;
table = (int (*)[4])color_space_conv_param_rgb2yuv_bt709_table;
table = dma2d_csc_param_rgb2yuv_bt709_table;
output_sel = 2;
break;
case DMA2D_CSC_TX_RGB888_TO_YUV422_601:
input_sel = 3;
proc_en = true;
table = (int (*)[4])color_space_conv_param_rgb2yuv_bt601_table;
table = dma2d_csc_param_rgb2yuv_bt601_table;
output_sel = 1;
break;
case DMA2D_CSC_TX_RGB888_TO_YUV422_709:
input_sel = 3;
proc_en = true;
table = (int (*)[4])color_space_conv_param_rgb2yuv_bt709_table;
table = dma2d_csc_param_rgb2yuv_bt709_table;
output_sel = 1;
break;
case DMA2D_CSC_TX_YUV444_TO_RGB888_601:
input_sel = 3;
proc_en = true;
table = (int (*)[4])color_space_conv_param_yuv2rgb_bt601_table;
table = dma2d_csc_param_yuv2rgb_bt601_table;
output_sel = 2;
break;
case DMA2D_CSC_TX_YUV444_TO_RGB888_709:
input_sel = 3;
proc_en = true;
table = (int (*)[4])color_space_conv_param_yuv2rgb_bt709_table;
table = dma2d_csc_param_yuv2rgb_bt709_table;
output_sel = 2;
break;
case DMA2D_CSC_TX_YUV422_TO_RGB888_601:
input_sel = 1;
proc_en = true;
table = (int (*)[4])color_space_conv_param_yuv2rgb_bt601_table;
table = dma2d_csc_param_yuv2rgb_bt601_table;
output_sel = 2;
break;
case DMA2D_CSC_TX_YUV422_TO_RGB888_709:
input_sel = 1;
proc_en = true;
table = (int (*)[4])color_space_conv_param_yuv2rgb_bt709_table;
table = dma2d_csc_param_yuv2rgb_bt709_table;
output_sel = 2;
break;
default:
components/esp_hal_dma/esp32s31/dma2d_periph.c
+33
View File
@@ -0,0 +1,33 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/dma2d_periph.h"
#include "hal/dma2d_types.h"
#include "soc/interrupts.h"
const int dma2d_csc_param_rgb2yuv_bt601_table[3][4] = DMA2D_COLOR_SPACE_CONV_PARAM_RGB2YUV_BT601;
const int dma2d_csc_param_rgb2yuv_bt709_table[3][4] = DMA2D_COLOR_SPACE_CONV_PARAM_RGB2YUV_BT709;
const int dma2d_csc_param_yuv2rgb_bt601_table[3][4] = DMA2D_COLOR_SPACE_CONV_PARAM_YUV2RGB_BT601;
const int dma2d_csc_param_yuv2rgb_bt709_table[3][4] = DMA2D_COLOR_SPACE_CONV_PARAM_YUV2RGB_BT709;
const dma2d_signal_conn_t dma2d_periph_signals = {
.groups = {
[0] = {
.module_name = "dma2d0",
.tx_irq_id = {
[0] = ETS_DMA2D_OUT_CH0_INTR_SOURCE,
[1] = ETS_DMA2D_OUT_CH1_INTR_SOURCE,
[2] = ETS_DMA2D_OUT_CH2_INTR_SOURCE,
[3] = ETS_DMA2D_OUT_CH3_INTR_SOURCE,
},
.rx_irq_id = {
[0] = ETS_DMA2D_IN_CH0_INTR_SOURCE,
[1] = ETS_DMA2D_IN_CH1_INTR_SOURCE,
[2] = ETS_DMA2D_IN_CH2_INTR_SOURCE,
}
}
}
};
components/esp_hal_dma/esp32s31/include/hal/dma2d_ll.h
+1189
View File
File diff suppressed because it is too large Load Diff
components/esp_hal_dma/include/hal/dma2d_periph.h
+1
View File
@@ -20,6 +20,7 @@ extern "C" {
#if SOC_HAS(DMA2D)
typedef struct {
struct {
const char *module_name; // module name
const int tx_irq_id[DMA2D_LL_GET(TX_CHANS_PER_INST)];
const int rx_irq_id[DMA2D_LL_GET(RX_CHANS_PER_INST)];
} groups[DMA2D_LL_GET(INST_NUM)];
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -27,6 +27,10 @@ config SOC_LP_AHB_GDMA_SUPPORTED
bool
default y
config SOC_DMA2D_SUPPORTED
bool
default y
config SOC_GPTIMER_SUPPORTED
bool
default y
components/soc/esp32s31/include/soc/dma2d_channel.h
+19
View File
@@ -0,0 +1,19 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
#pragma once
// The following macros are matched with the 2D-DMA peri_sel field peripheral selection ID
#define SOC_DMA2D_TRIG_PERIPH_JPEG_RX (0)
#define SOC_DMA2D_TRIG_PERIPH_PPA_SRM_RX (1)
#define SOC_DMA2D_TRIG_PERIPH_PPA_BLEND_RX (2)
#define SOC_DMA2D_TRIG_PERIPH_M2M_RX (-1) // Any value of 3 ~ 7, TX and RX do not have to use same ID value for M2M
#define SOC_DMA2D_TRIG_PERIPH_JPEG_TX (0)
#define SOC_DMA2D_TRIG_PERIPH_PPA_SRM_TX (1)
#define SOC_DMA2D_TRIG_PERIPH_PPA_BLEND_BG_TX (2)
#define SOC_DMA2D_TRIG_PERIPH_PPA_BLEND_FG_TX (3)
#define SOC_DMA2D_TRIG_PERIPH_M2M_TX (-1) // Any value of 4 ~ 7, TX and RX do not have to use same ID value for M2M
components/soc/esp32s31/include/soc/soc_caps.h
+1 -1
View File
@@ -32,7 +32,7 @@
#define SOC_AHB_GDMA_SUPPORTED 1
#define SOC_AXI_GDMA_SUPPORTED 1
#define SOC_LP_AHB_GDMA_SUPPORTED 1
// #define SOC_DMA2D_SUPPORTED 1 // TODO: [ESP32S31] IDF-14762
#define SOC_DMA2D_SUPPORTED 1
#define SOC_GPTIMER_SUPPORTED 1
// #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32S31] IDF-14699
// #define SOC_LCDCAM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14722
components/soc/esp32s31/register/soc/dma2d_struct.h
+85 -188
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -1856,194 +1856,90 @@ typedef union {
} dma2d_in_peri_sel_chn_reg_t;
/** Type of in/out_color_param_h/m/l_chn register
* Configures the rx/tx color convert parameter of channel n
*/
typedef union {
struct {
struct {
uint32_t a : 10;
uint32_t b : 11;
uint32_t reserved21 : 11;
};
struct {
uint32_t c : 10;
uint32_t d : 18;
uint32_t reserved60 : 4;
};
};
uint32_t val[2];
} dma2d_color_param_reg_t;
typedef struct {
volatile dma2d_out_conf0_chn_reg_t out_conf0_ch0;
volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch0;
volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch0;
volatile dma2d_out_int_st_chn_reg_t out_int_st_ch0;
volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch0;
volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch0;
volatile dma2d_out_push_chn_reg_t out_push_ch0;
volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch0;
volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch0;
volatile dma2d_out_state_chn_reg_t out_state_ch0;
volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch0;
volatile dma2d_out_dscr_chn_reg_t out_dscr_ch0;
volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch0;
volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch0;
volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch0;
volatile dma2d_out_arb_chn_reg_t out_arb_ch0;
volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch0;
volatile dma2d_out_ro_pd_conf_chn_reg_t out_ro_pd_conf_ch0;
volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch0;
volatile dma2d_out_scramble_chn_reg_t out_scramble_ch0;
volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch0;
volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch0;
volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch0;
volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch0;
volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch0;
volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch0;
volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch0;
volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch0;
uint32_t reserved_070[36];
volatile dma2d_out_conf0_chn_reg_t out_conf0_ch1;
volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch1;
volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch1;
volatile dma2d_out_int_st_chn_reg_t out_int_st_ch1;
volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch1;
volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch1;
volatile dma2d_out_push_chn_reg_t out_push_ch1;
volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch1;
volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch1;
volatile dma2d_out_state_chn_reg_t out_state_ch1;
volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch1;
volatile dma2d_out_dscr_chn_reg_t out_dscr_ch1;
volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch1;
volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch1;
volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch1;
volatile dma2d_out_arb_chn_reg_t out_arb_ch1;
volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch1;
uint32_t reserved_144;
volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch1;
volatile dma2d_out_scramble_chn_reg_t out_scramble_ch1;
volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch1;
volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch1;
volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch1;
volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch1;
volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch1;
volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch1;
volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch1;
volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch1;
uint32_t reserved_170[36];
volatile dma2d_out_conf0_chn_reg_t out_conf0_ch2;
volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch2;
volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch2;
volatile dma2d_out_int_st_chn_reg_t out_int_st_ch2;
volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch2;
volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch2;
volatile dma2d_out_push_chn_reg_t out_push_ch2;
volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch2;
volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch2;
volatile dma2d_out_state_chn_reg_t out_state_ch2;
volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch2;
volatile dma2d_out_dscr_chn_reg_t out_dscr_ch2;
volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch2;
volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch2;
volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch2;
volatile dma2d_out_arb_chn_reg_t out_arb_ch2;
volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch2;
uint32_t reserved_244;
volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch2;
volatile dma2d_out_scramble_chn_reg_t out_scramble_ch2;
volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch2;
volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch2;
volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch2;
volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch2;
volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch2;
volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch2;
volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch2;
volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch2;
uint32_t reserved_270[36];
volatile dma2d_out_conf0_chn_reg_t out_conf0_ch3;
volatile dma2d_out_int_raw_chn_reg_t out_int_raw_ch3;
volatile dma2d_out_int_ena_chn_reg_t out_int_ena_ch3;
volatile dma2d_out_int_st_chn_reg_t out_int_st_ch3;
volatile dma2d_out_int_clr_chn_reg_t out_int_clr_ch3;
volatile dma2d_outfifo_status_chn_reg_t outfifo_status_ch3;
volatile dma2d_out_push_chn_reg_t out_push_ch3;
volatile dma2d_out_link_conf_chn_reg_t out_link_conf_ch3;
volatile dma2d_out_link_addr_chn_reg_t out_link_addr_ch3;
volatile dma2d_out_state_chn_reg_t out_state_ch3;
volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr_ch3;
volatile dma2d_out_dscr_chn_reg_t out_dscr_ch3;
volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0_ch3;
volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1_ch3;
volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel_ch3;
volatile dma2d_out_arb_chn_reg_t out_arb_ch3;
volatile dma2d_out_ro_status_chn_reg_t out_ro_status_ch3;
uint32_t reserved_344;
volatile dma2d_out_color_convert_chn_reg_t out_color_convert_ch3;
volatile dma2d_out_scramble_chn_reg_t out_scramble_ch3;
volatile dma2d_out_color_param0_chn_reg_t out_color_param0_ch3;
volatile dma2d_out_color_param1_chn_reg_t out_color_param1_ch3;
volatile dma2d_out_color_param2_chn_reg_t out_color_param2_ch3;
volatile dma2d_out_color_param3_chn_reg_t out_color_param3_ch3;
volatile dma2d_out_color_param4_chn_reg_t out_color_param4_ch3;
volatile dma2d_out_color_param5_chn_reg_t out_color_param5_ch3;
volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf_ch3;
volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk_ch3;
uint32_t reserved_370[100];
volatile dma2d_in_conf0_chn_reg_t in_conf0_ch0;
volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch0;
volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch0;
volatile dma2d_in_int_st_chn_reg_t in_int_st_ch0;
volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch0;
volatile dma2d_infifo_status_chn_reg_t infifo_status_ch0;
volatile dma2d_in_pop_chn_reg_t in_pop_ch0;
volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch0;
volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch0;
volatile dma2d_in_state_chn_reg_t in_state_ch0;
volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch0;
volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch0;
volatile dma2d_in_dscr_chn_reg_t in_dscr_ch0;
volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch0;
volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch0;
volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch0;
volatile dma2d_in_arb_chn_reg_t in_arb_ch0;
volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch0;
volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf_ch0;
volatile dma2d_in_color_convert_chn_reg_t in_color_convert_ch0;
volatile dma2d_in_scramble_chn_reg_t in_scramble_ch0;
volatile dma2d_in_color_param0_chn_reg_t in_color_param0_ch0;
volatile dma2d_in_color_param1_chn_reg_t in_color_param1_ch0;
volatile dma2d_in_color_param2_chn_reg_t in_color_param2_ch0;
volatile dma2d_in_color_param3_chn_reg_t in_color_param3_ch0;
volatile dma2d_in_color_param4_chn_reg_t in_color_param4_ch0;
volatile dma2d_in_color_param5_chn_reg_t in_color_param5_ch0;
volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch0;
uint32_t reserved_570[36];
volatile dma2d_in_conf0_chn_reg_t in_conf0_ch1;
volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch1;
volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch1;
volatile dma2d_in_int_st_chn_reg_t in_int_st_ch1;
volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch1;
volatile dma2d_infifo_status_chn_reg_t infifo_status_ch1;
volatile dma2d_in_pop_chn_reg_t in_pop_ch1;
volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch1;
volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch1;
volatile dma2d_in_state_chn_reg_t in_state_ch1;
volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch1;
volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch1;
volatile dma2d_in_dscr_chn_reg_t in_dscr_ch1;
volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch1;
volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch1;
volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch1;
volatile dma2d_in_arb_chn_reg_t in_arb_ch1;
volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch1;
uint32_t reserved_648[9];
volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch1;
uint32_t reserved_670[36];
volatile dma2d_in_conf0_chn_reg_t in_conf0_ch2;
volatile dma2d_in_int_raw_chn_reg_t in_int_raw_ch2;
volatile dma2d_in_int_ena_chn_reg_t in_int_ena_ch2;
volatile dma2d_in_int_st_chn_reg_t in_int_st_ch2;
volatile dma2d_in_int_clr_chn_reg_t in_int_clr_ch2;
volatile dma2d_infifo_status_chn_reg_t infifo_status_ch2;
volatile dma2d_in_pop_chn_reg_t in_pop_ch2;
volatile dma2d_in_link_conf_chn_reg_t in_link_conf_ch2;
volatile dma2d_in_link_addr_chn_reg_t in_link_addr_ch2;
volatile dma2d_in_state_chn_reg_t in_state_ch2;
volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr_ch2;
volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr_ch2;
volatile dma2d_in_dscr_chn_reg_t in_dscr_ch2;
volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0_ch2;
volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1_ch2;
volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel_ch2;
volatile dma2d_in_arb_chn_reg_t in_arb_ch2;
volatile dma2d_in_ro_status_chn_reg_t in_ro_status_ch2;
uint32_t reserved_748[9];
volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf_ch2;
uint32_t reserved_770[164];
volatile dma2d_color_param_reg_t param_h;
volatile dma2d_color_param_reg_t param_m;
volatile dma2d_color_param_reg_t param_l;
} dma2d_color_param_group_chn_reg_t;
typedef struct {
volatile dma2d_out_conf0_chn_reg_t out_conf0;
volatile dma2d_out_int_raw_chn_reg_t out_int_raw;
volatile dma2d_out_int_ena_chn_reg_t out_int_ena;
volatile dma2d_out_int_st_chn_reg_t out_int_st;
volatile dma2d_out_int_clr_chn_reg_t out_int_clr;
volatile dma2d_outfifo_status_chn_reg_t outfifo_status;
volatile dma2d_out_push_chn_reg_t out_push;
volatile dma2d_out_link_conf_chn_reg_t out_link_conf;
volatile dma2d_out_link_addr_chn_reg_t out_link_addr;
volatile dma2d_out_state_chn_reg_t out_state;
volatile dma2d_out_eof_des_addr_chn_reg_t out_eof_des_addr;
volatile dma2d_out_dscr_chn_reg_t out_dscr;
volatile dma2d_out_dscr_bf0_chn_reg_t out_dscr_bf0;
volatile dma2d_out_dscr_bf1_chn_reg_t out_dscr_bf1;
volatile dma2d_out_peri_sel_chn_reg_t out_peri_sel;
volatile dma2d_out_arb_chn_reg_t out_arb;
volatile dma2d_out_ro_status_chn_reg_t out_ro_status;
volatile dma2d_out_ro_pd_conf_chn_reg_t out_ro_pd_conf; /* only exist on channel0 */
volatile dma2d_out_color_convert_chn_reg_t out_color_convert;
volatile dma2d_out_scramble_chn_reg_t out_scramble;
volatile dma2d_color_param_group_chn_reg_t out_color_param_group;
volatile dma2d_out_etm_conf_chn_reg_t out_etm_conf;
volatile dma2d_out_dscr_port_blk_chn_reg_t out_dscr_port_blk;
uint32_t reserved_out[36];
} dma2d_out_chn_reg_t;
typedef struct {
volatile dma2d_in_conf0_chn_reg_t in_conf0;
volatile dma2d_in_int_raw_chn_reg_t in_int_raw;
volatile dma2d_in_int_ena_chn_reg_t in_int_ena;
volatile dma2d_in_int_st_chn_reg_t in_int_st;
volatile dma2d_in_int_clr_chn_reg_t in_int_clr;
volatile dma2d_infifo_status_chn_reg_t infifo_status;
volatile dma2d_in_pop_chn_reg_t in_pop;
volatile dma2d_in_link_conf_chn_reg_t in_link_conf;
volatile dma2d_in_link_addr_chn_reg_t in_link_addr;
volatile dma2d_in_state_chn_reg_t in_state;
volatile dma2d_in_suc_eof_des_addr_chn_reg_t in_suc_eof_des_addr;
volatile dma2d_in_err_eof_des_addr_chn_reg_t in_err_eof_des_addr;
volatile dma2d_in_dscr_chn_reg_t in_dscr;
volatile dma2d_in_dscr_bf0_chn_reg_t in_dscr_bf0;
volatile dma2d_in_dscr_bf1_chn_reg_t in_dscr_bf1;
volatile dma2d_in_peri_sel_chn_reg_t in_peri_sel;
volatile dma2d_in_arb_chn_reg_t in_arb;
volatile dma2d_in_ro_status_chn_reg_t in_ro_status;
volatile dma2d_in_ro_pd_conf_chn_reg_t in_ro_pd_conf; /* only exist on channel0 */
volatile dma2d_in_color_convert_chn_reg_t in_color_convert; /* only exist on channel0 */
volatile dma2d_in_scramble_chn_reg_t in_scramble; /* only exist on channel0 */
volatile dma2d_color_param_group_chn_reg_t in_color_param_group; /* only exist on channel0 */
volatile dma2d_in_etm_conf_chn_reg_t in_etm_conf;
uint32_t reserved_in[36];
} dma2d_in_chn_reg_t;
typedef struct dma2d_dev_t {
volatile dma2d_out_chn_reg_t out_channel[4];
uint32_t reserved_400[64];
volatile dma2d_in_chn_reg_t in_channel[3];
uint32_t reserved_800[128];
volatile dma2d_axi_err_reg_t axi_err;
volatile dma2d_rst_conf_reg_t rst_conf;
volatile dma2d_intr_mem_start_addr_reg_t intr_mem_start_addr;
@@ -2058,6 +1954,7 @@ typedef struct {
volatile dma2d_date_reg_t date;
} dma2d_dev_t;
extern dma2d_dev_t DMA2D;
#ifndef __cplusplus
_Static_assert(sizeof(dma2d_dev_t) == 0xa30, "Invalid size of dma2d_dev_t structure");