fix(efuse): Adds missing SOC defines for ESP32-P4 v3

components/efuse/src/efuse_controller/keys/with_key_purposes/esp_efuse_api_key.c

@@ -312,17 +312,17 @@ esp_err_t esp_efuse_write_key(esp_efuse_block_t block, esp_efuse_purpose_t purpo
 #if SOC_EFUSE_ECDSA_KEY
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
 #endif
-#if SOC_EFUSE_ECDSA_KEY_P192
+#if SOC_EFUSE_ECDSA_KEY_P192 || EFUSE_LL_HAS_ECDSA_KEY_P192
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 ||
 #endif
-#if SOC_EFUSE_ECDSA_KEY_P384
+#if SOC_EFUSE_ECDSA_KEY_P384 || EFUSE_LL_HAS_ECDSA_KEY_P384
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L ||
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H ||
 #endif
-#if SOC_PSRAM_ENCRYPTION_XTS_AES_128
+#if SOC_PSRAM_ENCRYPTION_XTS_AES_128 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_128
             purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY ||
 #endif
-#if SOC_PSRAM_ENCRYPTION_XTS_AES_256
+#if SOC_PSRAM_ENCRYPTION_XTS_AES_256 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_256
             purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 ||
             purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 ||
 #endif

components/efuse/test_apps/.build-test-rules.yml

@@ -3,10 +3,6 @@
 components/efuse/test_apps:
   enable:
     - if: (INCLUDE_DEFAULT == 1 and SOC_EFUSE_SUPPORTED == 1) or IDF_TARGET == "linux")
-  disable:
-    - if: IDF_TARGET == "esp32p4"
-      temporary: true
-      reason: p4 rev3 migration # TODO: IDF-14403
   disable_test:
     - if: IDF_TARGET in ["esp32s2", "esp32s3"]
       reason: eFuse for S2 and S3 is similar to the C3 chip, so we only test for C3.

components/efuse/test_apps/README.md

@@ -1,3 +1,3 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-S2 | ESP32-S3 | Linux |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | ----- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | Linux |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | ----- |
 

components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c

@@ -14,6 +14,7 @@
 #include "esp_efuse.h"
 #include "esp_efuse_table.h"
 #include "esp_efuse_utility.h"
+#include "hal/efuse_ll.h"
 #include "sdkconfig.h"
 
 ESP_LOG_ATTR_TAG(TAG, "efuse_key_test");
@@ -93,17 +94,17 @@ static esp_err_t s_check_key(esp_efuse_block_t num_key, void* wr_key)
 #if SOC_EFUSE_ECDSA_KEY
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
 #endif
-#if SOC_EFUSE_ECDSA_KEY_P192
+#if SOC_EFUSE_ECDSA_KEY_P192 || EFUSE_LL_HAS_ECDSA_KEY_P192
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 ||
 #endif
-#if SOC_EFUSE_ECDSA_KEY_P384
+#if SOC_EFUSE_ECDSA_KEY_P384 || EFUSE_LL_HAS_ECDSA_KEY_P384
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L ||
             purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H ||
 #endif
-#if SOC_PSRAM_ENCRYPTION_XTS_AES_128
+#if SOC_PSRAM_ENCRYPTION_XTS_AES_128 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_128
             purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY ||
 #endif
-#if SOC_PSRAM_ENCRYPTION_XTS_AES_256
+#if SOC_PSRAM_ENCRYPTION_XTS_AES_256 || EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_256
             purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 ||
             purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 ||
 #endif

components/hal/esp32p4/include/hal/efuse_ll.h

@@ -11,6 +11,7 @@
 #include "soc/efuse_periph.h"
 #include "hal/assert.h"
 #include "rom/efuse.h"
+#include "hal/config.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -25,6 +26,25 @@ typedef enum {
     EFUSE_CONTROLLER_STATE_READ_RS_BLK      = 5,    ///< efuse_controllerid is on reading RS block state.
 } efuse_controller_state_t;
 
+/* Revision-aware eFuse feature macros
+ *
+ * These macros indicate whether an eFuse feature is available given the
+ * configured minimum supported chip revision (HAL_CONFIG(CHIP_SUPPORT_MIN_REV)).
+ * Use them when a feature's presence depends on the chosen minimum revision.
+ *
+ * Note: SOC_* capability macros describe silicon capabilities; these
+ * EFUSE_LL_HAS_* macros reflect availability relative to the configured min revision.
+ * If a feature is present in silicon and does not depend on the chip revision,
+ * then add SOC_* macro in soc_caps.h instead.
+ */
+#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
+// Rev 3.00+: key_purpose fields expanded from 4 to 5 bits, enabling additional key types.
+#define EFUSE_LL_HAS_ECDSA_KEY_P192    (1)
+#define EFUSE_LL_HAS_ECDSA_KEY_P384    (1)
+#define EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_128  (1)
+#define EFUSE_LL_HAS_PSRAM_ENCRYPTION_XTS_AES_256  (1)
+#endif
+
 // Always inline these functions even no gcc optimization is applied.
 
 /******************* eFuse fields *************************/
@@ -91,7 +111,6 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(
     return EFUSE.rd_mac_sys_2.pkg_version;
 }
 
-
 /******************* eFuse control functions *************************/
 
 __attribute__((always_inline)) static inline bool efuse_ll_get_read_cmd(void)

components/soc/esp32p4/include/soc/soc_caps.h

@@ -661,6 +661,7 @@
 #define SOC_FLASH_ENCRYPTION_XTS_AES_OPTIONS 1
 #define SOC_FLASH_ENCRYPTION_XTS_AES_128    1  /* SOC_EFUSE_XTS_AES_KEY_128 (1) || SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_128 (1) */
 #define SOC_FLASH_ENCRYPTION_XTS_AES_256    1  /* SOC_EFUSE_XTS_AES_KEY_256 (1) || SOC_KEY_MANAGER_FE_KEY_DEPLOY_XTS_AES_256 (1) */
+
 /*-------------------------- MEMPROT CAPS ------------------------------------*/
 
 /*-------------------------- UART CAPS ---------------------------------------*/