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feat(etm): add ETM LL and GPIO ETM support on esp32s31

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Enable ETM caps and add S31 ETM/GPIO LL and retention support for
GPTimer ETM builds.
This commit is contained in:
morris
2026-04-03 19:16:28 +08:00
parent 953c40c9aa
commit 43bc8c2fe5
56 changed files with 754 additions and 1268 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_driver_dma/test_apps/dma/main/test_gdma_etm.c
+1
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@@ -84,6 +84,7 @@ TEST_CASE("async_memcpy_eof_event", "[GDMA][ETM]")
TEST_ESP_OK(esp_etm_del_event(mcp_event));
TEST_ESP_OK(esp_etm_del_channel(etm_channel_a));
TEST_ESP_OK(esp_async_memcpy_uninstall(mcp_ctx));
TEST_ESP_OK(gpio_reset_pin(output_gpio));
free(src_buf);
free(dst_buf);
}
components/esp_hal_gpio/esp32s31/include/hal/gpio_caps.h
+3
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@@ -7,3 +7,6 @@
#pragma once
#define GPIO_CAPS_GET(_attr) _GPIO_ ## _attr
#define _GPIO_ETM_EVENT_CHANNELS_PER_GROUP 8
#define _GPIO_ETM_TASK_CHANNELS_PER_GROUP 8
components/esp_hal_gpio/esp32s31/include/hal/gpio_etm_ll.h
+133
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@@ -0,0 +1,133 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdbool.h>
#include "hal/assert.h"
#include "hal/misc.h"
#include "soc/gpio_ext_struct.h"
#include "soc/soc_etm_source.h"
#define GPIO_LL_ETM_EVENT_ID_POS_EDGE(ch) (GPIO_EVT_CH0_RISE_EDGE + (ch))
#define GPIO_LL_ETM_EVENT_ID_NEG_EDGE(ch) (GPIO_EVT_CH0_FALL_EDGE + (ch))
#define GPIO_LL_ETM_EVENT_ID_ANY_EDGE(ch) (GPIO_EVT_CH0_ANY_EDGE + (ch))
#define GPIO_LL_ETM_TASK_ID_SET(ch) (GPIO_TASK_CH0_SET + (ch))
#define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch))
#define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch))
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Set which GPIO to be bound to the event channel
*
* @note Different channels can be bound to one GPIO
*
* @param dev Register base address
* @param chan GPIO ETM Event channel number
* @param gpio_num GPIO number
*/
static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num)
{
dev->etm_event_chn_cfg[chan].etm_chn_event_sel = gpio_num;
}
/**
* @brief Whether to enable the event channel
*
* @param dev Register base address
* @param chan GPIO ETM Event channel number
* @param enable True to enable, false to disable
*/
static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable)
{
dev->etm_event_chn_cfg[chan].etm_chn_event_en = enable;
}
/**
* @brief Get which GPIO is bound to the event channel
*
* @param dev Register base address
* @param chan GPIO ETM Event channel number
* @return GPIO number
*/
static inline uint32_t gpio_ll_etm_event_channel_get_gpio(gpio_etm_dev_t *dev, uint32_t chan)
{
return dev->etm_event_chn_cfg[chan].etm_chn_event_sel;
}
/**
* @brief Set which GPIO to be bound to the task channel
*
* @note One channel can be bound to multiple different GPIOs
*
* @param dev Register base address
* @param chan GPIO ETM Task channel number
* @param gpio_num GPIO number
*/
static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan)
{
int g_p = gpio_num / 5;
int g_idx = gpio_num % 5;
uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val;
reg_val &= ~(0x07 << (g_idx * 6));
reg_val |= ((chan & 0x07) << (g_idx * 6));
dev->etm_task_pn_cfg[g_p].val = reg_val;
}
/**
* @brief Whether to enable the GPIO to be managed by the task channel
*
* @param dev Register base address
* @param gpio_num GPIO number
* @param enable True to enable, false to disable
*/
static inline void gpio_ll_etm_enable_task_gpio(gpio_etm_dev_t *dev, uint32_t gpio_num, bool enable)
{
int g_p = gpio_num / 5;
int g_idx = gpio_num % 5;
uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val;
reg_val &= ~(0x01 << (g_idx * 6 + 5));
reg_val |= ((enable & 0x01) << (g_idx * 6 + 5));
dev->etm_task_pn_cfg[g_p].val = reg_val;
}
/**
* @brief Check whether a GPIO has been enabled and managed by a task channel
*
* @param dev Register base address
* @param gpio_num GPIO number
* @return True if enabled, false otherwise
*/
static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_t gpio_num)
{
int g_p = gpio_num / 5;
int g_idx = gpio_num % 5;
return dev->etm_task_pn_cfg[g_p].val & (0x01 << (g_idx * 6 + 5));
}
/**
* @brief Get the channel number that the GPIO is bound to
*
* @param dev Register base address
* @param gpio_num GPIO number
* @return GPIO ETM Task channel number
*/
static inline uint32_t gpio_ll_etm_gpio_get_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num)
{
int g_p = gpio_num / 5;
int g_idx = gpio_num % 5;
return (dev->etm_task_pn_cfg[g_p].val >> (g_idx * 6)) & 0x07;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_systimer/esp32c5/rom.systimer.ld
+2 -3
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@@ -9,9 +9,8 @@
***************************************/
/* Functions */
/* The following ROM functions are commented out because they're patched in the rom_patch.c */
/* systimer_hal_init = 0x400003d0; */
/* systimer_hal_deinit = 0x400003d4; */
rom_systimer_hal_init = 0x400003d0;
rom_systimer_hal_deinit = 0x400003d4;
systimer_hal_set_tick_rate_ops = 0x400003d8;
systimer_hal_get_counter_value = 0x400003dc;
systimer_hal_get_time = 0x400003e0;
components/esp_hal_systimer/esp32c6/rom.systimer.ld
+2 -3
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@@ -9,9 +9,8 @@
***************************************/
/* Functions */
/* The following ROM functions are commented out because they're patched in the rom_patch.c */
/* systimer_hal_init = 0x400003c0; */
/* systimer_hal_deinit = 0x400003c4; */
rom_systimer_hal_init = 0x400003c0;
rom_systimer_hal_deinit = 0x400003c4;
systimer_hal_set_tick_rate_ops = 0x400003c8;
systimer_hal_get_counter_value = 0x400003cc;
components/esp_hal_systimer/esp32c61/rom.systimer.ld
+2 -3
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@@ -10,9 +10,8 @@
/* Functions */
/* The following ROM functions are commented out because they're patched in the rom_patch.c */
/* systimer_hal_init = 0x400003d0; */
/* systimer_hal_deinit = 0x400003d4; */
rom_systimer_hal_init = 0x400003d0;
rom_systimer_hal_deinit = 0x400003d4;
systimer_hal_set_tick_rate_ops = 0x400003d8;
systimer_hal_get_counter_value = 0x400003dc;
components/esp_hal_systimer/esp32h2/rom.systimer.ld
+2 -3
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@@ -9,9 +9,8 @@
***************************************/
/* Functions */
/* The following ROM functions are commented out because they're patched in the rom_patch.c */
/* systimer_hal_init = 0x400003b8; */
/* systimer_hal_deinit = 0x400003bc; */
rom_systimer_hal_init = 0x400003b8;
rom_systimer_hal_deinit = 0x400003bc;
systimer_hal_set_tick_rate_ops = 0x400003c0;
systimer_hal_get_counter_value = 0x400003c4;
components/esp_hal_systimer/esp32h21/rom.systimer.ld
+2 -3
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@@ -9,9 +9,8 @@
***************************************/
/* Functions */
/* The following ROM functions are commented out because they're patched in the rom_patch.c */
/* systimer_hal_init = 0x400003b8; */
/* systimer_hal_deinit = 0x400003bc; */
rom_systimer_hal_init = 0x400003b8;
rom_systimer_hal_deinit = 0x400003bc;
systimer_hal_set_tick_rate_ops = 0x400003c0;
systimer_hal_get_counter_value = 0x400003c4;
systimer_hal_get_time = 0x400003c8;
components/esp_hal_systimer/esp32h4/rom.systimer.ld
+2 -3
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@@ -18,9 +18,8 @@
***************************************/
/* Functions */
/* The following ROM functions are commented out because they're patched in the rom_patch.c */
/* systimer_hal_init = 0x4000036c; */
/* systimer_hal_deinit = 0x40000370; */
rom_systimer_hal_init = 0x4000036c;
rom_systimer_hal_deinit = 0x40000370;
systimer_hal_set_tick_rate_ops = 0x40000374;
systimer_hal_get_counter_value = 0x40000378;
components/esp_hal_systimer/esp32p4/rom.systimer.ld
+2 -3
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@@ -10,9 +10,8 @@
***************************************/
/* Functions */
/* The following ROM functions are commented out because they're patched in the rom_patch.c */
/* systimer_hal_init = 0x4fc00228; */
/* systimer_hal_deinit = 0x4fc0022c; */
rom_systimer_hal_init = 0x4fc00228;
rom_systimer_hal_deinit = 0x4fc0022c;
systimer_hal_set_tick_rate_ops = 0x4fc00230;
systimer_hal_get_counter_value = 0x4fc00234;
systimer_hal_get_time = 0x4fc00238;
components/esp_hal_systimer/esp32s31/rom.systimer.ld
+2 -2
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@@ -18,8 +18,8 @@
***************************************/
/* Functions */
systimer_hal_init = 0x2f800394;
systimer_hal_deinit = 0x2f800398;
rom_systimer_hal_init = 0x2f800394;
rom_systimer_hal_deinit = 0x2f800398;
systimer_hal_set_tick_rate_ops = 0x2f80039c;
systimer_hal_get_counter_value = 0x2f8003a0;
systimer_hal_get_time = 0x2f8003a4;
components/esp_hal_systimer/rom_patch.c
+11 -10
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@@ -9,10 +9,6 @@
*
* Some chips have systimer HAL implementations in ROM that require patches.
* This file provides the necessary patches when ROM implementation is used.
*
* For chips with ESP_ROM_SYSTIMER_INIT_PATCH defined (e.g., ESP32-C5, ESP32-C6,
* ESP32-H2, ESP32-P4), the ROM systimer_hal_init/deinit functions do not
* enable ETM, so we need to patch them here.
*/
#include <stddef.h>
@@ -20,18 +16,23 @@
#include "hal/systimer_hal.h"
#include "hal/systimer_ll.h"
#if ESP_ROM_SYSTIMER_INIT_PATCH
#if !CONFIG_IDF_TARGET_ESP32C2 // esp32c2 has dedicated ROM patch
extern void rom_systimer_hal_init(systimer_hal_context_t *hal);
extern void rom_systimer_hal_deinit(systimer_hal_context_t *hal);
void systimer_hal_init(systimer_hal_context_t *hal)
{
hal->dev = &SYSTIMER;
systimer_ll_enable_clock(hal->dev, true);
// For chips with ROM systimer that does not enable ETM, the ROM functions are
// exposed with "rom_" prefix in rom.systimer.ld. We wrap them here to add
// the missing systimer_ll_enable_etm() call.
rom_systimer_hal_init(hal);
systimer_ll_enable_etm(&SYSTIMER, true);
}
void systimer_hal_deinit(systimer_hal_context_t *hal)
{
systimer_ll_enable_etm(&SYSTIMER, false);
systimer_ll_enable_clock(hal->dev, false);
hal->dev = NULL;
rom_systimer_hal_deinit(hal);
}
#endif // ESP_ROM_SYSTIMER_INIT_PATCH
#endif // !CONFIG_IDF_TARGET_ESP32C2
components/esp_hw_support/etm/esp_etm.c
+10
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@@ -113,6 +113,7 @@ static etm_group_t *etm_acquire_group_handle(int group_id)
PERIPH_RCC_ATOMIC() {
etm_ll_enable_bus_clock(group_id, true);
etm_ll_reset_register(group_id);
etm_ll_enable_function_clock(group_id, true);
}
#if ETM_USE_RETENTION_LINK
@@ -257,6 +258,15 @@ esp_err_t esp_etm_new_channel(const esp_etm_channel_config_t *config, esp_etm_ch
int group_id = group->group_id;
int chan_id = chan->chan_id;
#if ETM_LL_SUPPORT(CLOCK_SRC)
// set the clock source for the ETM group
etm_clock_source_t clk_src = config->clk_src;
if (clk_src == 0) {
clk_src = ETM_CLK_SRC_DEFAULT;
}
etm_ll_set_clock_source(group_id, clk_src);
#endif
// set the initial state to INIT
atomic_init(&chan->fsm, ETM_CHAN_FSM_INIT);
components/esp_hw_support/etm/include/esp_etm.h
+2
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@@ -8,6 +8,7 @@
#include <stdint.h>
#include <stdio.h>
#include "esp_err.h"
#include "hal/etm_types.h"
#ifdef __cplusplus
extern "C" {
@@ -32,6 +33,7 @@ typedef struct esp_etm_task_t *esp_etm_task_handle_t;
* @brief ETM channel configuration
*/
typedef struct {
etm_clock_source_t clk_src; /*!< Clock source for the ETM channel */
/// Extra configuration flags for ETM channel
struct etm_chan_flags {
uint32_t allow_pd : 1; /*!< If set, driver allows the power domain to be powered off when system enters sleep mode.
components/esp_rom/esp32c5/Kconfig.soc_caps.in
-4
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@@ -43,10 +43,6 @@ config ESP_ROM_HAS_HAL_SYSTIMER
bool
default y
config ESP_ROM_SYSTIMER_INIT_PATCH
bool
default y
config ESP_ROM_HAS_HEAP_TLSF
bool
default y
components/esp_rom/esp32c5/esp_rom_caps.h
-1
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@@ -16,7 +16,6 @@
#define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib
#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver
#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver
#define ESP_ROM_SYSTIMER_INIT_PATCH (1) // ROM version initializes SYSTIMER without ETM
#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library
#define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check_pool()
#define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk()
components/esp_rom/esp32c6/Kconfig.soc_caps.in
-4
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@@ -43,10 +43,6 @@ config ESP_ROM_HAS_HAL_SYSTIMER
bool
default y
config ESP_ROM_SYSTIMER_INIT_PATCH
bool
default y
config ESP_ROM_HAS_HEAP_TLSF
bool
default y
components/esp_rom/esp32c6/esp_rom_caps.h
-1
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@@ -16,7 +16,6 @@
#define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib
#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver
#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver
#define ESP_ROM_SYSTIMER_INIT_PATCH (1) // ROM version initializes SYSTIMER without ETM
#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library
#define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check_pool()
#define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk()
components/esp_rom/esp32c61/Kconfig.soc_caps.in
-4
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@@ -43,10 +43,6 @@ config ESP_ROM_HAS_HAL_SYSTIMER
bool
default y
config ESP_ROM_SYSTIMER_INIT_PATCH
bool
default y
config ESP_ROM_HAS_HEAP_TLSF
bool
default y
components/esp_rom/esp32c61/esp_rom_caps.h
-1
View File
@@ -16,7 +16,6 @@
#define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib
#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver
#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver
#define ESP_ROM_SYSTIMER_INIT_PATCH (1) // ROM version initializes SYSTIMER without ETM
#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library
#define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check_pool()
#define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk()
components/esp_rom/esp32h2/Kconfig.soc_caps.in
-4
View File
@@ -35,10 +35,6 @@ config ESP_ROM_HAS_HAL_SYSTIMER
bool
default y
config ESP_ROM_SYSTIMER_INIT_PATCH
bool
default y
config ESP_ROM_HAS_HEAP_TLSF
bool
default y
components/esp_rom/esp32h2/esp_rom_caps.h
-1
View File
@@ -14,7 +14,6 @@
#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver
#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver
#define ESP_ROM_SYSTIMER_INIT_PATCH (1) // ROM version initializes SYSTIMER without ETM
#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library
#define ESP_ROM_TLSF_CHECK_PATCH (1) // ROM does not contain the patch of tlsf_check_pool()
#define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk()
components/esp_rom/esp32h21/Kconfig.soc_caps.in
-4
View File
@@ -35,10 +35,6 @@ config ESP_ROM_HAS_HAL_SYSTIMER
bool
default y
config ESP_ROM_SYSTIMER_INIT_PATCH
bool
default y
config ESP_ROM_HAS_HEAP_TLSF
bool
default y
components/esp_rom/esp32h21/esp_rom_caps.h
-1
View File
@@ -14,7 +14,6 @@
#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver
#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver
#define ESP_ROM_SYSTIMER_INIT_PATCH (1) // ROM version initializes SYSTIMER without ETM
#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library
#define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk()
#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table
components/esp_rom/esp32h4/Kconfig.soc_caps.in
-4
View File
@@ -35,10 +35,6 @@ config ESP_ROM_HAS_HAL_SYSTIMER
bool
default y
config ESP_ROM_SYSTIMER_INIT_PATCH
bool
default y
config ESP_ROM_HAS_HEAP_TLSF
bool
default y
components/esp_rom/esp32h4/esp_rom_caps.h
-1
View File
@@ -14,7 +14,6 @@
#define ESP_ROM_GET_CLK_FREQ (1) // Get clk frequency with rom function `ets_get_cpu_frequency`
#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver
#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver
#define ESP_ROM_SYSTIMER_INIT_PATCH (1) // ROM version initializes SYSTIMER without ETM
#define ESP_ROM_HAS_HEAP_TLSF (1) // ROM has the implementation of the tlsf and multi-heap library
#define ESP_ROM_MULTI_HEAP_WALK_PATCH (1) // ROM does not contain the patch of multi_heap_walk()
#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table
components/esp_rom/esp32p4/Kconfig.soc_caps.in
-4
View File
@@ -43,10 +43,6 @@ config ESP_ROM_HAS_HAL_SYSTIMER
bool
default y
config ESP_ROM_SYSTIMER_INIT_PATCH
bool
default y
config ESP_ROM_HAS_LAYOUT_TABLE
bool
default y
components/esp_rom/esp32p4/esp_rom_caps.h
-1
View File
@@ -16,7 +16,6 @@
#define ESP_ROM_HAS_RVFPLIB (1) // ROM has the rvfplib
#define ESP_ROM_HAS_HAL_WDT (1) // ROM has the implementation of Watchdog HAL driver
#define ESP_ROM_HAS_HAL_SYSTIMER (1) // ROM has the implementation of Systimer HAL driver
#define ESP_ROM_SYSTIMER_INIT_PATCH (1) // ROM version initializes SYSTIMER without ETM
#define ESP_ROM_HAS_LAYOUT_TABLE (1) // ROM has the layout table
#define ESP_ROM_WDT_INIT_PATCH (1) // ROM version does not configure the clock
#define ESP_ROM_HAS_LP_ROM (1) // ROM also has a LP ROM placed in LP memory
components/esp_system/test_apps/esp_system_unity_tests/main/test_systick_etm.c
+1
View File
@@ -60,4 +60,5 @@ TEST_CASE("rtos_systick_etm_event", "[etm]")
TEST_ESP_OK(esp_etm_del_event(systick_event));
TEST_ESP_OK(esp_etm_channel_disable(etm_channel_a));
TEST_ESP_OK(esp_etm_del_channel(etm_channel_a));
TEST_ESP_OK(gpio_reset_pin(output_gpio));
}
components/hal/esp32c5/include/hal/etm_ll.h
+25
View File
@@ -11,6 +11,7 @@
#include <stdbool.h>
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/etm_types.h"
#include "soc/soc_etm_struct.h"
#include "soc/pcr_struct.h"
@@ -42,6 +43,30 @@ static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
PCR.etm_conf.etm_clk_en = enable;
}
/**
* @brief Enable the clock for ETM function
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void etm_ll_enable_function_clock(int group_id, bool enable)
{
(void)group_id;
(void)enable;
}
/**
* @brief Set the clock source for ETM
*
* @param group_id Group ID
* @param clk_src Clock source
*/
static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src)
{
(void)group_id;
(void)clk_src;
}
/**
* @brief Reset the ETM register
*
components/hal/esp32c6/include/hal/etm_ll.h
+25
View File
@@ -11,6 +11,7 @@
#include <stdbool.h>
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/etm_types.h"
#include "soc/soc_etm_struct.h"
#include "soc/pcr_struct.h"
@@ -39,6 +40,30 @@ static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
PCR.etm_conf.etm_clk_en = enable;
}
/**
* @brief Enable the clock for ETM function
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void etm_ll_enable_function_clock(int group_id, bool enable)
{
(void)group_id;
(void)enable;
}
/**
* @brief Set the clock source for ETM
*
* @param group_id Group ID
* @param clk_src Clock source
*/
static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src)
{
(void)group_id;
(void)clk_src;
}
/**
* @brief Reset the ETM register
*
components/hal/esp32c61/include/hal/etm_ll.h
+25
View File
@@ -11,6 +11,7 @@
#include <stdbool.h>
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/etm_types.h"
#include "soc/soc_etm_struct.h"
#include "soc/pcr_struct.h"
@@ -42,6 +43,30 @@ static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
PCR.etm_conf.etm_clk_en = enable;
}
/**
* @brief Enable the clock for ETM function
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void etm_ll_enable_function_clock(int group_id, bool enable)
{
(void)group_id;
(void)enable;
}
/**
* @brief Set the clock source for ETM
*
* @param group_id Group ID
* @param clk_src Clock source
*/
static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src)
{
(void)group_id;
(void)clk_src;
}
/**
* @brief Reset the ETM register
*
components/hal/esp32h2/include/hal/etm_ll.h
+25
View File
@@ -11,6 +11,7 @@
#include <stdbool.h>
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/etm_types.h"
#include "soc/soc_etm_struct.h"
#include "soc/pcr_struct.h"
@@ -39,6 +40,30 @@ static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
PCR.etm_conf.etm_clk_en = enable;
}
/**
* @brief Enable the clock for ETM function
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void etm_ll_enable_function_clock(int group_id, bool enable)
{
(void)group_id;
(void)enable;
}
/**
* @brief Set the clock source for ETM
*
* @param group_id Group ID
* @param clk_src Clock source
*/
static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src)
{
(void)group_id;
(void)clk_src;
}
/**
* @brief Reset the ETM register
*
components/hal/esp32h21/include/hal/etm_ll.h
+25
View File
@@ -11,6 +11,7 @@
#include <stdbool.h>
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/etm_types.h"
#include "soc/soc_etm_struct.h"
#include "soc/pcr_struct.h"
@@ -39,6 +40,30 @@ static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
PCR.etm_conf.etm_clk_en = enable;
}
/**
* @brief Enable the clock for ETM function
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void etm_ll_enable_function_clock(int group_id, bool enable)
{
(void)group_id;
(void)enable;
}
/**
* @brief Set the clock source for ETM
*
* @param group_id Group ID
* @param clk_src Clock source
*/
static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src)
{
(void)group_id;
(void)clk_src;
}
/**
* @brief Reset the ETM register
*
components/hal/esp32h4/include/hal/etm_ll.h
+25
View File
@@ -11,6 +11,7 @@
#include <stdbool.h>
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/etm_types.h"
#include "soc/soc_etm_struct.h"
#include "soc/pcr_struct.h"
@@ -42,6 +43,30 @@ static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
PCR.etm_conf.etm_clk_en = enable;
}
/**
* @brief Enable the clock for ETM function
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void etm_ll_enable_function_clock(int group_id, bool enable)
{
(void)group_id;
(void)enable;
}
/**
* @brief Set the clock source for ETM
*
* @param group_id Group ID
* @param clk_src Clock source
*/
static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src)
{
(void)group_id;
(void)clk_src;
}
/**
* @brief Reset the ETM register
*
components/hal/esp32p4/include/hal/etm_ll.h
+25
View File
@@ -11,6 +11,7 @@
#include <stdbool.h>
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/etm_types.h"
#include "soc/soc_etm_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
@@ -50,6 +51,30 @@ static inline void _etm_ll_enable_bus_clock(int group_id, bool enable)
_etm_ll_enable_bus_clock(__VA_ARGS__); \
} while(0)
/**
* @brief Enable the clock for ETM function
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void etm_ll_enable_function_clock(int group_id, bool enable)
{
(void)group_id;
(void)enable;
}
/**
* @brief Set the clock source for ETM
*
* @param group_id Group ID
* @param clk_src Clock source
*/
static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src)
{
(void)group_id;
(void)clk_src;
}
/**
* @brief Reset the ETM module
*
components/hal/esp32s31/etm_periph.c
+44
View File
@@ -0,0 +1,44 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "hal/etm_periph.h"
#include "soc/soc_etm_reg.h"
/**
* ETM Registers to be saved during sleep retention
* - Channel configuration registers, e.g.: SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_TASK_ID_REG
*/
#define ETM_RETENTION_REGS_CNT ((SOC_ETM_CH49_TASK_ID_REG - SOC_ETM_CH0_EVT_ID_REG) / 4 + 1)
static const regdma_entries_config_t etm_regdma_entries[] = {
// backup stage: save the status of enabled channels
// restore stage: store the enabled channels
[0] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x00),
SOC_ETM_CH_ENA_AD0_REG, SOC_ETM_CH_ENA_AD0_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
[1] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x01),
SOC_ETM_CH_ENA_AD1_REG, SOC_ETM_CH_ENA_AD1_SET_REG, 1, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[2] = {
.config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_ETM_LINK(0x02),
SOC_ETM_CH0_EVT_ID_REG, SOC_ETM_CH0_EVT_ID_REG, ETM_RETENTION_REGS_CNT, 0, 0),
.owner = ENTRY(0) | ENTRY(2),
},
};
const soc_etm_retention_desc_t soc_etm_retention_info[1] = {
[0] = {
.module = SLEEP_RETENTION_MODULE_ETM0,
.regdma_entry_array = etm_regdma_entries,
.array_size = ARRAY_SIZE(etm_regdma_entries)
},
};
components/hal/esp32s31/include/hal/etm_ll.h
+169
View File
@@ -0,0 +1,169 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdbool.h>
#include "hal/assert.h"
#include "hal/misc.h"
#include "hal/etm_types.h"
#include "soc/soc_etm_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#define ETM_LL_GET(_attr) ETM_LL_ ## _attr
#define ETM_LL_SUPPORT(_feat) ETM_LL_SUPPORT_ ## _feat
// Number of ETM instances
#define ETM_LL_INST_NUM 1
// Number of channels in each ETM instance
#define ETM_LL_CHANS_PER_INST 50
// Support to get and clear the status of the ETM event and task
#define ETM_LL_SUPPORT_STATUS_REG 1
// Support to set the clock source for ETM
#define ETM_LL_SUPPORT_CLOCK_SRC 1
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Enable the clock for ETM register
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
{
(void)group_id;
HP_SYS_CLKRST.etm_ctrl0.reg_etm_apb_clk_en = enable;
}
/**
* @brief Enable the clock for ETM function
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void etm_ll_enable_function_clock(int group_id, bool enable)
{
(void)group_id;
HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_en = enable;
}
/**
* @brief Set the clock source for ETM
*
* @param group_id Group ID
* @param clk_src Clock source
*/
static inline void etm_ll_set_clock_source(int group_id, etm_clock_source_t clk_src)
{
(void)group_id;
switch (clk_src) {
case ETM_CLK_SRC_XTAL:
HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_sel = 0;
break;
case ETM_CLK_SRC_RC_FAST:
HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_sel = 1;
break;
case ETM_CLK_SRC_PLL_F80M:
HP_SYS_CLKRST.etm_ctrl0.reg_soc_etm_clk_sel = 2;
break;
default:
HAL_ASSERT(false);
}
}
/**
* @brief Reset the ETM register
*
* @param group_id Group ID
*/
static inline void etm_ll_reset_register(int group_id)
{
(void)group_id;
HP_SYS_CLKRST.etm_ctrl0.reg_etm_rst_en = 1;
HP_SYS_CLKRST.etm_ctrl0.reg_etm_rst_en = 0;
}
/**
* @brief Enable ETM channel
*
* @param hw ETM register base address
* @param chan Channel ID
*/
static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan)
{
if (chan < 32) {
hw->ch_ena_ad0_set.val = 1 << chan;
} else {
hw->ch_ena_ad1_set.val = 1 << (chan - 32);
}
}
/**
* @brief Disable ETM channel
*
* @param hw ETM register base address
* @param chan Channel ID
*/
static inline void etm_ll_disable_channel(soc_etm_dev_t *hw, uint32_t chan)
{
if (chan < 32) {
hw->ch_ena_ad0_clr.val = 1 << chan;
} else {
hw->ch_ena_ad1_clr.val = 1 << (chan - 32);
}
}
/**
* @brief Check whether the ETM channel is enabled or not
*
* @param hw ETM register base address
* @param chan Channel ID
* @return true if the channel is enabled, false otherwise
*/
static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan)
{
if (chan < 32) {
return hw->ch_ena_ad0.val & (1 << chan);
} else {
return hw->ch_ena_ad1.val & (1 << (chan - 32));
}
}
/**
* @brief Set the input event for the ETM channel
*
* @param hw ETM register base address
* @param chan Channel ID
* @param event Event ID
*/
static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event)
{
hw->channel[chan].eid.chn_evt_id = event;
}
/**
* @brief Set the output task for the ETM channel
*
* @param hw ETM register base address
* @param chan Channel ID
* @param task Task ID
*/
static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task)
{
hw->channel[chan].tid.chn_task_id = task;
}
#ifdef __cplusplus
}
#endif
components/hal/include/hal/etm_types.h
+31
View File
@@ -0,0 +1,31 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_ETM_SUPPORTED
/**
* @brief ETM clock source
* @note User should select the clock source based on the power and resolution requirement
*/
typedef soc_periph_etm_clk_src_t etm_clock_source_t;
#else
/**
* @brief Default type
*/
typedef int etm_clock_source_t;
#endif
#ifdef __cplusplus
}
#endif
components/soc/esp32c5/include/soc/clk_tree_defs.h
+7
View File
@@ -193,6 +193,13 @@ typedef enum {
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} soc_periph_gptimer_clk_src_t;
//////////////////////////////////////////////////ETM///////////////////////////////////////////////////////////////////
/**
* @brief Type of ETM clock source
*/
typedef int soc_periph_etm_clk_src_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**
components/soc/esp32c6/include/soc/clk_tree_defs.h
+7
View File
@@ -190,6 +190,13 @@ typedef enum {
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} soc_periph_gptimer_clk_src_t;
//////////////////////////////////////////////////ETM///////////////////////////////////////////////////////////////////
/**
* @brief Type of ETM clock source
*/
typedef int soc_periph_etm_clk_src_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**
components/soc/esp32c61/include/soc/clk_tree_defs.h
+7
View File
@@ -180,6 +180,13 @@ typedef enum {
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} soc_periph_gptimer_clk_src_t;
//////////////////////////////////////////////////ETM///////////////////////////////////////////////////////////////////
/**
* @brief Type of ETM clock source
*/
typedef int soc_periph_etm_clk_src_t;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
/**
components/soc/esp32h2/include/soc/clk_tree_defs.h
+7
View File
@@ -199,6 +199,13 @@ typedef enum {
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default choice */
} soc_periph_gptimer_clk_src_t;
//////////////////////////////////////////////////ETM///////////////////////////////////////////////////////////////////
/**
* @brief Type of ETM clock source
*/
typedef int soc_periph_etm_clk_src_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**
components/soc/esp32h21/include/soc/clk_tree_defs.h
+7
View File
@@ -188,6 +188,13 @@ typedef enum {
#endif
} soc_periph_gptimer_clk_src_t;
//////////////////////////////////////////////////ETM///////////////////////////////////////////////////////////////////
/**
* @brief Type of ETM clock source
*/
typedef int soc_periph_etm_clk_src_t;
//////////////////////////////////////////////////SDM///////////////////////////////////////////////////////////////////
/**
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
-16
View File
@@ -363,14 +363,6 @@ config SOC_GDMA_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_ETM_GROUPS
int
default 1
config SOC_ETM_CHANNELS_PER_GROUP
int
default 50
config SOC_MODEM_SUPPORT_ETM
bool
default y
@@ -403,14 +395,6 @@ config SOC_GPIO_SUPPORT_ETM
bool
default y
config SOC_GPIO_ETM_EVENTS_PER_GROUP
int
default 8
config SOC_GPIO_ETM_TASKS_PER_GROUP
int
default 8
config SOC_LP_IO_CLOCK_IS_INDEPENDENT
bool
default y
components/soc/esp32h4/include/soc/clk_tree_defs.h
+7
View File
@@ -190,6 +190,13 @@ typedef enum {
#endif
} soc_periph_gptimer_clk_src_t;
//////////////////////////////////////////////////ETM///////////////////////////////////////////////////////////////////
/**
* @brief Type of ETM clock source
*/
typedef int soc_periph_etm_clk_src_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**
components/soc/esp32h4/include/soc/soc_caps.h
-6
View File
@@ -196,10 +196,6 @@
#define SOC_GDMA_SUPPORT_ETM 1 // Support ETM submodule
#define SOC_GDMA_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- ETM CAPS --------------------------------------*/
#define SOC_ETM_GROUPS 1U // Number of ETM groups
#define SOC_ETM_CHANNELS_PER_GROUP 50 // Number of ETM channels in the group
/*-------------------------- MODEM CAPS --------------------------------------*/
#define SOC_MODEM_SUPPORT_ETM 1
@@ -217,8 +213,6 @@
// GPIO peripheral has the ETM extension
#define SOC_GPIO_SUPPORT_ETM 1
#define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
#define SOC_GPIO_ETM_TASKS_PER_GROUP 8
// Target has the full LP IO subsystem
components/soc/esp32p4/include/soc/clk_tree_defs.h
+7
View File
@@ -232,6 +232,13 @@ typedef enum {
#endif // SOC_CLK_TREE_SUPPORTED
} soc_periph_gptimer_clk_src_t;
//////////////////////////////////////////////////ETM///////////////////////////////////////////////////////////////////
/**
* @brief Type of ETM clock source
*/
typedef int soc_periph_etm_clk_src_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+16
View File
@@ -35,6 +35,10 @@ config SOC_MCPWM_SUPPORTED
bool
default y
config SOC_ETM_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
@@ -259,6 +263,10 @@ config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
bool
default y
config SOC_GPIO_SUPPORT_ETM
bool
default y
config SOC_LP_IO_HAS_INDEPENDENT_WAKEUP_SOURCE
bool
default y
@@ -311,6 +319,10 @@ config SOC_SDM_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_ETM_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_LEDC_CHANNEL_NUM
int
default 6
@@ -367,6 +379,10 @@ config SOC_MEMSPI_ENCRYPTION_ALIGNMENT
int
default 16
config SOC_SYSTIMER_SUPPORT_ETM
bool
default y
config SOC_TIMER_SUPPORT_ETM
bool
default y
components/soc/esp32s31/include/soc/clk_tree_defs.h
+21 -19
View File
@@ -186,11 +186,7 @@ typedef enum {
* }
* @endcode
*/
#if SOC_CLK_TREE_SUPPORTED
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
#else
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_XTAL}
#endif
/**
* @brief Type of GPTimer clock source
@@ -199,25 +195,17 @@ typedef enum {
GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
#if SOC_CLK_TREE_SUPPORTED
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
#else
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice */
#endif // SOC_CLK_TREE_SUPPORTED
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
//////////////////////////////////////////////////ETM///////////////////////////////////////////////////////////////////
typedef enum {
TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
#if SOC_CLK_TREE_SUPPORTED
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */
#else
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Timer group clock source default choice is XTAL */
#endif // SOC_CLK_TREE_SUPPORTED
} soc_periph_tg_clk_src_legacy_t;
ETM_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
ETM_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
ETM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
ETM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} soc_periph_etm_clk_src_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
@@ -306,6 +294,8 @@ typedef enum {
MWDT_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL 40 MHz as the default clock choice */
} soc_periph_mwdt_clk_src_t;
//////////////////////////////////////////////////SDM/////////////////////////////////////////////////////////////////
/**
* @brief Sigma Delta Modulator clock source
*/
@@ -315,6 +305,18 @@ typedef enum {
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
/**
* @brief Glitch filter clock source
*/
typedef enum {
GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
GLITCH_FILTER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the source clock */
GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_glitch_filter_clk_src_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
/**
components/soc/esp32s31/include/soc/soc_caps.h
+6 -5
View File
@@ -41,7 +41,7 @@
// #define SOC_LCDCAM_RGB_LCD_SUPPORTED 1 // TODO: [ESP32S31] IDF-14722
#define SOC_MCPWM_SUPPORTED 1
// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32S31] IDF-14719
// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14724
#define SOC_ETM_SUPPORTED 1
// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32S31] IDF-14711
#define SOC_ASYNC_MEMCPY_SUPPORTED 1
// #define SOC_USB_OTG_SUPPORTED 1 // TODO: [ESP32S31] IDF-14701
@@ -166,9 +166,7 @@
#define SOC_GPIO_SUPPORT_PIN_HYS_FILTER 1
// GPIO peripheral has the ETM extension
// #define SOC_GPIO_SUPPORT_ETM 1 // TODO: [ESP32S31] IDF-14786
// #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8 // TODO: [ESP32S31] IDF-14786
// #define SOC_GPIO_ETM_TASKS_PER_GROUP 8 // TODO: [ESP32S31] IDF-14786
#define SOC_GPIO_SUPPORT_ETM 1
// GPIO0~7 on ESP32S31 can support chip deep sleep wakeup
// #define SOC_GPIO_SUPPORT_HP_PERIPH_PD_SLEEP_WAKEUP (1) // TODO: [ESP32S31] IDF-14643
@@ -206,6 +204,9 @@
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- ETM CAPS -----------------------------------*/
#define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
/*-------------------------- LEDC CAPS ---------------------------------------*/
// TODO: [ESP32S31] IDF-14709
#define SOC_LEDC_CHANNEL_NUM (6)
@@ -237,7 +238,7 @@
#define SOC_MEMSPI_ENCRYPTION_ALIGNMENT 16 /*!< 16-byte alignment restriction to mem addr and size if encryption is enabled */
/*-------------------------- SYSTIMER CAPS ----------------------------------*/
// TODO: [ESP32S31] IDF-14693
#define SOC_SYSTIMER_SUPPORT_ETM 1 // Systimer comparator can generate ETM event
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_ETM (1)
components/soc/esp32s31/ld/esp32s31.peripherals.ld
+2
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@@ -73,6 +73,8 @@ PROVIDE ( IO_MUX = 0x20582000 );
PROVIDE ( GPIO = 0x20583000 );
PROVIDE ( GPIO_EXT = 0x20583E00 );
PROVIDE ( SDM = 0x20583E04 );
PROVIDE ( GLITCH_FILTER = 0x20583E08 );
PROVIDE ( GPIO_ETM = 0x20583F18 );
PROVIDE ( MSPI_IOMUX = 0x20584000 );
PROVIDE ( HP_SYSTEM = 0x20586000 );
PROVIDE ( HP_SYS_CLKRST = 0x20587000 );
components/soc/esp32s31/register/soc/gpio_ext_struct.h
+55 -1050
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File diff suppressed because it is too large Load Diff
components/soc/esp32s31/register/soc/soc_etm_struct.h
+6 -101
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@@ -10547,113 +10547,17 @@ typedef union {
} soc_etm_date_reg_t;
typedef struct {
typedef struct soc_etm_dev_t {
volatile soc_etm_ch_ena_ad0_reg_t ch_ena_ad0;
volatile soc_etm_ch_ena_ad0_set_reg_t ch_ena_ad0_set;
volatile soc_etm_ch_ena_ad0_clr_reg_t ch_ena_ad0_clr;
volatile soc_etm_ch_ena_ad1_reg_t ch_ena_ad1;
volatile soc_etm_ch_ena_ad1_set_reg_t ch_ena_ad1_set;
volatile soc_etm_ch_ena_ad1_clr_reg_t ch_ena_ad1_clr;
volatile soc_etm_chn_evt_id_reg_t ch0_evt_id;
volatile soc_etm_chn_task_id_reg_t ch0_task_id;
volatile soc_etm_chn_evt_id_reg_t ch1_evt_id;
volatile soc_etm_chn_task_id_reg_t ch1_task_id;
volatile soc_etm_chn_evt_id_reg_t ch2_evt_id;
volatile soc_etm_chn_task_id_reg_t ch2_task_id;
volatile soc_etm_chn_evt_id_reg_t ch3_evt_id;
volatile soc_etm_chn_task_id_reg_t ch3_task_id;
volatile soc_etm_chn_evt_id_reg_t ch4_evt_id;
volatile soc_etm_chn_task_id_reg_t ch4_task_id;
volatile soc_etm_chn_evt_id_reg_t ch5_evt_id;
volatile soc_etm_chn_task_id_reg_t ch5_task_id;
volatile soc_etm_chn_evt_id_reg_t ch6_evt_id;
volatile soc_etm_chn_task_id_reg_t ch6_task_id;
volatile soc_etm_chn_evt_id_reg_t ch7_evt_id;
volatile soc_etm_chn_task_id_reg_t ch7_task_id;
volatile soc_etm_chn_evt_id_reg_t ch8_evt_id;
volatile soc_etm_chn_task_id_reg_t ch8_task_id;
volatile soc_etm_chn_evt_id_reg_t ch9_evt_id;
volatile soc_etm_chn_task_id_reg_t ch9_task_id;
volatile soc_etm_chn_evt_id_reg_t ch10_evt_id;
volatile soc_etm_chn_task_id_reg_t ch10_task_id;
volatile soc_etm_chn_evt_id_reg_t ch11_evt_id;
volatile soc_etm_chn_task_id_reg_t ch11_task_id;
volatile soc_etm_chn_evt_id_reg_t ch12_evt_id;
volatile soc_etm_chn_task_id_reg_t ch12_task_id;
volatile soc_etm_chn_evt_id_reg_t ch13_evt_id;
volatile soc_etm_chn_task_id_reg_t ch13_task_id;
volatile soc_etm_chn_evt_id_reg_t ch14_evt_id;
volatile soc_etm_chn_task_id_reg_t ch14_task_id;
volatile soc_etm_chn_evt_id_reg_t ch15_evt_id;
volatile soc_etm_chn_task_id_reg_t ch15_task_id;
volatile soc_etm_chn_evt_id_reg_t ch16_evt_id;
volatile soc_etm_chn_task_id_reg_t ch16_task_id;
volatile soc_etm_chn_evt_id_reg_t ch17_evt_id;
volatile soc_etm_chn_task_id_reg_t ch17_task_id;
volatile soc_etm_chn_evt_id_reg_t ch18_evt_id;
volatile soc_etm_chn_task_id_reg_t ch18_task_id;
volatile soc_etm_chn_evt_id_reg_t ch19_evt_id;
volatile soc_etm_chn_task_id_reg_t ch19_task_id;
volatile soc_etm_chn_evt_id_reg_t ch20_evt_id;
volatile soc_etm_chn_task_id_reg_t ch20_task_id;
volatile soc_etm_chn_evt_id_reg_t ch21_evt_id;
volatile soc_etm_chn_task_id_reg_t ch21_task_id;
volatile soc_etm_chn_evt_id_reg_t ch22_evt_id;
volatile soc_etm_chn_task_id_reg_t ch22_task_id;
volatile soc_etm_chn_evt_id_reg_t ch23_evt_id;
volatile soc_etm_chn_task_id_reg_t ch23_task_id;
volatile soc_etm_chn_evt_id_reg_t ch24_evt_id;
volatile soc_etm_chn_task_id_reg_t ch24_task_id;
volatile soc_etm_chn_evt_id_reg_t ch25_evt_id;
volatile soc_etm_chn_task_id_reg_t ch25_task_id;
volatile soc_etm_chn_evt_id_reg_t ch26_evt_id;
volatile soc_etm_chn_task_id_reg_t ch26_task_id;
volatile soc_etm_chn_evt_id_reg_t ch27_evt_id;
volatile soc_etm_chn_task_id_reg_t ch27_task_id;
volatile soc_etm_chn_evt_id_reg_t ch28_evt_id;
volatile soc_etm_chn_task_id_reg_t ch28_task_id;
volatile soc_etm_chn_evt_id_reg_t ch29_evt_id;
volatile soc_etm_chn_task_id_reg_t ch29_task_id;
volatile soc_etm_chn_evt_id_reg_t ch30_evt_id;
volatile soc_etm_chn_task_id_reg_t ch30_task_id;
volatile soc_etm_chn_evt_id_reg_t ch31_evt_id;
volatile soc_etm_chn_task_id_reg_t ch31_task_id;
volatile soc_etm_chn_evt_id_reg_t ch32_evt_id;
volatile soc_etm_chn_task_id_reg_t ch32_task_id;
volatile soc_etm_chn_evt_id_reg_t ch33_evt_id;
volatile soc_etm_chn_task_id_reg_t ch33_task_id;
volatile soc_etm_chn_evt_id_reg_t ch34_evt_id;
volatile soc_etm_chn_task_id_reg_t ch34_task_id;
volatile soc_etm_chn_evt_id_reg_t ch35_evt_id;
volatile soc_etm_chn_task_id_reg_t ch35_task_id;
volatile soc_etm_chn_evt_id_reg_t ch36_evt_id;
volatile soc_etm_chn_task_id_reg_t ch36_task_id;
volatile soc_etm_chn_evt_id_reg_t ch37_evt_id;
volatile soc_etm_chn_task_id_reg_t ch37_task_id;
volatile soc_etm_chn_evt_id_reg_t ch38_evt_id;
volatile soc_etm_chn_task_id_reg_t ch38_task_id;
volatile soc_etm_chn_evt_id_reg_t ch39_evt_id;
volatile soc_etm_chn_task_id_reg_t ch39_task_id;
volatile soc_etm_chn_evt_id_reg_t ch40_evt_id;
volatile soc_etm_chn_task_id_reg_t ch40_task_id;
volatile soc_etm_chn_evt_id_reg_t ch41_evt_id;
volatile soc_etm_chn_task_id_reg_t ch41_task_id;
volatile soc_etm_chn_evt_id_reg_t ch42_evt_id;
volatile soc_etm_chn_task_id_reg_t ch42_task_id;
volatile soc_etm_chn_evt_id_reg_t ch43_evt_id;
volatile soc_etm_chn_task_id_reg_t ch43_task_id;
volatile soc_etm_chn_evt_id_reg_t ch44_evt_id;
volatile soc_etm_chn_task_id_reg_t ch44_task_id;
volatile soc_etm_chn_evt_id_reg_t ch45_evt_id;
volatile soc_etm_chn_task_id_reg_t ch45_task_id;
volatile soc_etm_chn_evt_id_reg_t ch46_evt_id;
volatile soc_etm_chn_task_id_reg_t ch46_task_id;
volatile soc_etm_chn_evt_id_reg_t ch47_evt_id;
volatile soc_etm_chn_task_id_reg_t ch47_task_id;
volatile soc_etm_chn_evt_id_reg_t ch48_evt_id;
volatile soc_etm_chn_task_id_reg_t ch48_task_id;
volatile soc_etm_chn_evt_id_reg_t ch49_evt_id;
volatile soc_etm_chn_task_id_reg_t ch49_task_id;
volatile struct {
soc_etm_chn_evt_id_reg_t eid;
soc_etm_chn_task_id_reg_t tid;
} channel[50];
volatile soc_etm_evt_st0_reg_t evt_st0;
volatile soc_etm_evt_st0_clr_reg_t evt_st0_clr;
volatile soc_etm_evt_st1_reg_t evt_st1;
@@ -10708,6 +10612,7 @@ typedef struct {
volatile soc_etm_date_reg_t date;
} soc_etm_dev_t;
extern soc_etm_dev_t SOC_ETM;
#ifndef __cplusplus
_Static_assert(sizeof(soc_etm_dev_t) == 0x278, "Invalid size of soc_etm_dev_t structure");
examples/peripherals/timer_group/gptimer_capture_hc_sr04/README.md
+2 -2
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@@ -1,5 +1,5 @@
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 |
| ----------------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- |
| Supported Targets | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S31 |
| ----------------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | --------- |
# HC-SR04 Example based on GPTimer Capture and ETM
examples/peripherals/timer_group/gptimer_capture_hc_sr04/pytest_gptimer_capture_example.py
+1 -1
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@@ -6,7 +6,7 @@ from pytest_embedded_idf.utils import idf_parametrize
@pytest.mark.generic
@idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32c61', 'esp32h2', 'esp32p4'], indirect=['target'])
@idf_parametrize('target', ['esp32c5', 'esp32c6', 'esp32c61', 'esp32h2', 'esp32p4', 'esp32s31'], indirect=['target'])
def test_gptimer_capture(dut: Dut) -> None:
dut.expect_exact('Configure trig gpio')
dut.expect_exact('Configure echo gpio')