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ci(intr_dump): added mspi intr

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armando
2025-12-19 14:39:51 +08:00
committed by Armando (Dou Yiwen)
parent 513f424769
commit 4777ce6e8c
2 changed files with 12 additions and 12 deletions
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tools/test_apps/system/esp_intr_dump/expected_output/esp32c5.txt
+6 -6
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@@ -2,12 +2,12 @@ CPU 0 interrupt status:
Int Level Type Status
0 1 Level Shared: LP_RTC_TIMER
1 * * Reserved
2 1 Level Used: FROM_CPU_INTR0
3 1 Level Used: SYSTIMER_TARGET0
4 1 Level Used: TG0_WDT_LEVEL
5 1 Level Used: UART0
2 1 Level Used: MSPI
3 1 Level Used: FROM_CPU_INTR0
4 1 Level Used: SYSTIMER_TARGET0
5 1 Level Used: TG0_WDT_LEVEL
6 * * Reserved
7 * * Free
7 1 Level Used: UART0
8 * * Free
9 * * Free
10 * * Free
@@ -32,5 +32,5 @@ CPU 0 interrupt status:
29 * * Free
30 * * Free
31 * * Free
Interrupts available for general use: 22
Interrupts available for general use: 21
Shared interrupts: 1
tools/test_apps/system/esp_intr_dump/expected_output/esp32c61.txt
+6 -6
View File
@@ -2,12 +2,12 @@ CPU 0 interrupt status:
Int Level Type Status
0 1 Level Shared: LP_RTC_TIMER
1 * * Reserved
2 1 Level Used: CPU_FROM_CPU_0
3 1 Level Used: SYSTIMER_TARGET0
4 1 Level Used: TG0_WDT
5 1 Level Used: UART0
2 1 Level Used: MSPI
3 1 Level Used: CPU_FROM_CPU_0
4 1 Level Used: SYSTIMER_TARGET0
5 1 Level Used: TG0_WDT
6 * * Reserved
7 * * Free
7 1 Level Used: UART0
8 * * Free
9 * * Free
10 * * Free
@@ -32,5 +32,5 @@ CPU 0 interrupt status:
29 * * Free
30 * * Free
31 * * Free
Interrupts available for general use: 22
Interrupts available for general use: 21
Shared interrupts: 1