fix(intr_alloc): Fix ISR allocate methods in several drivers

components/esp_driver_ledc/src/ledc.c

@@ -1581,7 +1581,15 @@ esp_err_t ledc_fade_func_install(int intr_alloc_flags)
 {
     LEDC_CHECK(s_ledc_fade_isr_handle == NULL, "fade function already installed", ESP_ERR_INVALID_STATE);
     //OR intr_alloc_flags with ESP_INTR_FLAG_IRAM because the fade isr is in IRAM
-    return esp_intr_alloc(ETS_LEDC_INTR_SOURCE, intr_alloc_flags | ESP_INTR_FLAG_IRAM, ledc_fade_isr, NULL, &s_ledc_fade_isr_handle);
+    return esp_intr_alloc_intrstatus(
+               ETS_LEDC_INTR_SOURCE,
+               intr_alloc_flags | ESP_INTR_FLAG_IRAM,
+               (uint32_t)ledc_hal_get_fade_end_intr_addr(&(p_ledc_obj[0]->ledc_hal)),
+               LEDC_LL_FADE_END_INTR_MASK,
+               ledc_fade_isr,
+               NULL,
+               &s_ledc_fade_isr_handle
+           );
 }
 
 void ledc_fade_func_uninstall(void)

components/esp_driver_sdio/src/sdio_slave.c

@@ -356,15 +356,20 @@ esp_err_t sdio_slave_initialize(sdio_slave_config_t *config)
     esp_err_t r;
     intr_handle_t intr_handle = NULL;
     const int flags = 0;
-    r = esp_intr_alloc(ETS_SLC0_INTR_SOURCE, flags, sdio_intr, NULL, &intr_handle);
-    if (r != ESP_OK) {
-        return r;
-    }
 
     r = init_context(config);
-    if (r != ESP_OK) {
-        return r;
-    }
+    SDIO_SLAVE_CHECK(r == ESP_OK, "context initialization failed", r);
+
+    r = esp_intr_alloc_intrstatus(
+            ETS_SLC0_INTR_SOURCE,
+            flags,
+            (uint32_t)sdio_slave_hal_get_intr_status_reg(context.hal),
+            sdio_slave_ll_intr_status_mask,
+            sdio_intr,
+            NULL,
+            &intr_handle
+        );
+    SDIO_SLAVE_CHECK(r == ESP_OK, "interrupt allocation failed", r);
     context.intr_handle = intr_handle;
 
 #if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP

components/esp_driver_sdmmc/legacy/include/driver/sdmmc_host.h

@@ -15,7 +15,7 @@
 #include "esp_err.h"
 #include "driver/sdmmc_types.h"
 #include "driver/sdmmc_default_configs.h"
-#include "driver/gpio.h"
+#include "soc/gpio_num.h"
 
 #ifdef __cplusplus
 extern "C" {

components/esp_driver_spi/src/gpspi/spi_common.c

@@ -811,7 +811,7 @@ esp_err_t spi_bus_initialize(spi_host_device_t host_id, const spi_bus_config_t *
 #elif SOC_GDMA_SUPPORTED
     SPI_CHECK(dma_chan == SPI_DMA_DISABLED || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG);
 #endif
-    SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH | ESP_INTR_FLAG_EDGE | ESP_INTR_FLAG_INTRDISABLED)) == 0, "intr flag not allowed", ESP_ERR_INVALID_ARG);
+    SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH | ESP_INTR_FLAG_EDGE | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_INTRDISABLED)) == 0, "intr flag not allowed", ESP_ERR_INVALID_ARG);
 #ifndef CONFIG_SPI_MASTER_ISR_IN_IRAM
     SPI_CHECK((bus_config->intr_flags & ESP_INTR_FLAG_IRAM) == 0, "ESP_INTR_FLAG_IRAM should be disabled when CONFIG_SPI_MASTER_ISR_IN_IRAM is not set.", ESP_ERR_INVALID_ARG);
 #endif

components/esp_driver_spi/src/gpspi/spi_slave.c

@@ -162,7 +162,7 @@ esp_err_t spi_slave_initialize(spi_host_device_t host, const spi_bus_config_t *b
 #elif SOC_GDMA_SUPPORTED
     SPI_CHECK(dma_chan == SPI_DMA_DISABLED || dma_chan == SPI_DMA_CH_AUTO, "invalid dma channel, chip only support spi dma channel auto-alloc", ESP_ERR_INVALID_ARG);
 #endif
-    SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH | ESP_INTR_FLAG_EDGE | ESP_INTR_FLAG_INTRDISABLED)) == 0, "intr flag not allowed", ESP_ERR_INVALID_ARG);
+    SPI_CHECK((bus_config->intr_flags & (ESP_INTR_FLAG_HIGH | ESP_INTR_FLAG_EDGE | ESP_INTR_FLAG_SHARED | ESP_INTR_FLAG_INTRDISABLED)) == 0, "intr flag not allowed", ESP_ERR_INVALID_ARG);
 #ifndef CONFIG_SPI_SLAVE_ISR_IN_IRAM
     SPI_CHECK((bus_config->intr_flags & ESP_INTR_FLAG_IRAM) == 0, "ESP_INTR_FLAG_IRAM should be disabled when CONFIG_SPI_SLAVE_ISR_IN_IRAM is not set.", ESP_ERR_INVALID_ARG);
 #endif

components/esp_driver_uart/src/uart.c

@@ -2042,9 +2042,15 @@ esp_err_t uart_driver_install(uart_port_t uart_num, int rx_buffer_size, int tx_b
     uart_hal_disable_intr_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
     uart_hal_clr_intsts_mask(&(uart_context[uart_num].hal), UART_LL_INTR_MASK);
 
-    ret = esp_intr_alloc(uart_periph_signal[uart_num].irq, intr_alloc_flags,
-                         uart_rx_intr_handler_default, p_uart_obj[uart_num],
-                         &p_uart_obj[uart_num]->intr_handle);
+    ret = esp_intr_alloc_intrstatus(
+              uart_periph_signal[uart_num].irq,
+              intr_alloc_flags,
+              (uint32_t)uart_hal_get_intr_status_reg(&(uart_context[uart_num].hal)),
+              UART_LL_INTR_MASK,
+              uart_rx_intr_handler_default,
+              p_uart_obj[uart_num],
+              &p_uart_obj[uart_num]->intr_handle
+          );
     ESP_GOTO_ON_ERROR(ret, err, UART_TAG, "Could not allocate an interrupt for UART");
 
     uart_intr_config_t uart_intr = {

components/hal/esp32/include/hal/ledc_ll.h

@@ -26,6 +26,8 @@ extern "C" {
 #define LEDC_LL_HPOINT_VAL_MAX     (LEDC_HPOINT_LSCH0_V)
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
+/// Get the mask of the fade end interrupt status register.
+#define LEDC_LL_FADE_END_INTR_MASK  (0xffffUL << LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S)
 
 #define LEDC_LL_GLOBAL_CLOCKS { \
                                 LEDC_SLOW_CLK_APB, \
@@ -556,7 +558,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
  *
  * @param hw Beginning address of the peripheral registers
  * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode
- * @param channel_num LEDC channel index (0-7), select from ledc_channel_t
  * @param intr_status The fade end interrupt status
  *
  * @return None
@@ -568,6 +569,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
     *intr_status = (value >> int_en_base) & 0xff;
 }
 
+/**
+ * @brief Get the address of the fade end interrupt status register.
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @return Pointer to the fade end interrupt status register.
+ */
+static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
+
 /**
  * @brief Clear fade end interrupt status
  *

components/hal/esp32/include/hal/sdio_slave_ll.h

@@ -37,6 +37,8 @@ extern "C" {
 #define sdio_slave_ll_get_host(ID)  (&HOST)
 /// Get address of the only HINF registers for ESP32
 #define sdio_slave_ll_get_hinf(ID)  (&HINF)
+/// Get the mask of the interrupt status.
+#define sdio_slave_ll_intr_status_mask  (0xff | SLC_SLC0_RX_DONE_INT_ST | SLC_SLC0_RX_EOF_INT_ST | SLC_SLC0_TX_DONE_INT_ST)
 
 /*
  *  SLC2 DMA Desc struct, aka sdio_slave_ll_desc_t
@@ -550,6 +552,17 @@ static inline void sdio_slave_ll_slvint_fetch_clear(slc_dev_t *slc, sdio_slave_l
     slc->slc0_int_clr.val = slv_int;
 }
 
+/**
+ * Get the address of the interrupt status register.
+ *
+ * @param slc Address of the SLC registers
+ * @return Address of the interrupt status register
+ */
+static inline volatile void* sdio_slave_ll_get_intr_status_reg(slc_dev_t *slc)
+{
+    return &slc->slc0_int_st.val;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32/include/hal/uart_ll.h

@@ -37,7 +37,6 @@ extern "C" {
 
 #define UART_LL_INTR_MASK         (0x7ffff) //All interrupt mask
 
-
 // Define UART interrupts
 typedef enum {
     UART_INTR_RXFIFO_FULL      = (0x1<<0),
@@ -300,6 +299,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
     return hw->int_st.val;
 }
 
+FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
 /**
  * @brief  Clear the UART interrupt status based on the given mask.
  *

components/hal/esp32c2/include/hal/ledc_ll.h

@@ -29,6 +29,8 @@ extern "C" {
 #define LEDC_LL_OVF_CNT_MAX        (LEDC_OVF_NUM_CH0_V + 1)
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
+/// Get the mask of the fade end interrupt status register.
+#define LEDC_LL_FADE_END_INTR_MASK  (0x3fUL << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
 
 #define LEDC_LL_GLOBAL_CLOCKS { \
                                 LEDC_SLOW_CLK_PLL_DIV, \
@@ -533,7 +535,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
  *
  * @param hw Beginning address of the peripheral registers
  * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode
- * @param channel_num LEDC channel index (0-7), select from ledc_channel_t
  * @param intr_status The fade end interrupt status
  *
  * @return None
@@ -545,6 +546,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
     *intr_status = (value >> int_en_base) & 0xff;
 }
 
+/**
+ * @brief Get the address of the fade end interrupt status register.
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @return Pointer to the fade end interrupt status register.
+ */
+static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
+
 /**
  * @brief Clear fade end interrupt status
  *

components/hal/esp32c2/include/hal/uart_ll.h

@@ -310,6 +310,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
     return hw->int_st.val;
 }
 
+FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
 /**
  * @brief  Clear the UART interrupt status based on the given mask.
  *

components/hal/esp32c3/include/hal/ledc_ll.h

@@ -30,6 +30,8 @@ extern "C" {
 #define LEDC_LL_OVF_CNT_MAX        (LEDC_OVF_NUM_LSCH0_V + 1)
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
+/// Get the mask of the fade end interrupt status register.
+#define LEDC_LL_FADE_END_INTR_MASK  (0x3fUL << LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S)
 
 #define LEDC_LL_GLOBAL_CLOCKS { \
                                 LEDC_SLOW_CLK_APB, \
@@ -535,7 +537,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
  *
  * @param hw Beginning address of the peripheral registers
  * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode
- * @param channel_num LEDC channel index (0-7), select from ledc_channel_t
  * @param intr_status The fade end interrupt status
  *
  * @return None
@@ -547,6 +548,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
     *intr_status = (value >> int_en_base) & 0xff;
 }
 
+/**
+ * @brief Get the address of the fade end interrupt status register.
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @return Pointer to the fade end interrupt status register.
+ */
+static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
+
 /**
  * @brief Clear fade end interrupt status
  *

components/hal/esp32c3/include/hal/uart_ll.h

@@ -315,6 +315,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
     return hw->int_st.val;
 }
 
+FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
 /**
  * @brief  Clear the UART interrupt status based on the given mask.
  *

components/hal/esp32c5/include/hal/ledc_ll.h

@@ -34,6 +34,8 @@ extern "C" {
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
 #define LEDC_LL_GLOBAL_CLOCKS      SOC_LEDC_CLKS
+/// Get the mask of the fade end interrupt status register.
+#define LEDC_LL_FADE_END_INTR_MASK  (0x3fUL << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
 
 // Channel tasks: ID, enable register and bit
 #define LEDC_LL_ETM_CHANNEL_TASK_ID(group, channel, task) \
@@ -622,7 +624,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
  *
  * @param hw Beginning address of the peripheral registers
  * @param speed_mode LEDC speed_mode, low-speed mode only
- * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
  * @param intr_status The fade end interrupt status
  *
  * @return None
@@ -634,6 +635,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
     *intr_status = (value >> int_en_base) & 0xff;
 }
 
+/**
+ * @brief Get the address of the fade end interrupt status register.
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @return Pointer to the fade end interrupt status register.
+ */
+static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
+
 /**
  * @brief Clear fade end interrupt status
  *

components/hal/esp32c5/include/hal/sdio_slave_ll.h

@@ -37,6 +37,8 @@ extern "C" {
 #define sdio_slave_ll_get_host(ID)  (&HOST)
 /// Get address of the only HINF registers
 #define sdio_slave_ll_get_hinf(ID)  (&HINF)
+/// Get the mask of the interrupt status.
+#define sdio_slave_ll_intr_status_mask  (0xff | SDIO_SLC0_RX_DONE_INT_ST | SDIO_SLC0_RX_EOF_INT_ST | SDIO_SLC0_TX_DONE_INT_ST)
 
 /*
  *  SLC2 DMA Desc struct, aka sdio_slave_ll_desc_t
@@ -533,6 +535,17 @@ static inline void sdio_slave_ll_slvint_fetch_clear(slc_dev_t *slc, sdio_slave_l
     slc->slc_slc0int_clr.val = slv_int;
 }
 
+/**
+ * Get the address of the interrupt status register.
+ *
+ * @param slc Address of the SLC registers
+ * @return Address of the interrupt status register
+ */
+static inline volatile void* sdio_slave_ll_get_intr_status_reg(slc_dev_t *slc)
+{
+    return &slc->slc_slc0int_st.val;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c5/include/hal/uart_ll.h

@@ -537,6 +537,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
     return hw->int_st.val;
 }
 
+FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
 /**
  * @brief  Clear the UART interrupt status based on the given mask.
  *

components/hal/esp32c6/include/hal/ledc_ll.h

@@ -35,6 +35,8 @@ extern "C" {
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
 #define LEDC_LL_GLOBAL_CLOCKS      SOC_LEDC_CLKS
+/// Get the mask of the fade end interrupt status register.
+#define LEDC_LL_FADE_END_INTR_MASK  (0x3fUL << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
 
 #define LEDC_LL_GLOBAL_CLK_NC_BY_DEFAULT    1
 #define LEDC_LL_GLOBAL_CLK_DEFAULT          LEDC_SLOW_CLK_RC_FAST   // The temporal global clock source to set to at least make the LEDC core clock on
@@ -744,7 +746,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
  *
  * @param hw Beginning address of the peripheral registers
  * @param speed_mode LEDC speed_mode, low-speed mode only
- * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
  * @param intr_status The fade end interrupt status
  *
  * @return None
@@ -756,6 +757,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
     *intr_status = (value >> int_en_base) & 0xff;
 }
 
+/**
+ * @brief Get the address of the fade end interrupt status register.
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @return Pointer to the fade end interrupt status register.
+ */
+static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
+
 /**
  * @brief Clear fade end interrupt status
  *

components/hal/esp32c6/include/hal/sdio_slave_ll.h

@@ -37,6 +37,8 @@ extern "C" {
 #define sdio_slave_ll_get_host(ID)  (&HOST)
 /// Get address of the only HINF registers
 #define sdio_slave_ll_get_hinf(ID)  (&HINF)
+/// Get the mask of the interrupt status.
+#define sdio_slave_ll_intr_status_mask  (0xff | SDIO_SLC0_RX_DONE_INT_ST | SDIO_SLC0_RX_EOF_INT_ST | SDIO_SLC0_TX_DONE_INT_ST)
 
 /*
  *  SLC2 DMA Desc struct, aka sdio_slave_ll_desc_t
@@ -533,6 +535,17 @@ static inline void sdio_slave_ll_slvint_fetch_clear(slc_dev_t *slc, sdio_slave_l
     slc->slc0int_clr.val = slv_int;
 }
 
+/**
+ * Get the address of the interrupt status register.
+ *
+ * @param slc Address of the SLC registers
+ * @return Address of the interrupt status register
+ */
+static inline volatile void* sdio_slave_ll_get_intr_status_reg(slc_dev_t *slc)
+{
+    return &slc->slc0int_st.val;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c6/include/hal/spi_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/hal/esp32c6/include/hal/uart_ll.h

@@ -518,6 +518,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
     return hw->int_st.val;
 }
 
+FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
 /**
  * @brief  Clear the UART interrupt status based on the given mask.
  *

components/hal/esp32c61/include/hal/ledc_ll.h

@@ -34,6 +34,8 @@ extern "C" {
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
 #define LEDC_LL_GLOBAL_CLOCKS      SOC_LEDC_CLKS
+/// Get the mask of the fade end interrupt status register.
+#define LEDC_LL_FADE_END_INTR_MASK  (0x3fUL << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
 
 // Channel tasks: ID, enable register and bit
 #define LEDC_LL_ETM_CHANNEL_TASK_ID(group, channel, task) \
@@ -622,7 +624,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
  *
  * @param hw Beginning address of the peripheral registers
  * @param speed_mode LEDC speed_mode, low-speed mode only
- * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
  * @param intr_status The fade end interrupt status
  *
  * @return None
@@ -634,6 +635,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
     *intr_status = (value >> int_en_base) & 0xff;
 }
 
+/**
+ * @brief Get the address of the fade end interrupt status register.
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @return Pointer to the fade end interrupt status register.
+ */
+static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
+
 /**
  * @brief Clear fade end interrupt status
  *

components/hal/esp32c61/include/hal/sdio_slave_ll.h

@@ -37,6 +37,9 @@ extern "C" {
 #define sdio_slave_ll_get_host(ID)  (&HOST)
 /// Get address of the only HINF registers
 #define sdio_slave_ll_get_hinf(ID)  (&HINF)
+/// Get the mask of the interrupt status.
+#define sdio_slave_ll_intr_status_mask  (0xff | SDIO_SLC0_RX_DONE_INT_ST | SDIO_SLC0_RX_EOF_INT_ST | SDIO_SLC0_TX_DONE_INT_ST)
+
 
 /*
  *  SLC2 DMA Desc struct, aka sdio_slave_ll_desc_t
@@ -533,6 +536,17 @@ static inline void sdio_slave_ll_slvint_fetch_clear(slc_dev_t *slc, sdio_slave_l
     slc->slc_slc0int_clr.val = slv_int;
 }
 
+/**
+ * Get the address of the interrupt status register.
+ *
+ * @param slc Address of the SLC registers
+ * @return Address of the interrupt status register
+ */
+static inline volatile void* sdio_slave_ll_get_intr_status_reg(slc_dev_t *slc)
+{
+    return &slc->slc_slc0int_st.val;
+}
+
 #ifdef __cplusplus
 }
 #endif

components/hal/esp32c61/include/hal/uart_ll.h

@@ -356,6 +356,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
     return hw->int_st.val;
 }
 
+FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
 /**
  * @brief  Clear the UART interrupt status based on the given mask.
  *

components/hal/esp32h2/include/hal/ledc_ll.h

@@ -35,6 +35,8 @@ extern "C" {
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
 #define LEDC_LL_GLOBAL_CLOCKS      SOC_LEDC_CLKS
+/// Get the mask of the fade end interrupt status register.
+#define LEDC_LL_FADE_END_INTR_MASK  (0x3fUL << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
 
 // Channel tasks: ID, enable register and bit
 #define LEDC_LL_ETM_CHANNEL_TASK_ID(group, channel, task) \
@@ -741,7 +743,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
  *
  * @param hw Beginning address of the peripheral registers
  * @param speed_mode LEDC speed_mode, low-speed mode only
- * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
  * @param intr_status The fade end interrupt status
  *
  * @return None
@@ -753,6 +754,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
     *intr_status = (value >> int_en_base) & 0xff;
 }
 
+/**
+ * @brief Get the address of the fade end interrupt status register.
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @return Pointer to the fade end interrupt status register.
+ */
+static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
+
 /**
  * @brief Clear fade end interrupt status
  *

components/hal/esp32h2/include/hal/spi_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/hal/esp32h2/include/hal/uart_ll.h

@@ -335,6 +335,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
     return hw->int_st.val;
 }
 
+FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
 /**
  * @brief  Clear the UART interrupt status based on the given mask.
  *

components/hal/esp32h21/include/hal/ledc_ll.h

@@ -35,6 +35,8 @@ extern "C" {
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
 #define LEDC_LL_GLOBAL_CLOCKS      SOC_LEDC_CLKS
+/// Get the mask of the fade end interrupt status register.
+#define LEDC_LL_FADE_END_INTR_MASK  (0x3fUL << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
 
 // Channel tasks: ID, enable register and bit
 #define LEDC_LL_ETM_CHANNEL_TASK_ID(group, channel, task) \
@@ -740,7 +742,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
  *
  * @param hw Beginning address of the peripheral registers
  * @param speed_mode LEDC speed_mode, low-speed mode only
- * @param channel_num LEDC channel index (0-5), select from ledc_channel_t
  * @param intr_status The fade end interrupt status
  *
  * @return None
@@ -752,6 +753,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
     *intr_status = (value >> int_en_base) & 0xff;
 }
 
+/**
+ * @brief Get the address of the fade end interrupt status register.
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @return Pointer to the fade end interrupt status register.
+ */
+static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
+
 /**
  * @brief Clear fade end interrupt status
  *

components/hal/esp32h21/include/hal/uart_ll.h

@@ -336,6 +336,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
     return hw->int_st.val;
 }
 
+FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
 /**
  * @brief  Clear the UART interrupt status based on the given mask.
  *

components/hal/esp32h4/include/hal/ledc_ll.h

@@ -34,6 +34,8 @@ extern "C" {
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
 #define LEDC_LL_GLOBAL_CLOCKS      SOC_LEDC_CLKS
+/// Get the mask of the fade end interrupt status register.
+#define LEDC_LL_FADE_END_INTR_MASK  (0xffUL << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
 
 // Channel tasks: ID, enable register and bit
 #define LEDC_LL_ETM_CHANNEL_TASK_ID(group, channel, task) \
@@ -569,7 +571,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
  *
  * @param hw Beginning address of the peripheral registers
  * @param speed_mode LEDC speed_mode, low-speed mode only
- * @param channel_num LEDC channel index (0-7), select from ledc_channel_t
  * @param intr_status The fade end interrupt status
  *
  * @return None
@@ -581,6 +582,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
     *intr_status = (value >> int_en_base) & 0xff;
 }
 
+/**
+ * @brief Get the address of the fade end interrupt status register.
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @return Pointer to the fade end interrupt status register.
+ */
+static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
+
 /**
  * @brief Clear fade end interrupt status
  *

components/hal/esp32h4/include/hal/uart_ll.h

@@ -350,6 +350,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
     return hw->int_st.val;
 }
 
+FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
 /**
  * @brief  Clear the UART interrupt status based on the given mask.
  *

components/hal/esp32p4/include/hal/ledc_ll.h

@@ -34,6 +34,8 @@ extern "C" {
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
 #define LEDC_LL_GLOBAL_CLOCKS      SOC_LEDC_CLKS
+/// Get the mask of the fade end interrupt status register.
+#define LEDC_LL_FADE_END_INTR_MASK  (0xffUL << LEDC_DUTY_CHNG_END_CH0_INT_ENA_S)
 
 // Channel tasks: ID, enable register and bit
 #define LEDC_LL_ETM_CHANNEL_TASK_ID(group, channel, task) \
@@ -647,7 +649,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
  *
  * @param hw Beginning address of the peripheral registers
  * @param speed_mode LEDC speed_mode, low-speed mode only
- * @param channel_num LEDC channel index (0-7), select from ledc_channel_t
  * @param intr_status The fade end interrupt status
  *
  * @return None
@@ -659,6 +660,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
     *intr_status = (value >> int_en_base) & 0xff;
 }
 
+/**
+ * @brief Get the address of the fade end interrupt status register.
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @return Pointer to the fade end interrupt status register.
+ */
+static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
+
 /**
  * @brief Clear fade end interrupt status
  *

components/hal/esp32p4/include/hal/uart_ll.h

@@ -659,6 +659,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
     return hw->int_st.val;
 }
 
+FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
 /**
  * @brief  Clear the UART interrupt status based on the given mask.
  *

components/hal/esp32s2/include/hal/cache_ll.h

@@ -282,7 +282,8 @@ static inline void cache_ll_resume_cache(uint32_t cache_level, cache_type_t type
  * @return  true: enabled; false: disabled
  */
 __attribute__((always_inline))
-static inline bool cache_ll_l1_is_icache_enabled(uint32_t cache_id){
+static inline bool cache_ll_l1_is_icache_enabled(uint32_t cache_id)
+{
     HAL_ASSERT(cache_id <= CACHE_LL_ID_ALL);
 
     bool enabled;

components/hal/esp32s2/include/hal/ledc_ll.h

@@ -30,6 +30,8 @@ extern "C" {
 #define LEDC_LL_OVF_CNT_MAX        (LEDC_OVF_NUM_LSCH0_V + 1)
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
+/// Get the mask of the fade end interrupt status register.
+#define LEDC_LL_FADE_END_INTR_MASK  (0xffUL << LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S)
 
 #define LEDC_LL_GLOBAL_CLOCKS { \
                                 LEDC_SLOW_CLK_APB, \
@@ -574,7 +576,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
  *
  * @param hw Beginning address of the peripheral registers
  * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode
- * @param channel_num LEDC channel index (0-7), select from ledc_channel_t
  * @param intr_status The fade end interrupt status
  *
  * @return None
@@ -586,6 +587,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
     *intr_status = (value >> int_en_base) & 0xff;
 }
 
+/**
+ * @brief Get the address of the fade end interrupt status register.
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @return Pointer to the fade end interrupt status register.
+ */
+static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
+
 /**
  * @brief Clear fade end interrupt status
  *

components/hal/esp32s2/include/hal/uart_ll.h

@@ -288,6 +288,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
     return hw->int_st.val;
 }
 
+FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
 /**
  * @brief  Clear the UART interrupt status based on the given mask.
  *

components/hal/esp32s3/include/hal/ledc_ll.h

@@ -30,6 +30,8 @@ extern "C" {
 #define LEDC_LL_OVF_CNT_MAX        (LEDC_OVF_NUM_LSCH0_V + 1)
 #define LEDC_LL_FRACTIONAL_BITS    (8)
 #define LEDC_LL_FRACTIONAL_MAX     ((1 << LEDC_LL_FRACTIONAL_BITS) - 1)
+/// Get the mask of the fade end interrupt status register.
+#define LEDC_LL_FADE_END_INTR_MASK  (0xffUL << LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S)
 
 #define LEDC_LL_GLOBAL_CLOCKS { \
                                 LEDC_SLOW_CLK_APB, \
@@ -535,7 +537,6 @@ static inline void ledc_ll_set_fade_end_intr(ledc_dev_t *hw, ledc_mode_t speed_m
  *
  * @param hw Beginning address of the peripheral registers
  * @param speed_mode LEDC speed_mode, high-speed mode or low-speed mode
- * @param channel_num LEDC channel index (0-7), select from ledc_channel_t
  * @param intr_status The fade end interrupt status
  *
  * @return None
@@ -547,6 +548,18 @@ static inline void ledc_ll_get_fade_end_intr_status(ledc_dev_t *hw, ledc_mode_t
     *intr_status = (value >> int_en_base) & 0xff;
 }
 
+/**
+ * @brief Get the address of the fade end interrupt status register.
+ *
+ * @param hw Beginning address of the peripheral registers
+ * @return Pointer to the fade end interrupt status register.
+ */
+static inline volatile void* ledc_ll_get_fade_end_intr_addr(ledc_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
+
 /**
  * @brief Clear fade end interrupt status
  *

components/hal/esp32s3/include/hal/uart_ll.h

@@ -345,6 +345,11 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
     return hw->int_ena.val;
 }
 
+FORCE_INLINE_ATTR volatile void* uart_ll_get_intr_status_reg(uart_dev_t *hw)
+{
+    return &hw->int_st.val;
+}
+
 /**
  * @brief  Read the UART rxfifo.
  *

components/hal/include/hal/ledc_hal.h

@@ -409,6 +409,14 @@ void ledc_hal_get_fade_end_intr_status(ledc_hal_context_t *hal, uint32_t *intr_s
  */
 void ledc_hal_clear_fade_end_intr_status(ledc_hal_context_t *hal, ledc_channel_t channel_num);
 
+/**
+ * @brief Get the address of the fade end interrupt status register.
+ *
+ * @param hal Context of the HAL layer
+ * @return Pointer to the fade end interrupt status register.
+ */
+volatile void* ledc_hal_get_fade_end_intr_addr(ledc_hal_context_t *hal);
+
 /**
  * @brief Get clock config of LEDC timer
  *

components/hal/include/hal/sdio_slave_hal.h

@@ -532,6 +532,14 @@ uint8_t sdio_slave_hal_host_get_reg(sdio_slave_context_t *hal, int pos);
  */
 void sdio_slave_hal_host_set_reg(sdio_slave_context_t *hal, int pos, uint8_t reg);
 
+/**
+ * Get the address of the interrupt status register.
+ *
+ * @param hal Context of the HAL layer.
+ * @return Address of the interrupt status register
+ */
+volatile void* sdio_slave_hal_get_intr_status_reg(sdio_slave_context_t *hal);
+
 #endif  // SOC_SDIO_SLAVE_SUPPORTED
 
 #ifdef __cplusplus

components/hal/include/hal/spi_hal.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/hal/include/hal/spi_slave_hal.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/hal/include/hal/uart_hal.h

@@ -106,6 +106,16 @@ typedef struct {
  */
 #define uart_hal_get_intr_ena_status(hal) uart_ll_get_intr_ena_status((hal)->dev)
 
+/**
+ * @brief Get the pointer to the UART interrupt status register
+ *
+ * @param  hal Context of the HAL layer
+ *
+ * @return UART interrupt status register
+ */
+#define uart_hal_get_intr_status_reg(hal) uart_ll_get_intr_status_reg((hal)->dev)
+
+
 /**
  * @brief Get the UART pattern char configuration
  *

components/hal/ledc_hal_iram.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -75,3 +75,8 @@ void ledc_hal_clear_fade_end_intr_status(ledc_hal_context_t *hal, ledc_channel_t
 {
     ledc_ll_clear_fade_end_intr_status(hal->dev, hal->speed_mode, channel_num);
 }
+
+volatile void* ledc_hal_get_fade_end_intr_addr(ledc_hal_context_t *hal)
+{
+    return ledc_ll_get_fade_end_intr_addr(hal->dev);
+}

components/hal/sdio_slave_hal.c

@@ -720,3 +720,8 @@ void sdio_slave_hal_slvint_fetch_clear(sdio_slave_context_t *hal, sdio_slave_ll_
 {
     sdio_slave_ll_slvint_fetch_clear(hal->slc, out_int_mask);
 }
+
+volatile void* sdio_slave_hal_get_intr_status_reg(sdio_slave_context_t *hal)
+{
+    return sdio_slave_ll_get_intr_status_reg(hal->slc);
+}

components/hal/spi_hal.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */