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Merge branch 'refactor/usb_leakage' into 'master'

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Refactor deep-sleep USB leakage current workaround

See merge request espressif/esp-idf!47746
This commit is contained in:
Tomas Rezucha
2026-04-22 15:43:02 +02:00
parent e5eec95f49 d02062f914
commit 47faecc3e4
11 changed files with 177 additions and 77 deletions
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components/esp_hal_usb/esp32h4/include/hal/usb_dwc_ll.h
+33 -4
View File
@@ -107,6 +107,17 @@ extern "C" {
#define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1) #define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1)
#define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0) #define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0)
/*
* OTG mode configuration values for the GHWCFG2 register
*/
#define USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG 0
#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG 1
#define USB_DWC_LL_GHWCFG_OTG_MODE_OTG 2
#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE 3
#define USB_DWC_LL_GHWCFG_OTG_MODE_DEVICE 4
#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST 5
#define USB_DWC_LL_GHWCFG_OTG_MODE_HOST 6
/* /*
* QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode. * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode.
* Each QTD describes one transfer. Scatter gather mode will automatically split * Each QTD describes one transfer. Scatter gather mode will automatically split
@@ -202,14 +213,14 @@ static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw)
hw->gusbcfg_reg.forcehstmode = 1; hw->gusbcfg_reg.forcehstmode = 1;
} }
static inline void usb_dwc_ll_gusbcfg_dis_hnp_cap(usb_dwc_dev_t *hw) static inline void usb_dwc_ll_gusbcfg_set_hnp_cap(usb_dwc_dev_t *hw, bool hnp_cap)
{ {
hw->gusbcfg_reg.hnpcap = 0; hw->gusbcfg_reg.hnpcap = hnp_cap;
} }
static inline void usb_dwc_ll_gusbcfg_dis_srp_cap(usb_dwc_dev_t *hw) static inline void usb_dwc_ll_gusbcfg_set_srp_cap(usb_dwc_dev_t *hw, bool srp_cap)
{ {
hw->gusbcfg_reg.srpcap = 0; hw->gusbcfg_reg.srpcap = srp_cap;
} }
static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal) static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal)
@@ -348,6 +359,24 @@ static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw)
// --------------------------- GHWCFGx Register -------------------------------- // --------------------------- GHWCFGx Register --------------------------------
static inline void usb_dwc_ll_ghwcfg_get_hnp_srp_cap(usb_dwc_dev_t *hw, bool *hnp_cap, bool *srp_cap)
{
const uint32_t otg_mode = hw->ghwcfg2_reg.otgmode;
if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG) {
*hnp_cap = true;
*srp_cap = true;
} else if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG ||
otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE ||
otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST) {
*hnp_cap = false;
*srp_cap = true;
} else {
*hnp_cap = false;
*srp_cap = false;
}
}
static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw) static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw)
{ {
return hw->ghwcfg3_reg.dfifodepth; return hw->ghwcfg3_reg.dfifodepth;
components/esp_hal_usb/esp32p4/include/hal/usb_dwc_ll.h
+33 -9
View File
@@ -109,6 +109,17 @@ extern "C" {
#define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1) #define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1)
#define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0) #define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0)
/*
* OTG mode configuration values for the GHWCFG2 register
*/
#define USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG 0
#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG 1
#define USB_DWC_LL_GHWCFG_OTG_MODE_OTG 2
#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE 3
#define USB_DWC_LL_GHWCFG_OTG_MODE_DEVICE 4
#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST 5
#define USB_DWC_LL_GHWCFG_OTG_MODE_HOST 6
/* /*
* QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode. * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode.
* Each QTD describes one transfer. Scatter gather mode will automatically split * Each QTD describes one transfer. Scatter gather mode will automatically split
@@ -204,19 +215,14 @@ static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw)
hw->gusbcfg_reg.forcehstmode = 1; hw->gusbcfg_reg.forcehstmode = 1;
} }
static inline void usb_dwc_ll_gusbcfg_en_hnp_cap(usb_dwc_dev_t *hw) static inline void usb_dwc_ll_gusbcfg_set_hnp_cap(usb_dwc_dev_t *hw, bool hnp_cap)
{ {
hw->gusbcfg_reg.hnpcap = 1; hw->gusbcfg_reg.hnpcap = hnp_cap;
} }
static inline void usb_dwc_ll_gusbcfg_dis_hnp_cap(usb_dwc_dev_t *hw) static inline void usb_dwc_ll_gusbcfg_set_srp_cap(usb_dwc_dev_t *hw, bool srp_cap)
{ {
hw->gusbcfg_reg.hnpcap = 0; hw->gusbcfg_reg.srpcap = srp_cap;
}
static inline void usb_dwc_ll_gusbcfg_dis_srp_cap(usb_dwc_dev_t *hw)
{
hw->gusbcfg_reg.srpcap = 0;
} }
static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal) static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal)
@@ -371,6 +377,24 @@ static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw)
// --------------------------- GHWCFGx Register -------------------------------- // --------------------------- GHWCFGx Register --------------------------------
static inline void usb_dwc_ll_ghwcfg_get_hnp_srp_cap(usb_dwc_dev_t *hw, bool *hnp_cap, bool *srp_cap)
{
const uint32_t otg_mode = hw->ghwcfg2_reg.otgmode;
if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG) {
*hnp_cap = true;
*srp_cap = true;
} else if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG ||
otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE ||
otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST) {
*hnp_cap = false;
*srp_cap = true;
} else {
*hnp_cap = false;
*srp_cap = false;
}
}
static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw) static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw)
{ {
return hw->ghwcfg3_reg.dfifodepth; return hw->ghwcfg3_reg.dfifodepth;
components/esp_hal_usb/esp32s2/include/hal/usb_dwc_ll.h
+33 -4
View File
@@ -107,6 +107,17 @@ extern "C" {
#define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1) #define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1)
#define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0) #define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0)
/*
* OTG mode configuration values for the GHWCFG2 register
*/
#define USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG 0
#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG 1
#define USB_DWC_LL_GHWCFG_OTG_MODE_OTG 2
#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE 3
#define USB_DWC_LL_GHWCFG_OTG_MODE_DEVICE 4
#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST 5
#define USB_DWC_LL_GHWCFG_OTG_MODE_HOST 6
/* /*
* QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode. * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode.
* Each QTD describes one transfer. Scatter gather mode will automatically split * Each QTD describes one transfer. Scatter gather mode will automatically split
@@ -202,14 +213,14 @@ static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw)
hw->gusbcfg_reg.forcehstmode = 1; hw->gusbcfg_reg.forcehstmode = 1;
} }
static inline void usb_dwc_ll_gusbcfg_dis_hnp_cap(usb_dwc_dev_t *hw) static inline void usb_dwc_ll_gusbcfg_set_hnp_cap(usb_dwc_dev_t *hw, bool hnp_cap)
{ {
hw->gusbcfg_reg.hnpcap = 0; hw->gusbcfg_reg.hnpcap = hnp_cap;
} }
static inline void usb_dwc_ll_gusbcfg_dis_srp_cap(usb_dwc_dev_t *hw) static inline void usb_dwc_ll_gusbcfg_set_srp_cap(usb_dwc_dev_t *hw, bool srp_cap)
{ {
hw->gusbcfg_reg.srpcap = 0; hw->gusbcfg_reg.srpcap = srp_cap;
} }
static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal) static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal)
@@ -346,6 +357,24 @@ static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw)
// --------------------------- GHWCFGx Register -------------------------------- // --------------------------- GHWCFGx Register --------------------------------
static inline void usb_dwc_ll_ghwcfg_get_hnp_srp_cap(usb_dwc_dev_t *hw, bool *hnp_cap, bool *srp_cap)
{
const uint32_t otg_mode = hw->ghwcfg2_reg.otgmode;
if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG) {
*hnp_cap = true;
*srp_cap = true;
} else if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG ||
otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE ||
otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST) {
*hnp_cap = false;
*srp_cap = true;
} else {
*hnp_cap = false;
*srp_cap = false;
}
}
static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw) static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw)
{ {
return hw->ghwcfg3_reg.dfifodepth; return hw->ghwcfg3_reg.dfifodepth;
components/esp_hal_usb/esp32s3/include/hal/usb_dwc_ll.h
+33 -4
View File
@@ -107,6 +107,17 @@ extern "C" {
#define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1) #define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1)
#define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0) #define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0)
/*
* OTG mode configuration values for the GHWCFG2 register
*/
#define USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG 0
#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG 1
#define USB_DWC_LL_GHWCFG_OTG_MODE_OTG 2
#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE 3
#define USB_DWC_LL_GHWCFG_OTG_MODE_DEVICE 4
#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST 5
#define USB_DWC_LL_GHWCFG_OTG_MODE_HOST 6
/* /*
* QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode. * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode.
* Each QTD describes one transfer. Scatter gather mode will automatically split * Each QTD describes one transfer. Scatter gather mode will automatically split
@@ -202,14 +213,14 @@ static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw)
hw->gusbcfg_reg.forcehstmode = 1; hw->gusbcfg_reg.forcehstmode = 1;
} }
static inline void usb_dwc_ll_gusbcfg_dis_hnp_cap(usb_dwc_dev_t *hw) static inline void usb_dwc_ll_gusbcfg_set_hnp_cap(usb_dwc_dev_t *hw, bool hnp_cap)
{ {
hw->gusbcfg_reg.hnpcap = 0; hw->gusbcfg_reg.hnpcap = hnp_cap;
} }
static inline void usb_dwc_ll_gusbcfg_dis_srp_cap(usb_dwc_dev_t *hw) static inline void usb_dwc_ll_gusbcfg_set_srp_cap(usb_dwc_dev_t *hw, bool srp_cap)
{ {
hw->gusbcfg_reg.srpcap = 0; hw->gusbcfg_reg.srpcap = srp_cap;
} }
static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal) static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal)
@@ -346,6 +357,24 @@ static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw)
// --------------------------- GHWCFGx Register -------------------------------- // --------------------------- GHWCFGx Register --------------------------------
static inline void usb_dwc_ll_ghwcfg_get_hnp_srp_cap(usb_dwc_dev_t *hw, bool *hnp_cap, bool *srp_cap)
{
const uint32_t otg_mode = hw->ghwcfg2_reg.otgmode;
if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG) {
*hnp_cap = true;
*srp_cap = true;
} else if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG ||
otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE ||
otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST) {
*hnp_cap = false;
*srp_cap = true;
} else {
*hnp_cap = false;
*srp_cap = false;
}
}
static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw) static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw)
{ {
return hw->ghwcfg3_reg.dfifodepth; return hw->ghwcfg3_reg.dfifodepth;
components/esp_hal_usb/esp32s31/include/hal/usb_dwc_ll.h
+33 -9
View File
@@ -107,6 +107,17 @@ extern "C" {
#define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1) #define USB_DWC_LL_INTR_CHAN_CHHLTD (1 << 1)
#define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0) #define USB_DWC_LL_INTR_CHAN_XFERCOMPL (1 << 0)
/*
* OTG mode configuration values for the GHWCFG2 register
*/
#define USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG 0
#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG 1
#define USB_DWC_LL_GHWCFG_OTG_MODE_OTG 2
#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE 3
#define USB_DWC_LL_GHWCFG_OTG_MODE_DEVICE 4
#define USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST 5
#define USB_DWC_LL_GHWCFG_OTG_MODE_HOST 6
/* /*
* QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode. * QTD (Queue Transfer Descriptor) structure used in Scatter/Gather DMA mode.
* Each QTD describes one transfer. Scatter gather mode will automatically split * Each QTD describes one transfer. Scatter gather mode will automatically split
@@ -202,19 +213,14 @@ static inline void usb_dwc_ll_gusbcfg_force_host_mode(usb_dwc_dev_t *hw)
hw->gusbcfg_reg.forcehstmode = 1; hw->gusbcfg_reg.forcehstmode = 1;
} }
static inline void usb_dwc_ll_gusbcfg_en_hnp_cap(usb_dwc_dev_t *hw) static inline void usb_dwc_ll_gusbcfg_set_hnp_cap(usb_dwc_dev_t *hw, bool hnp_cap)
{ {
hw->gusbcfg_reg.hnpcap = 1; hw->gusbcfg_reg.hnpcap = hnp_cap;
} }
static inline void usb_dwc_ll_gusbcfg_dis_hnp_cap(usb_dwc_dev_t *hw) static inline void usb_dwc_ll_gusbcfg_set_srp_cap(usb_dwc_dev_t *hw, bool srp_cap)
{ {
hw->gusbcfg_reg.hnpcap = 0; hw->gusbcfg_reg.srpcap = srp_cap;
}
static inline void usb_dwc_ll_gusbcfg_dis_srp_cap(usb_dwc_dev_t *hw)
{
hw->gusbcfg_reg.srpcap = 0;
} }
static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal) static inline void usb_dwc_ll_gusbcfg_set_timeout_cal(usb_dwc_dev_t *hw, uint8_t tout_cal)
@@ -360,6 +366,24 @@ static inline uint32_t usb_dwc_ll_gsnpsid_get_id(usb_dwc_dev_t *hw)
// --------------------------- GHWCFGx Register -------------------------------- // --------------------------- GHWCFGx Register --------------------------------
static inline void usb_dwc_ll_ghwcfg_get_hnp_srp_cap(usb_dwc_dev_t *hw, bool *hnp_cap, bool *srp_cap)
{
const uint32_t otg_mode = hw->ghwcfg2_reg.otgmode;
if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_HNP_SRP_OTG) {
*hnp_cap = true;
*srp_cap = true;
} else if (otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_OTG ||
otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_DEVICE ||
otg_mode == USB_DWC_LL_GHWCFG_OTG_MODE_SRP_HOST) {
*hnp_cap = false;
*srp_cap = true;
} else {
*hnp_cap = false;
*srp_cap = false;
}
}
static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw) static inline unsigned usb_dwc_ll_ghwcfg_get_fifo_depth(usb_dwc_dev_t *hw)
{ {
return hw->ghwcfg3_reg.dfifodepth; return hw->ghwcfg3_reg.dfifodepth;
components/esp_hal_usb/usb_dwc_hal.c
+8 -2
View File
@@ -125,9 +125,15 @@ static void set_defaults(usb_dwc_hal_context_t *hal)
usb_dwc_ll_set_stoppclk(hal->dev, false); usb_dwc_ll_set_stoppclk(hal->dev, false);
#endif // SOC_IS(ESP32P4) || SOC_IS(ESP32S31) #endif // SOC_IS(ESP32P4) || SOC_IS(ESP32S31)
usb_dwc_ll_gahbcfg_set_hbstlen(hal->dev, hbstlen); //Set AHB burst mode usb_dwc_ll_gahbcfg_set_hbstlen(hal->dev, hbstlen); //Set AHB burst mode
//GUSBCFG register //GUSBCFG register
usb_dwc_ll_gusbcfg_dis_hnp_cap(hal->dev); //Disable HNP bool hnp_cap, srp_cap;
usb_dwc_ll_gusbcfg_dis_srp_cap(hal->dev); //Disable SRP usb_dwc_ll_ghwcfg_get_hnp_srp_cap(hal->dev, &hnp_cap, &srp_cap);
// On targets where the USB controller is HNP capable, the data lines pull-downs are controlled by the USB controller.
// Enabling HNP capability will also enable the data line pull-downs in deep-sleep mode eliminating leakage current.
usb_dwc_ll_gusbcfg_set_hnp_cap(hal->dev, hnp_cap);
usb_dwc_ll_gusbcfg_set_srp_cap(hal->dev, false); //Disable SRP
// If this USB-DWC supports HS PHY, use it // If this USB-DWC supports HS PHY, use it
if (hal->constant_config.hsphy_type != 0) { if (hal->constant_config.hsphy_type != 0) {
components/esp_hw_support/include/esp_private/sleep_usb.h
+2 -13
View File
@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -13,8 +13,7 @@
extern "C" { extern "C" {
#endif #endif
#if SOC_USB_OTG_SUPPORTED #if SOC_USB_OTG_SUPPORTED && SOC_PM_SUPPORT_CNNT_PD
#if SOC_PM_SUPPORT_CNNT_PD
/** /**
* @brief Backup usb OTG phy bus_clock / stoppclk configuration and * @brief Backup usb OTG phy bus_clock / stoppclk configuration and
* before light sleep to avoid current leakage * before light sleep to avoid current leakage
@@ -27,16 +26,6 @@ void sleep_usb_otg_phy_backup_and_disable(void);
void sleep_usb_otg_phy_restore(void); void sleep_usb_otg_phy_restore(void);
#endif #endif
#if SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO
/**
* @brief The DP/DM part of the UTMI PHY circuit of esp32p4 that converts logic level to digital
* has no power off isolation, which will cause leakage when entering deepsleep.
* This problem can be workarounded by enabling USB-OTG's HNP (Host negotiation protocol)
* to enable DM pull-down to suppress leakage.
*/
void sleep_usb_suppress_deepsleep_leakage(void);
#endif
#endif
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
components/esp_hw_support/sleep_usb.c
+2 -16
View File
@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -7,15 +7,11 @@
#include <stdbool.h> #include <stdbool.h>
#include "soc/soc_caps.h" #include "soc/soc_caps.h"
#include "esp_private/sleep_usb.h" #include "esp_private/sleep_usb.h"
#include "esp_attr.h"
#if SOC_USB_OTG_SUPPORTED && (SOC_PM_SUPPORT_CNNT_PD || SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO) #if SOC_USB_OTG_SUPPORTED && SOC_PM_SUPPORT_CNNT_PD
#include "hal/usb_utmi_ll.h" #include "hal/usb_utmi_ll.h"
#include "hal/usb_dwc_ll.h" #include "hal/usb_dwc_ll.h"
#endif
#if SOC_USB_OTG_SUPPORTED
#if SOC_PM_SUPPORT_CNNT_PD
static bool s_usb_utmi_bus_clock_state, s_usb_utmi_stoppclk_state, s_usb_dwc_bvalid_override; static bool s_usb_utmi_bus_clock_state, s_usb_utmi_stoppclk_state, s_usb_dwc_bvalid_override;
void sleep_usb_otg_phy_backup_and_disable(void) void sleep_usb_otg_phy_backup_and_disable(void)
@@ -41,13 +37,3 @@ void sleep_usb_otg_phy_restore(void)
} }
} }
#endif #endif
#if SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO
void sleep_usb_suppress_deepsleep_leakage(void)
{
if (_usb_utmi_ll_bus_clock_is_enabled()) {
usb_dwc_ll_gusbcfg_en_hnp_cap(&USB_DWC_HS);
}
}
#endif
#endif
components/esp_hw_support/usb_phy/usb_phy.c
-11
View File
@@ -20,11 +20,6 @@
#include "hal/gpio_ll.h" #include "hal/gpio_ll.h"
#include "soc/soc_caps.h" #include "soc/soc_caps.h"
#if SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO
#include "esp_private/sleep_usb.h"
#include "esp_sleep.h"
#endif
#if (SOC_USB_FSLS_PHY_NUM > 0) #if (SOC_USB_FSLS_PHY_NUM > 0)
#define USB_PHY_FSLS_EXT_PHY_SUPPORTED USB_WRAP_LL_EXT_PHY_SUPPORTED #define USB_PHY_FSLS_EXT_PHY_SUPPORTED USB_WRAP_LL_EXT_PHY_SUPPORTED
#else #else
@@ -246,12 +241,6 @@ esp_err_t usb_new_phy(const usb_phy_config_t *config, usb_phy_handle_t *handle_r
} }
#endif #endif
#if SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO
if (phy_target == USB_PHY_TARGET_UTMI) {
esp_deep_sleep_register_hook(&sleep_usb_suppress_deepsleep_leakage);
}
#endif
ESP_RETURN_ON_FALSE(config, ESP_ERR_INVALID_ARG, USBPHY_TAG, "config argument is invalid"); ESP_RETURN_ON_FALSE(config, ESP_ERR_INVALID_ARG, USBPHY_TAG, "config argument is invalid");
ESP_RETURN_ON_FALSE(phy_target < USB_PHY_TARGET_MAX, ESP_ERR_INVALID_ARG, USBPHY_TAG, "specified PHY argument is invalid"); ESP_RETURN_ON_FALSE(phy_target < USB_PHY_TARGET_MAX, ESP_ERR_INVALID_ARG, USBPHY_TAG, "specified PHY argument is invalid");
ESP_RETURN_ON_FALSE(config->controller < USB_PHY_CTRL_MAX, ESP_ERR_INVALID_ARG, USBPHY_TAG, "specified source argument is invalid"); ESP_RETURN_ON_FALSE(config->controller < USB_PHY_CTRL_MAX, ESP_ERR_INVALID_ARG, USBPHY_TAG, "specified source argument is invalid");
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
-4
View File
@@ -1171,10 +1171,6 @@ config SOC_USB_UTMI_PHY_NUM
int int
default 1 default 1
config SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO
bool
default y
config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH config SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH
int int
default 16 default 16
components/soc/esp32p4/include/soc/soc_caps.h
-1
View File
@@ -434,7 +434,6 @@
// USB PHY Caps // USB PHY Caps
#define SOC_USB_UTMI_PHY_NUM (1U) #define SOC_USB_UTMI_PHY_NUM (1U)
#define SOC_USB_UTMI_PHY_NO_POWER_OFF_ISO 1
/*-------------------------- PARLIO CAPS --------------------------------------*/ /*-------------------------- PARLIO CAPS --------------------------------------*/
#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */ #define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */