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change(esp_hal_rtc_timer): unify lp_timer/rtc_timer naming to RTC_TIMER

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This commit is contained in:
wuzhenghui
2025-12-25 15:27:07 +08:00
parent 0d93c29143
commit 48ba430297
92 changed files with 1142 additions and 937 deletions
Download Patch File Download Diff File Expand all files Collapse all files
.gitlab/CODEOWNERS
+1
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@@ -96,6 +96,7 @@
/components/esp_gdbstub/ @esp-idf-codeowners/debugging
/components/esp_hal_*/ @esp-idf-codeowners/peripherals
/components/esp_hal_pmu/ @esp-idf-codeowners/power-management @esp-idf-codeowners/peripherals
/components/esp_hal_rtc_timer/ @esp-idf-codeowners/power-management @esp-idf-codeowners/peripherals
/components/esp_hid/ @esp-idf-codeowners/bluetooth
/components/esp_http_client/ @esp-idf-codeowners/app-utilities
/components/esp_http_server/ @esp-idf-codeowners/app-utilities
components/bootloader_support/CMakeLists.txt
+2 -2
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@@ -74,7 +74,7 @@ if(BOOTLOADER_BUILD OR CONFIG_APP_BUILD_TYPE_RAM)
"private_include")
set(priv_requires micro-ecc spi_flash efuse esp_bootloader_format esp_app_format esptool_py)
# `esp_hal_ana_conv` is required by bootloader_random_esp32xx.c
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_uart esp_hal_ana_conv)
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_uart esp_hal_ana_conv esp_hal_rtc_timer)
list(APPEND srcs
"src/bootloader_init.c"
"src/bootloader_clock_loader.c"
@@ -92,7 +92,7 @@ else()
# heap is required for `heap_memory_layout.h` header
set(priv_requires spi_flash mbedtls efuse heap esp_bootloader_format esp_app_format esptool_py)
# `esp_hal_ana_conv` is required by bootloader_random_esp32xx.c
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_uart esp_hal_ana_conv)
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_uart esp_hal_ana_conv esp_hal_rtc_timer)
endif()
if(BOOTLOADER_BUILD)
components/bootloader_support/src/bootloader_random.c
+3 -5
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@@ -9,9 +9,7 @@
#include "esp_cpu.h"
#include "soc/wdev_reg.h"
#if SOC_LP_TIMER_SUPPORTED
#include "hal/lp_timer_hal.h"
#endif
#include "hal/rtc_timer_hal.h"
#ifndef BOOTLOADER_BUILD
#include "esp_random.h"
@@ -47,7 +45,7 @@
assert(buffer != NULL);
for (size_t i = 0; i < length; i++) {
#if SOC_LP_TIMER_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
random = REG_READ(WDEV_RND_REG);
start = esp_cpu_get_cycle_count();
do {
@@ -57,7 +55,7 @@
// XOR the RT slow clock, which is asynchronous, to add some entropy and improve
// the distribution
uint32_t current_rtc_timer_counter = (lp_timer_hal_get_cycle_count() & 0xFF);
uint32_t current_rtc_timer_counter = (rtc_timer_hal_get_cycle_count(0) & 0xFF);
random = random ^ current_rtc_timer_counter;
buffer_bytes[i] = random & 0xFF;
components/esp_hal_pmu/CMakeLists.txt
+1 -1
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@@ -31,5 +31,5 @@ endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${public_include}
REQUIRES soc hal esp_rom esp_hal_rtc_timer
REQUIRES soc hal esp_rom
LDFRAGMENTS linker.lf)
components/esp_hal_pmu/esp32/include/hal/rtc_cntl_ll.h
+1 -8
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,15 +11,11 @@
#include "hal/clk_tree_ll.h"
#include "esp_rom_sys.h"
#include "hal/assert.h"
#include "hal/rtc_timer_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
// RTC timer functions moved to esp_hal_rtc_timer component
#define rtc_cntl_ll_set_wakeup_timer(t) rtc_timer_ll_set_wakeup_timer(t)
FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void)
{
REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
@@ -85,9 +81,6 @@ FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
}
// RTC timer functions moved to esp_hal_rtc_timer component
#define rtc_cntl_ll_get_rtc_time() rtc_timer_ll_get_rtc_time()
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
{
return REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_CAUSE);
components/esp_hal_pmu/esp32c2/include/hal/rtc_cntl_ll.h
+1 -8
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,15 +10,11 @@
#include "soc/rtc_cntl_reg.h"
#include "soc/syscon_reg.h"
#include "esp_attr.h"
#include "hal/rtc_timer_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
// RTC timer functions moved to esp_hal_rtc_timer component
#define rtc_cntl_ll_set_wakeup_timer(t) rtc_timer_ll_set_wakeup_timer(t)
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS);
@@ -60,9 +56,6 @@ FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
}
// RTC timer functions moved to esp_hal_rtc_timer component
#define rtc_cntl_ll_get_rtc_time() rtc_timer_ll_get_rtc_time()
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
{
return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);
components/esp_hal_pmu/esp32c3/include/hal/rtc_cntl_ll.h
+1 -8
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,15 +10,11 @@
#include "soc/rtc_cntl_reg.h"
#include "soc/syscon_reg.h"
#include "esp_attr.h"
#include "hal/rtc_timer_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
// RTC timer functions moved to esp_hal_rtc_timer component
#define rtc_cntl_ll_set_wakeup_timer(t) rtc_timer_ll_set_wakeup_timer(t)
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_gpio_get_wakeup_status(void)
{
return GET_PERI_REG_MASK(RTC_CNTL_GPIO_WAKEUP_REG, RTC_CNTL_GPIO_WAKEUP_STATUS);
@@ -66,9 +62,6 @@ FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
}
// RTC timer functions moved to esp_hal_rtc_timer component
#define rtc_cntl_ll_get_rtc_time() rtc_timer_ll_get_rtc_time()
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
{
return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);
components/esp_hal_pmu/esp32s2/include/hal/rtc_cntl_ll.h
+1 -8
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,15 +10,11 @@
#include "soc/rtc_cntl_reg.h"
#include "esp_attr.h"
#include "hal/assert.h"
#include "hal/rtc_timer_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
// RTC timer functions moved to esp_hal_rtc_timer component
#define rtc_cntl_ll_set_wakeup_timer(t) rtc_timer_ll_set_wakeup_timer(t)
FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void)
{
REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
@@ -80,9 +76,6 @@ FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
}
// RTC timer functions moved to esp_hal_rtc_timer component
#define rtc_cntl_ll_get_rtc_time() rtc_timer_ll_get_rtc_time()
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
{
return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);
components/esp_hal_pmu/esp32s3/include/hal/rtc_cntl_ll.h
+1 -8
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,7 +11,6 @@
#include "soc/syscon_reg.h"
#include "esp_attr.h"
#include "hal/assert.h"
#include "hal/rtc_timer_ll.h"
#ifdef __cplusplus
extern "C" {
@@ -20,9 +19,6 @@ extern "C" {
#define RTC_CNTL_LL_RETENTION_TARGET_CPU (BIT(0))
#define RTC_CNTL_LL_RETENTION_TARGET_TAGMEM (BIT(1))
// RTC timer functions moved to esp_hal_rtc_timer component
#define rtc_cntl_ll_set_wakeup_timer(t) rtc_timer_ll_set_wakeup_timer(t)
FORCE_INLINE_ATTR void rtc_cntl_ll_ext1_clear_wakeup_status(void)
{
REG_SET_BIT(RTC_CNTL_EXT_WAKEUP1_REG, RTC_CNTL_EXT_WAKEUP1_STATUS_CLR);
@@ -161,9 +157,6 @@ FORCE_INLINE_ATTR void rtc_cntl_ll_sleep_enable(void)
SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
}
// RTC timer functions moved to esp_hal_rtc_timer component
#define rtc_cntl_ll_get_rtc_time() rtc_timer_ll_get_rtc_time()
FORCE_INLINE_ATTR uint32_t rtc_cntl_ll_get_wakeup_cause(void)
{
return REG_GET_FIELD(RTC_CNTL_SLP_WAKEUP_CAUSE_REG, RTC_CNTL_WAKEUP_CAUSE);
components/esp_hal_pmu/esp32s31/include/hal/pmu_ll.h
+1 -1
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@@ -22,7 +22,7 @@
extern "C" {
#endif
// TODO: ["ESP32S31"] IDF-14653
// TODO: ["ESP32S31"] IDF-14642
#ifdef __cplusplus
}
components/esp_hal_pmu/include/hal/rtc_hal.h
+3 -5
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@@ -10,7 +10,9 @@
#include "soc/soc_caps.h"
#include "hal/gpio_types.h"
#if SOC_IS(ESP32) || SOC_IS(ESP32C2) || SOC_IS(ESP32C3) || SOC_IS(ESP32S2) || SOC_IS(ESP32S3)
#if SOC_PMU_SUPPORTED || SOC_IS(ESP32S31) // TODO: ["ESP32S31"] IDF-14653
#include "hal/pmu_ll.h"
#else
#include "hal/rtc_cntl_ll.h"
#endif
@@ -22,10 +24,6 @@
#include "hal/lp_aon_ll.h"
#endif
#if SOC_PM_EXT1_WAKEUP_BY_PMU
#include "hal/pmu_ll.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
components/esp_hal_rtc_timer/README.md
+3 -10
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@@ -8,18 +8,11 @@
The `esp_hal_rtc_timer` component provides a **unified Hardware Abstraction Layer** for RTC Timer peripherals across all ESP-IDF supported targets. This HAL abstracts hardware differences between legacy RTC timer implementations (in RTC_CNTL peripheral) and modern low-power timer implementations, providing a consistent API for wakeup timer configuration and RTC time reading across different ESP chip families.
The component consolidates timer functionality from two different hardware implementations:
- **RTC_TIMER_LL_HARDWARE_V1**: Legacy RTC timer functionality in RTC_CNTL peripheral (ESP32, ESP32C2, ESP32C3, ESP32S2, ESP32S3)
- **RTC_TIMER_LL_HARDWARE_V2**: Newer LP timer peripheral
## Hardware Version Abstraction
The component uses hardware version macros defined in LL headers to automatically select the correct implementation:
- **RTC_TIMER_LL_HARDWARE_V1**: Defined in LL headers for legacy chips (ESP32, ESP32C2, ESP32C3, ESP32S2, ESP32S3)
- **RTC_TIMER_LL_HARDWARE_V2**: Defined in LL headers for modern chips (ESP32C5, ESP32C6, ESP32C61, ESP32H2, ESP32H21, ESP32H4, ESP32P4)
- **SOC_RTC_TIMER_V1_SUPPORTED**: Legacy RTC timer functionality in RTC_CNTL peripheral (ESP32, ESP32C2, ESP32C3, ESP32S2, ESP32S3)
- **SOC_RTC_TIMER_V2_SUPPORTED**: Newer LP timer peripheral (ESP32C5, ESP32C6, ESP32C61, ESP32H2, ESP32H21, ESP32H4, ESP32P4)
### Unified HAL API (All Chips)
- Wakeup timer configuration via `rtc_timer_hal_set_wakeup_timer()`
- Wakeup timer configuration via `rtc_timer_hal_set_wakeup_time()`
- RTC time reading via `rtc_timer_hal_get_cycle_count()`
### Hardware-Specific LL API
components/esp_hal_rtc_timer/esp32/include/hal/rtc_timer_ll.h
+21 -6
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,30 +7,45 @@
#pragma once
#include "soc/soc.h"
#include "soc/rtc_cntl_reg.h"
#include "esp_attr.h"
#include "hal/clk_tree_ll.h"
#include "esp_rom_sys.h"
#include "hal/log.h"
#include "hal/assert.h"
#include "hal/clk_tree_ll.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_timer(uint64_t t)
/**
* @brief Set wakeup timer value
*
* @param timer_id Timer ID (ignored for V1 hardware, only one timer supported)
* @param ticks Timer value in RTC slow clock ticks
*/
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_time(uint8_t timer_id, uint64_t t)
{
(void)timer_id; // V1 hardware only supports one timer
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
}
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_rtc_time(void)
/**
* @brief Get current RTC timer cycle count
*
* @param timer_id Timer ID (ignored for V1 hardware, only one timer supported)
* @return Current RTC time in RTC slow clock ticks
*/
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_cycle_count(uint8_t timer_id)
{
(void)timer_id; // V1 hardware only supports one timer
SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
int attempts = 1000;
while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) {
esp_rom_delay_us(1);
if (attempts) {
if (--attempts == 0 && clk_ll_xtal32k_digi_is_enabled()) {
esp_rom_printf("32KHz xtal has been stopped\n");
HAL_LOGW("rtc_timer_ll", "32KHz xtal has been stopped.");
}
}
}
components/esp_hal_rtc_timer/esp32c2/include/hal/rtc_timer_ll.h
+17 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -15,8 +15,15 @@
extern "C" {
#endif
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_timer(uint64_t t)
/**
* @brief Set wakeup timer value
*
* @param timer_id Timer ID (ignored for V1 hardware, only one timer supported)
* @param ticks Timer value in RTC slow clock ticks
*/
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_time(uint8_t timer_id, uint64_t t)
{
(void)timer_id; // V1 hardware only supports one timer
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
@@ -24,8 +31,15 @@ FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_timer(uint64_t t)
SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
}
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_rtc_time(void)
/**
* @brief Get current RTC timer cycle count
*
* @param timer_id Timer ID (ignored for V1 hardware, only one timer supported)
* @return Current RTC time in RTC slow clock ticks
*/
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_cycle_count(uint8_t timer_id)
{
(void)timer_id; // V1 hardware only supports one timer
SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
components/esp_hal_rtc_timer/esp32c3/include/hal/rtc_timer_ll.h
+17 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -15,8 +15,15 @@
extern "C" {
#endif
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_timer(uint64_t t)
/**
* @brief Set wakeup timer value
*
* @param timer_id Timer ID (ignored for V1 hardware, only one timer supported)
* @param ticks Timer value in RTC slow clock ticks
*/
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_time(uint8_t timer_id, uint64_t t)
{
(void)timer_id; // V1 hardware only supports one timer
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
@@ -24,8 +31,15 @@ FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_timer(uint64_t t)
SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
}
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_rtc_time(void)
/**
* @brief Get current RTC timer cycle count
*
* @param timer_id Timer ID (ignored for V1 hardware, only one timer supported)
* @return Current RTC time in RTC slow clock ticks
*/
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_cycle_count(uint8_t timer_id)
{
(void)timer_id; // V1 hardware only supports one timer
SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
components/esp_hal_rtc_timer/esp32c5/include/hal/lp_timer_ll.h
-83
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@@ -1,83 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-C5 LP_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_aon_reg.h"
#include "hal/lp_timer_types.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, main_timer_tar_high0, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, main_timer_tar_low0, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.main_timer_tar_en0 = en;
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].lo, main_timer_buf0_low);
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].hi, main_timer_buf0_high);
}
FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
dev->update.main_timer_update = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.soc_wakeup_int_clr = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.overflow_clr = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *dev)
{
dev->lp_int_clr.main_timer_lp_int_clr = 1;
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_lp_intr_raw(lp_timer_dev_t *dev)
{
return dev->lp_int_raw.val;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_intsts_mask(lp_timer_dev_t *dev, uint32_t mask)
{
dev->lp_int_clr.val = mask;
}
FORCE_INLINE_ATTR void lp_timer_ll_lp_alarm_intr_enable(lp_timer_dev_t *dev, bool enable)
{
dev->lp_int_ena.main_timer_lp_int_ena = enable;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/esp32c5/include/hal/rtc_timer_ll.h
+127
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@@ -0,0 +1,127 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-C5 RTC_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_aon_reg.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void rtc_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, main_timer_tar_high0, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, main_timer_tar_low0, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void rtc_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.main_timer_tar_en0 = en;
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].lo, main_timer_buf0_low);
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].hi, main_timer_buf0_high);
}
FORCE_INLINE_ATTR void rtc_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
dev->update.main_timer_update = 1;
}
/**
* @brief Clear alarm interrupt status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
*/
FORCE_INLINE_ATTR void rtc_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev, uint8_t timer_id)
{
if (timer_id == 0) {
dev->int_clr.soc_wakeup_int_clr = 1;
} else if (timer_id == 1) {
dev->lp_int_clr.main_timer_lp_int_clr = 1;
}
}
/**
* @brief Get interrupt raw status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
* @return Interrupt raw status value
*/
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_intr_raw(lp_timer_dev_t *dev, uint8_t timer_id)
{
if (timer_id == 0) {
return dev->int_raw.val;
} else if (timer_id == 1) {
return dev->lp_int_raw.val;
}
return 0;
}
/**
* @brief Enable/disable alarm interrupt
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
* @param enable Enable or disable interrupt
*/
FORCE_INLINE_ATTR void rtc_timer_ll_alarm_intr_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool enable)
{
if (timer_id == 0) {
dev->int_ena.soc_wakeup_int_ena = enable;
} else if (timer_id == 1) {
dev->lp_int_ena.main_timer_lp_int_ena = enable;
}
}
/**
* @brief Set wakeup timer value
*
* @param timer_id Timer ID
* @param ticks Timer value in RTC slow clock ticks
*/
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_time(uint8_t timer_id, uint64_t ticks)
{
rtc_timer_ll_clear_alarm_intr_status(&LP_TIMER, timer_id);
rtc_timer_ll_set_alarm_target(&LP_TIMER, timer_id, ticks);
rtc_timer_ll_set_target_enable(&LP_TIMER, timer_id, true);
}
/**
* @brief Get current RTC timer cycle count
*
* @param timer_id Timer ID
* @return Current RTC time in RTC slow clock ticks
*/
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_cycle_count(uint8_t timer_id)
{
rtc_timer_ll_counter_snapshot(&LP_TIMER);
uint32_t lo = rtc_timer_ll_get_counter_value_low(&LP_TIMER, timer_id);
uint32_t hi = rtc_timer_ll_get_counter_value_high(&LP_TIMER, timer_id);
return ((uint64_t)hi << 32) | lo;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/esp32c6/include/hal/lp_timer_ll.h
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/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-C6 LP_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_aon_reg.h"
#include "hal/lp_timer_types.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, target_hi, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, target_lo, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.enable = en;
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].lo, counter_lo);
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].hi, counter_hi);
}
FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
dev->update.update = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.alarm = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.overflow = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *dev)
{
dev->lp_int_clr.alarm = 1;
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_lp_intr_raw(lp_timer_dev_t *dev)
{
return dev->lp_int_raw.val;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_intsts_mask(lp_timer_dev_t *dev, uint32_t mask)
{
dev->lp_int_clr.val = mask;
}
FORCE_INLINE_ATTR void lp_timer_ll_lp_alarm_intr_enable(lp_timer_dev_t *dev, bool enable)
{
dev->lp_int_en.alarm = enable;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/esp32c6/include/hal/rtc_timer_ll.h
+127
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/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-C6 RTC_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_aon_reg.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void rtc_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, target_hi, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, target_lo, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void rtc_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.enable = en;
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].lo, counter_lo);
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].hi, counter_hi);
}
FORCE_INLINE_ATTR void rtc_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
dev->update.update = 1;
}
/**
* @brief Clear alarm interrupt status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
*/
FORCE_INLINE_ATTR void rtc_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev, uint8_t timer_id)
{
if (timer_id == 0) {
dev->int_clr.alarm = 1;
} else if (timer_id == 1) {
dev->lp_int_clr.alarm = 1;
}
}
/**
* @brief Get interrupt raw status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
* @return Interrupt raw status value
*/
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_intr_raw(lp_timer_dev_t *dev, uint8_t timer_id)
{
if (timer_id == 0) {
return dev->int_raw.val;
} else if (timer_id == 1) {
return dev->lp_int_raw.val;
}
return 0;
}
/**
* @brief Enable/disable alarm interrupt
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
* @param enable Enable or disable interrupt
*/
FORCE_INLINE_ATTR void rtc_timer_ll_alarm_intr_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool enable)
{
if (timer_id == 0) {
dev->int_en.alarm = enable;
} else if (timer_id == 1) {
dev->lp_int_en.alarm = enable;
}
}
/**
* @brief Set wakeup timer value
*
* @param timer_id Timer ID
* @param ticks Timer value in RTC slow clock ticks
*/
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_time(uint8_t timer_id, uint64_t ticks)
{
rtc_timer_ll_clear_alarm_intr_status(&LP_TIMER, timer_id);
rtc_timer_ll_set_alarm_target(&LP_TIMER, timer_id, ticks);
rtc_timer_ll_set_target_enable(&LP_TIMER, timer_id, true);
}
/**
* @brief Get current RTC timer cycle count
*
* @param timer_id Timer ID
* @return Current RTC time in RTC slow clock ticks
*/
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_cycle_count(uint8_t timer_id)
{
rtc_timer_ll_counter_snapshot(&LP_TIMER);
uint32_t lo = rtc_timer_ll_get_counter_value_low(&LP_TIMER, timer_id);
uint32_t hi = rtc_timer_ll_get_counter_value_high(&LP_TIMER, timer_id);
return ((uint64_t)hi << 32) | lo;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/esp32c61/include/hal/lp_timer_ll.h
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@@ -1,83 +0,0 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-C61 LP_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_aon_reg.h"
#include "hal/lp_timer_types.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, main_timer_tar_high0, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, main_timer_tar_low0, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.main_timer_tar_en0 = en;
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].lo, main_timer_buf0_low);
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].hi, main_timer_buf0_high);
}
FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
dev->update.main_timer_update = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.soc_wakeup_int_clr = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.overflow_clr = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *dev)
{
dev->lp_int_clr.main_timer_lp_int_clr = 1;
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_lp_intr_raw(lp_timer_dev_t *dev)
{
return dev->lp_int_raw.val;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_intsts_mask(lp_timer_dev_t *dev, uint32_t mask)
{
dev->lp_int_clr.val = mask;
}
FORCE_INLINE_ATTR void lp_timer_ll_lp_alarm_intr_enable(lp_timer_dev_t *dev, bool enable)
{
dev->lp_int_ena.main_timer_lp_int_ena = enable;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/esp32c61/include/hal/rtc_timer_ll.h
+127
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/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-C61 RTC_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_aon_reg.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void rtc_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, main_timer_tar_high0, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, main_timer_tar_low0, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void rtc_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.main_timer_tar_en0 = en;
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].lo, main_timer_buf0_low);
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].hi, main_timer_buf0_high);
}
FORCE_INLINE_ATTR void rtc_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
dev->update.main_timer_update = 1;
}
/**
* @brief Clear alarm interrupt status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
*/
FORCE_INLINE_ATTR void rtc_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev, uint8_t timer_id)
{
if (timer_id == 0) {
dev->int_clr.soc_wakeup_int_clr = 1;
} else if (timer_id == 1) {
dev->lp_int_clr.main_timer_lp_int_clr = 1;
}
}
/**
* @brief Get interrupt raw status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
* @return Interrupt raw status value
*/
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_intr_raw(lp_timer_dev_t *dev, uint8_t timer_id)
{
if (timer_id == 0) {
return dev->int_raw.val;
} else if (timer_id == 1) {
return dev->lp_int_raw.val;
}
return 0;
}
/**
* @brief Enable/disable alarm interrupt
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
* @param enable Enable or disable interrupt
*/
FORCE_INLINE_ATTR void rtc_timer_ll_alarm_intr_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool enable)
{
if (timer_id == 0) {
dev->int_ena.soc_wakeup_int_ena = enable;
} else if (timer_id == 1) {
dev->lp_int_ena.main_timer_lp_int_ena = enable;
}
}
/**
* @brief Set wakeup timer value
*
* @param timer_id Timer ID
* @param ticks Timer value in RTC slow clock ticks
*/
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_time(uint8_t timer_id, uint64_t ticks)
{
rtc_timer_ll_clear_alarm_intr_status(&LP_TIMER, timer_id);
rtc_timer_ll_set_alarm_target(&LP_TIMER, timer_id, ticks);
rtc_timer_ll_set_target_enable(&LP_TIMER, timer_id, true);
}
/**
* @brief Get current RTC timer cycle count
*
* @param timer_id Timer ID
* @return Current RTC time in RTC slow clock ticks
*/
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_cycle_count(uint8_t timer_id)
{
rtc_timer_ll_counter_snapshot(&LP_TIMER);
uint32_t lo = rtc_timer_ll_get_counter_value_low(&LP_TIMER, timer_id);
uint32_t hi = rtc_timer_ll_get_counter_value_high(&LP_TIMER, timer_id);
return ((uint64_t)hi << 32) | lo;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/esp32h2/include/hal/lp_timer_ll.h
-67
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/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-H2 LP_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_aon_reg.h"
#include "hal/lp_timer_types.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, target_hi, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, target_lo, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.enable = en;
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].lo, counter_lo);
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].hi, counter_hi);
}
FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
dev->update.update = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.alarm = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.overflow = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_lp_alarm_intr_enable(lp_timer_dev_t *dev, bool enable)
{
dev->lp_int_en.alarm = enable;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/esp32h2/include/hal/rtc_timer_ll.h
+117
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/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-H2 RTC_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_aon_reg.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void rtc_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, target_hi, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, target_lo, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void rtc_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.enable = en;
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].lo, counter_lo);
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].hi, counter_hi);
}
FORCE_INLINE_ATTR void rtc_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
dev->update.update = 1;
}
/**
* @brief Clear alarm interrupt status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (ignored for ESP32-H2, always clears main timer interrupt)
*/
FORCE_INLINE_ATTR void rtc_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev, uint8_t timer_id)
{
(void)timer_id; // ESP32-H2 only supports main timer
dev->int_clr.alarm = 1;
}
/**
* @brief Get interrupt raw status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (ignored for ESP32-H2, always returns main timer interrupt status)
* @return Interrupt raw status value
*/
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_intr_raw(lp_timer_dev_t *dev, uint8_t timer_id)
{
(void)timer_id; // ESP32-H2 only supports main timer
return dev->int_raw.val;
}
/**
* @brief Enable/disable alarm interrupt
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (ignored for ESP32-H2, always controls main timer interrupt)
* @param enable Enable or disable interrupt
*/
FORCE_INLINE_ATTR void rtc_timer_ll_alarm_intr_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool enable)
{
(void)timer_id; // ESP32-H2 only supports main timer
dev->int_en.alarm = enable;
}
/**
* @brief Set wakeup timer value
*
* @param timer_id Timer ID
* @param ticks Timer value in RTC slow clock ticks
*/
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_time(uint8_t timer_id, uint64_t ticks)
{
rtc_timer_ll_clear_alarm_intr_status(&LP_TIMER, timer_id);
rtc_timer_ll_set_alarm_target(&LP_TIMER, timer_id, ticks);
rtc_timer_ll_set_target_enable(&LP_TIMER, timer_id, true);
}
/**
* @brief Get current RTC timer cycle count
* Note: For ESP32-H2, counter[timer_id] is used after snapshot
*
* @param timer_id Timer ID
* @return Current RTC time in RTC slow clock ticks
*/
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_cycle_count(uint8_t timer_id)
{
rtc_timer_ll_counter_snapshot(&LP_TIMER);
uint32_t lo = rtc_timer_ll_get_counter_value_low(&LP_TIMER, timer_id);
uint32_t hi = rtc_timer_ll_get_counter_value_high(&LP_TIMER, timer_id);
return ((uint64_t)hi << 32) | lo;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/esp32h21/include/hal/lp_timer_ll.h
-62
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@@ -1,62 +0,0 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-H2 LP_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_aon_reg.h"
#include "hal/lp_timer_types.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, target_hi, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, target_lo, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.enable = en;
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].lo, counter_lo);
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].hi, counter_hi);
}
FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
dev->update.update = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.alarm = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.overflow = 1;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/esp32h21/include/hal/rtc_timer_ll.h
+117
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-H2 RTC_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_aon_reg.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void rtc_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, target_hi, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, target_lo, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void rtc_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.enable = en;
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].lo, counter_lo);
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].hi, counter_hi);
}
FORCE_INLINE_ATTR void rtc_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
dev->update.update = 1;
}
/**
* @brief Clear alarm interrupt status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (ignored for ESP32-H21, always clears main timer interrupt)
*/
FORCE_INLINE_ATTR void rtc_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev, uint8_t timer_id)
{
(void)timer_id; // ESP32-H21 only supports main timer
dev->int_clr.alarm = 1;
}
/**
* @brief Get interrupt raw status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (ignored for ESP32-H21, always returns main timer interrupt status)
* @return Interrupt raw status value
*/
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_intr_raw(lp_timer_dev_t *dev, uint8_t timer_id)
{
(void)timer_id; // ESP32-H21 only supports main timer
return dev->int_raw.val;
}
/**
* @brief Enable/disable alarm interrupt
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (ignored for ESP32-H21, always controls main timer interrupt)
* @param enable Enable or disable interrupt
*/
FORCE_INLINE_ATTR void rtc_timer_ll_alarm_intr_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool enable)
{
(void)timer_id; // ESP32-H21 only supports main timer
dev->int_en.alarm = enable;
}
/**
* @brief Set wakeup timer value
*
* @param timer_id Timer ID
* @param ticks Timer value in RTC slow clock ticks
*/
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_time(uint8_t timer_id, uint64_t ticks)
{
rtc_timer_ll_clear_alarm_intr_status(&LP_TIMER, timer_id);
rtc_timer_ll_set_alarm_target(&LP_TIMER, timer_id, ticks);
rtc_timer_ll_set_target_enable(&LP_TIMER, timer_id, true);
}
/**
* @brief Get current RTC timer cycle count
* Note: For ESP32-H21, counter[timer_id] is used after snapshot
*
* @param timer_id Timer ID
* @return Current RTC time in RTC slow clock ticks
*/
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_cycle_count(uint8_t timer_id)
{
rtc_timer_ll_counter_snapshot(&LP_TIMER);
uint32_t lo = rtc_timer_ll_get_counter_value_low(&LP_TIMER, timer_id);
uint32_t hi = rtc_timer_ll_get_counter_value_high(&LP_TIMER, timer_id);
return ((uint64_t)hi << 32) | lo;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/esp32h4/include/hal/lp_timer_ll.h
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-H4 LP_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_aon_reg.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, main_timer_tar_high0, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, main_timer_tar_low0, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.main_timer_tar_en0 = en;
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].lo, main_timer_buf0_low);
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].hi, main_timer_buf0_high);
}
FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
dev->update.main_timer_update = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.soc_wakeup_int_clr = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.overflow_clr = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *dev)
{
dev->lp_int_clr.main_timer_lp_int_clr = 1;
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_lp_intr_raw(lp_timer_dev_t *dev)
{
return dev->lp_int_raw.val;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_intsts_mask(lp_timer_dev_t *dev, uint32_t mask)
{
dev->lp_int_clr.val = mask;
}
FORCE_INLINE_ATTR void lp_timer_ll_lp_alarm_intr_enable(lp_timer_dev_t *dev, bool enable)
{
dev->lp_int_ena.main_timer_lp_int_ena = enable;
}
/* Record the start and finish times for one-time regdma work */
FORCE_INLINE_ATTR void lp_timer_ll_record_regdma_work_time_enable(lp_timer_dev_t *dev, bool en)
{
dev->update.main_timer_regdma_work = en;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/esp32h4/include/hal/rtc_timer_ll.h
+133
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/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-H4 RTC_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_aon_reg.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void rtc_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, main_timer_tar_high0, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, main_timer_tar_low0, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void rtc_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.main_timer_tar_en0 = en;
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].lo, main_timer_buf0_low);
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t buffer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[buffer_id].hi, main_timer_buf0_high);
}
FORCE_INLINE_ATTR void rtc_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
dev->update.main_timer_update = 1;
}
/**
* @brief Clear alarm interrupt status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
*/
FORCE_INLINE_ATTR void rtc_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev, uint8_t timer_id)
{
if (timer_id == 0) {
dev->int_clr.soc_wakeup_int_clr = 1;
} else if (timer_id == 1) {
dev->lp_int_clr.main_timer_lp_int_clr = 1;
}
}
/**
* @brief Get interrupt raw status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
* @return Interrupt raw status value
*/
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_intr_raw(lp_timer_dev_t *dev, uint8_t timer_id)
{
if (timer_id == 0) {
return dev->int_raw.val;
} else if (timer_id == 1) {
return dev->lp_int_raw.val;
}
return 0;
}
/**
* @brief Enable/disable alarm interrupt
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
* @param enable Enable or disable interrupt
*/
FORCE_INLINE_ATTR void rtc_timer_ll_alarm_intr_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool enable)
{
if (timer_id == 0) {
dev->int_ena.soc_wakeup_int_ena = enable;
} else if (timer_id == 1) {
dev->lp_int_ena.main_timer_lp_int_ena = enable;
}
}
/* Record the start and finish times for one-time regdma work */
FORCE_INLINE_ATTR void rtc_timer_ll_record_regdma_work_time_enable(lp_timer_dev_t *dev, bool en)
{
dev->update.main_timer_regdma_work = en;
}
/**
* @brief Set wakeup timer value
*
* @param timer_id Timer ID
* @param ticks Timer value in RTC slow clock ticks
*/
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_time(uint8_t timer_id, uint64_t ticks)
{
rtc_timer_ll_clear_alarm_intr_status(&LP_TIMER, timer_id);
rtc_timer_ll_set_alarm_target(&LP_TIMER, timer_id, ticks);
rtc_timer_ll_set_target_enable(&LP_TIMER, timer_id, true);
}
/**
* @brief Get current RTC timer cycle count
*
* @param timer_id Timer ID
* @return Current RTC time in RTC slow clock ticks
*/
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_cycle_count(uint8_t timer_id)
{
rtc_timer_ll_counter_snapshot(&LP_TIMER);
uint32_t lo = rtc_timer_ll_get_counter_value_low(&LP_TIMER, timer_id);
uint32_t hi = rtc_timer_ll_get_counter_value_high(&LP_TIMER, timer_id);
return ((uint64_t)hi << 32) | lo;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/esp32p4/include/hal/lp_timer_ll.h
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@@ -1,83 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-P4 LP_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_system_reg.h"
#include "hal/lp_timer_types.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void lp_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, target_hi, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, target_lo, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void lp_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.enable = en;
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].lo, counter_lo);
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].hi, counter_hi);
}
FORCE_INLINE_ATTR void lp_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
dev->update.main_timer_update = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.soc_wakeup_int_clr = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_overflow_intr_status(lp_timer_dev_t *dev)
{
dev->int_clr.overflow_clr = 1;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_dev_t *dev)
{
dev->lp_int_clr.main_timer_lp_int_clr = 1;
}
FORCE_INLINE_ATTR uint32_t lp_timer_ll_get_lp_intr_raw(lp_timer_dev_t *dev)
{
return dev->lp_int_raw.val;
}
FORCE_INLINE_ATTR void lp_timer_ll_clear_lp_intsts_mask(lp_timer_dev_t *dev, uint32_t mask)
{
dev->lp_int_clr.val = mask;
}
FORCE_INLINE_ATTR void lp_timer_ll_lp_alarm_intr_enable(lp_timer_dev_t *dev, bool enable)
{
dev->lp_int_ena.main_timer_lp_int_ena = enable;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/esp32p4/include/hal/rtc_timer_ll.h
+128
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/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-P4 RTC_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_system_reg.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
FORCE_INLINE_ATTR void rtc_timer_ll_set_alarm_target(lp_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, target_hi, (value >> 32) & 0xFFFF);
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, target_lo, value & 0xFFFFFFFF);
}
FORCE_INLINE_ATTR void rtc_timer_ll_set_target_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool en)
{
dev->target[timer_id].hi.enable = en;
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_low(lp_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].lo, counter_lo);
}
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_high(lp_timer_dev_t *dev, uint8_t timer_id)
{
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].hi, counter_hi);
}
FORCE_INLINE_ATTR void rtc_timer_ll_counter_snapshot(lp_timer_dev_t *dev)
{
dev->update.main_timer_update = 1;
}
/**
* @brief Clear alarm interrupt status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
*/
FORCE_INLINE_ATTR void rtc_timer_ll_clear_alarm_intr_status(lp_timer_dev_t *dev, uint8_t timer_id)
{
if (timer_id == 0) {
dev->int_clr.soc_wakeup_int_clr = 1;
} else if (timer_id == 1) {
dev->lp_int_clr.main_timer_lp_int_clr = 1;
}
}
/**
* @brief Get interrupt raw status
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
* @return Interrupt raw status value
*/
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_intr_raw(lp_timer_dev_t *dev, uint8_t timer_id)
{
if (timer_id == 0) {
return dev->int_raw.val;
} else if (timer_id == 1) {
return dev->lp_int_raw.val;
}
return 0;
}
/**
* @brief Enable/disable alarm interrupt
*
* @param dev LP timer peripheral instance
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
* @param enable Enable or disable interrupt
*/
FORCE_INLINE_ATTR void rtc_timer_ll_alarm_intr_enable(lp_timer_dev_t *dev, uint8_t timer_id, bool enable)
{
if (timer_id == 0) {
dev->int_ena.soc_wakeup_int_ena = enable;
} else if (timer_id == 1) {
dev->lp_int_ena.main_timer_lp_int_ena = enable;
}
}
/**
* @brief Set wakeup timer value
*
* @param timer_id Timer ID
* @param ticks Timer value in RTC slow clock ticks
*/
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_time(uint8_t timer_id, uint64_t ticks)
{
rtc_timer_ll_clear_alarm_intr_status(&LP_TIMER, timer_id);
rtc_timer_ll_set_alarm_target(&LP_TIMER, timer_id, ticks);
rtc_timer_ll_set_target_enable(&LP_TIMER, timer_id, true);
}
/**
* @brief Get current RTC timer cycle count
* Note: For ESP32-P4, counter[timer_id] is used after snapshot
*
* @param timer_id Timer ID
* @return Current RTC time in RTC slow clock ticks
*/
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_cycle_count(uint8_t timer_id)
{
rtc_timer_ll_counter_snapshot(&LP_TIMER);
uint32_t lo = rtc_timer_ll_get_counter_value_low(&LP_TIMER, timer_id);
uint32_t hi = rtc_timer_ll_get_counter_value_high(&LP_TIMER, timer_id);
return ((uint64_t)hi << 32) | lo;
}
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/esp32s2/include/hal/rtc_timer_ll.h
+17 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -15,8 +15,15 @@
extern "C" {
#endif
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_timer(uint64_t t)
/**
* @brief Set wakeup timer value
*
* @param timer_id Timer ID (ignored for V1 hardware, only one timer supported)
* @param ticks Timer value in RTC slow clock ticks
*/
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_time(uint8_t timer_id, uint64_t t)
{
(void)timer_id; // V1 hardware only supports one timer
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
@@ -24,8 +31,15 @@ FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_timer(uint64_t t)
SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
}
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_rtc_time(void)
/**
* @brief Get current RTC timer cycle count
*
* @param timer_id Timer ID (ignored for V1 hardware, only one timer supported)
* @return Current RTC time in RTC slow clock ticks
*/
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_cycle_count(uint8_t timer_id)
{
(void)timer_id; // V1 hardware only supports one timer
SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
components/esp_hal_rtc_timer/esp32s3/include/hal/rtc_timer_ll.h
+17 -3
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,8 +16,15 @@
extern "C" {
#endif
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_timer(uint64_t t)
/**
* @brief Set wakeup timer value
*
* @param timer_id Timer ID (ignored for V1 hardware, only one timer supported)
* @param ticks Timer value in RTC slow clock ticks
*/
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_time(uint8_t timer_id, uint64_t t)
{
(void)timer_id; // V1 hardware only supports one timer
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
@@ -25,8 +32,15 @@ FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_timer(uint64_t t)
SET_PERI_REG_MASK(RTC_CNTL_SLP_TIMER1_REG, RTC_CNTL_MAIN_TIMER_ALARM_EN_M);
}
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_rtc_time(void)
/**
* @brief Get current RTC timer cycle count
*
* @param timer_id Timer ID (ignored for V1 hardware, only one timer supported)
* @return Current RTC time in RTC slow clock ticks
*/
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_cycle_count(uint8_t timer_id)
{
(void)timer_id; // V1 hardware only supports one timer
SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
components/esp_hal_rtc_timer/esp32s31/include/hal/rtc_timer_ll.h
+28
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@@ -0,0 +1,28 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-P4 RTC_Timer register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/lp_timer_struct.h"
#include "soc/lp_timer_reg.h"
#include "soc/lp_system_reg.h"
#include "hal/misc.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
// TODO: ["ESP32S31"] IDF-14642
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/include/hal/lp_timer_hal.h
-51
View File
@@ -1,51 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include "soc/soc_caps.h"
#include "soc/soc.h"
#if SOC_LP_TIMER_SUPPORTED
#include "hal/lp_timer_types.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_LP_TIMER_SUPPORTED
/*
* @brief set alarm target value
*
* @param timer_id timer num of lp_timer, 0 or 1 for esp32c6 and esp32h2
*
* @param value when counter reaches alarm value, alarm event will be triggered
*/
void lp_timer_hal_set_alarm_target(uint8_t timer_id, uint64_t value);
/**
* @brief get current counter value
*/
uint64_t lp_timer_hal_get_cycle_count(void);
/**
* @brief clear alarm interrupt status
*/
void lp_timer_hal_clear_alarm_intr_status(void);
/**
* @brief clear overflow interrupt status
*/
void lp_timer_hal_clear_overflow_intr_status(void);
#endif
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/include/hal/lp_timer_types.h
-34
View File
@@ -1,34 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include "soc/soc_caps.h"
/**
* @brief The structure of the counter value in lower power timer
*/
#if SOC_LP_TIMER_SUPPORTED
typedef struct {
union {
struct {
uint32_t lo: SOC_LP_TIMER_BIT_WIDTH_LO; /*!< Low part of counter value */
uint32_t hi: SOC_LP_TIMER_BIT_WIDTH_HI; /*!< High part of counter value */
uint32_t reserved: 16;
};
uint64_t val; /*!< counter value */
};
} lp_timer_counter_value_t;
#endif
#ifdef __cplusplus
}
#endif
components/esp_hal_rtc_timer/include/hal/rtc_timer_hal.h
+7 -23
View File
@@ -8,44 +8,28 @@
#include <stdint.h>
#include "soc/soc_caps.h"
#if SOC_IS(ESP32) || SOC_IS(ESP32C2) || SOC_IS(ESP32C3) || SOC_IS(ESP32S2) || SOC_IS(ESP32S3)
#include "hal/rtc_timer_ll.h"
#endif
#if SOC_LP_TIMER_SUPPORTED
#include "hal/lp_timer_hal.h"
#include "hal/lp_timer_types.h"
#endif
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_RTC_TIMER_SUPPORTED
/**
* @brief Set wakeup timer value (for legacy chips with RTC_CNTL)
* @brief Set wakeup timer value
*
* @param timer_id Timer ID
* @param ticks Timer value in RTC slow clock ticks
*/
#if SOC_IS(ESP32) || SOC_IS(ESP32C2) || SOC_IS(ESP32C3) || SOC_IS(ESP32S2) || SOC_IS(ESP32S3)
#define rtc_timer_hal_set_wakeup_timer(ticks) rtc_timer_ll_set_wakeup_timer(ticks)
#elif SOC_LP_TIMER_SUPPORTED
#define rtc_timer_hal_set_wakeup_timer(ticks) lp_timer_hal_set_alarm_target(0, ticks)
#else
#error "RTC timer not supported on this target"
#endif
#define rtc_timer_hal_set_wakeup_time(timer_id, ticks) rtc_timer_ll_set_wakeup_time(timer_id, ticks)
/**
* @brief Get current RTC time (for legacy chips with RTC_CNTL)
* @brief Get current RTC timer cycle count
*
* @param timer_id Timer ID
* @return Current RTC time in RTC slow clock ticks
*/
#if SOC_IS(ESP32) || SOC_IS(ESP32C2) || SOC_IS(ESP32C3) || SOC_IS(ESP32S2) || SOC_IS(ESP32S3)
#define rtc_timer_hal_get_rtc_time() rtc_timer_ll_get_rtc_time()
#elif SOC_LP_TIMER_SUPPORTED
#define rtc_timer_hal_get_rtc_time() lp_timer_hal_get_cycle_count()
#else
#error "RTC timer not supported on this target"
#define rtc_timer_hal_get_cycle_count(timer_id) rtc_timer_ll_get_cycle_count(timer_id)
#endif
#ifdef __cplusplus
components/esp_hal_rtc_timer/linker.lf
-5
View File
@@ -1,5 +0,0 @@
[mapping:esp_hal_rtc_timer]
archive: libesp_hal_rtc_timer.a
entries:
if SOC_LP_TIMER_SUPPORTED = y:
lp_timer_hal (noflash)
components/esp_hal_rtc_timer/lp_timer_hal.c
-49
View File
@@ -1,49 +0,0 @@
/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <stdlib.h>
#include <esp_types.h>
#include "esp_attr.h"
#include "soc/soc.h"
#include "hal/lp_timer_types.h"
#include "hal/lp_timer_ll.h"
static DRAM_ATTR struct {
lp_timer_dev_t *dev;
} lp_timer_context = { .dev = &LP_TIMER };
void IRAM_ATTR lp_timer_hal_set_alarm_target(uint8_t timer_id, uint64_t value)
{
lp_timer_ll_clear_alarm_intr_status(lp_timer_context.dev);
lp_timer_ll_set_alarm_target(lp_timer_context.dev, timer_id, value);
lp_timer_ll_set_target_enable(lp_timer_context.dev, timer_id, true);
}
uint64_t IRAM_ATTR lp_timer_hal_get_cycle_count(void)
{
/* Shifts current count to buffer 0, and the value in buffer 0 to buffer 1 */
lp_timer_ll_counter_snapshot(lp_timer_context.dev);
uint32_t lo = lp_timer_ll_get_counter_value_low(lp_timer_context.dev, 0);
uint32_t hi = lp_timer_ll_get_counter_value_high(lp_timer_context.dev, 0);
lp_timer_counter_value_t result = {
.lo = lo,
.hi = hi
};
return result.val;
}
void IRAM_ATTR lp_timer_hal_clear_alarm_intr_status(void)
{
lp_timer_ll_clear_alarm_intr_status(lp_timer_context.dev);
}
void IRAM_ATTR lp_timer_hal_clear_overflow_intr_status(void)
{
lp_timer_ll_clear_overflow_intr_status(lp_timer_context.dev);
}
components/esp_hw_support/CMakeLists.txt
+2 -2
View File
@@ -9,9 +9,9 @@ if(${target} STREQUAL "linux")
return()
endif()
set(requires esp_hal_dma esp_hal_gpio esp_hal_usb esp_hal_pmu esp_hal_rtc_timer)
set(requires esp_hal_dma esp_hal_gpio esp_hal_usb esp_hal_pmu)
# only esp_hw_support/adc_share_hw_ctrl.c requires efuse component
set(priv_requires efuse spi_flash bootloader_support esp_hal_wdt)
set(priv_requires efuse spi_flash bootloader_support esp_hal_wdt esp_hal_rtc_timer)
set(srcs "cpu.c" "port/${IDF_TARGET}/esp_cpu_intr.c" "esp_memory_utils.c" "port/${IDF_TARGET}/cpu_region_protect.c")
if(NOT non_os_build)
components/esp_hw_support/hw_random.c
+4 -11
View File
@@ -19,9 +19,7 @@
#include "esp_private/startup_internal.h"
#endif
#if SOC_LP_TIMER_SUPPORTED
#include "hal/lp_timer_hal.h"
#endif
#include "hal/rtc_timer_hal.h"
#if SOC_RNG_CLOCK_IS_INDEPENDENT
#include "hal/lp_clkrst_ll.h"
@@ -74,21 +72,16 @@ uint32_t IRAM_ATTR esp_random(void)
static uint32_t last_ccount = 0;
uint32_t ccount;
uint32_t result = 0;
#if SOC_LP_TIMER_SUPPORTED
for (size_t i = 0; i < sizeof(result); i++) {
do {
ccount = esp_cpu_get_cycle_count();
result ^= REG_READ(WDEV_RND_REG);
} while (ccount - last_ccount < cpu_to_apb_freq_ratio * APB_CYCLE_WAIT_NUM);
uint32_t current_rtc_timer_counter = (lp_timer_hal_get_cycle_count() & 0xFF);
#if SOC_RTC_TIMER_SUPPORTED
uint32_t current_rtc_timer_counter = (rtc_timer_hal_get_cycle_count(0) & 0xFF);
result ^= (current_rtc_timer_counter << (i * 8));
}
#else
do {
ccount = esp_cpu_get_cycle_count();
result ^= REG_READ(WDEV_RND_REG);
} while (ccount - last_ccount < cpu_to_apb_freq_ratio * APB_CYCLE_WAIT_NUM);
#endif
}
last_ccount = ccount;
return result ^ REG_READ(WDEV_RND_REG);
}
components/esp_hw_support/include/esp_private/esp_pmu.h
+1 -1
View File
@@ -74,7 +74,7 @@ typedef enum {
#define RTC_GPIO_TRIG_EN (PMU_GPIO_WAKEUP_EN)
#endif
#if SOC_LP_TIMER_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
#define RTC_TIMER_TRIG_EN PMU_LP_TIMER_WAKEUP_EN //!< Timer wakeup
#else
#define RTC_TIMER_TRIG_EN 0
components/esp_hw_support/port/esp32/rtc_time.c
+2 -2
View File
@@ -7,7 +7,7 @@
#include <stdint.h>
#include "esp_rom_sys.h"
#include "hal/clk_tree_ll.h"
#include "hal/rtc_cntl_ll.h"
#include "hal/rtc_timer_ll.h"
#include "hal/timg_ll.h"
#include "soc/rtc.h"
#include "hal/timer_periph.h"
@@ -159,7 +159,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return rtc_cntl_ll_get_rtc_time();
return rtc_timer_ll_get_cycle_count(0);
}
void rtc_clk_wait_for_slow_cycle(void)
components/esp_hw_support/port/esp32c2/rtc_time.c
+2 -2
View File
@@ -9,7 +9,7 @@
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "hal/clk_tree_ll.h"
#include "hal/rtc_cntl_ll.h"
#include "hal/rtc_timer_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
#include "esp_rom_sys.h"
@@ -170,7 +170,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return rtc_cntl_ll_get_rtc_time();
return rtc_timer_ll_get_cycle_count(0);
}
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
components/esp_hw_support/port/esp32c3/rtc_time.c
+2 -2
View File
@@ -9,7 +9,7 @@
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "hal/clk_tree_ll.h"
#include "hal/rtc_cntl_ll.h"
#include "hal/rtc_timer_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
#include "esp_rom_sys.h"
@@ -170,7 +170,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return rtc_cntl_ll_get_rtc_time();
return rtc_timer_ll_get_cycle_count(0);
}
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
components/esp_hw_support/port/esp32c5/rtc_time.c
+2 -2
View File
@@ -8,7 +8,7 @@
#include "esp32c5/rom/ets_sys.h"
#include "soc/rtc.h"
#include "soc/lp_timer_reg.h"
#include "hal/lp_timer_hal.h"
#include "hal/rtc_timer_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
@@ -188,7 +188,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return lp_timer_hal_get_cycle_count();
return rtc_timer_hal_get_cycle_count(0);
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
components/esp_hw_support/port/esp32c6/rtc_time.c
+2 -2
View File
@@ -8,7 +8,7 @@
#include "esp32c6/rom/ets_sys.h"
#include "soc/rtc.h"
#include "soc/pcr_reg.h"
#include "hal/lp_timer_hal.h"
#include "hal/rtc_timer_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
@@ -231,7 +231,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return lp_timer_hal_get_cycle_count();
return rtc_timer_hal_get_cycle_count(0);
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
components/esp_hw_support/port/esp32c61/rtc_time.c
+2 -2
View File
@@ -7,7 +7,7 @@
#include <stdint.h>
#include "esp32c61/rom/ets_sys.h"
#include "soc/rtc.h"
#include "hal/lp_timer_hal.h"
#include "hal/rtc_timer_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
@@ -187,7 +187,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return lp_timer_hal_get_cycle_count();
return rtc_timer_hal_get_cycle_count(0);
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
components/esp_hw_support/port/esp32h2/rtc_time.c
+2 -2
View File
@@ -7,7 +7,7 @@
#include <stdint.h>
#include "esp32h2/rom/ets_sys.h"
#include "soc/rtc.h"
#include "hal/lp_timer_hal.h"
#include "hal/rtc_timer_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
@@ -231,7 +231,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return lp_timer_hal_get_cycle_count();
return rtc_timer_hal_get_cycle_count(0);
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
components/esp_hw_support/port/esp32h21/rtc_time.c
+2 -2
View File
@@ -7,7 +7,7 @@
#include <stdint.h>
#include "esp32h21/rom/ets_sys.h"
#include "soc/rtc.h"
#include "hal/lp_timer_hal.h"
#include "hal/rtc_timer_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
@@ -205,7 +205,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return lp_timer_hal_get_cycle_count();
return rtc_timer_hal_get_cycle_count(0);
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
components/esp_hw_support/port/esp32h4/rtc_time.c
+2 -2
View File
@@ -7,7 +7,7 @@
#include <stdint.h>
#include "esp32h4/rom/ets_sys.h"
#include "soc/rtc.h"
#include "hal/lp_timer_hal.h"
#include "hal/rtc_timer_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
@@ -204,7 +204,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return lp_timer_hal_get_cycle_count();
return rtc_timer_hal_get_cycle_count(0);
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
components/esp_hw_support/port/esp32p4/rtc_time.c
+2 -2
View File
@@ -8,7 +8,7 @@
#include <assert.h>
#include "esp32p4/rom/ets_sys.h"
#include "soc/rtc.h"
#include "hal/lp_timer_hal.h"
#include "hal/rtc_timer_hal.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "soc/hp_sys_clkrst_reg.h"
@@ -213,7 +213,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return lp_timer_hal_get_cycle_count();
return rtc_timer_hal_get_cycle_count(0);
}
uint32_t rtc_clk_freq_cal(uint32_t cal_val)
components/esp_hw_support/port/esp32s2/rtc_time.c
+2 -2
View File
@@ -9,7 +9,7 @@
#include "soc/rtc.h"
#include "soc/rtc_cntl_reg.h"
#include "hal/clk_tree_ll.h"
#include "hal/rtc_cntl_ll.h"
#include "hal/rtc_timer_ll.h"
#include "hal/timg_ll.h"
#include "soc/timer_group_reg.h"
#include "esp_private/periph_ctrl.h"
@@ -234,7 +234,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return rtc_cntl_ll_get_rtc_time();
return rtc_timer_ll_get_cycle_count(0);
}
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
components/esp_hw_support/port/esp32s3/rtc_time.c
+2 -2
View File
@@ -10,7 +10,7 @@
#include "soc/rtc_cntl_reg.h"
#include "hal/clk_tree_ll.h"
#include "hal/timg_ll.h"
#include "hal/rtc_cntl_ll.h"
#include "hal/rtc_timer_ll.h"
#include "soc/timer_group_reg.h"
#include "esp_private/periph_ctrl.h"
@@ -169,7 +169,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
uint64_t rtc_time_get(void)
{
return rtc_cntl_ll_get_rtc_time();
return rtc_timer_ll_get_cycle_count(0);
}
void rtc_clk_wait_for_slow_cycle(void) //This function may not by useful any more
components/esp_hw_support/port/esp32s31/rtc_time.c
+1 -1
View File
@@ -8,7 +8,7 @@
#include <assert.h>
#include "esp32s31/rom/ets_sys.h"
#include "soc/rtc.h"
#include "hal/lp_timer_hal.h"
#include "hal/rtc_timer_hal.h"
#include "hal/clk_tree_ll.h"
// #include "hal/timer_ll.h"
#include "soc/hp_sys_clkrst_reg.h"
components/esp_hw_support/sleep_modes.c
+2 -9
View File
@@ -140,9 +140,7 @@
#include "soc/pmu_icg_mapping.h"
#endif
#if SOC_LP_TIMER_SUPPORTED
#include "hal/lp_timer_hal.h"
#endif
#include "hal/rtc_timer_hal.h"
#if SOC_VBAT_SUPPORTED
#include "esp_vbat.h"
@@ -1842,7 +1840,6 @@ static SLEEP_FN_ATTR esp_err_t timer_wakeup_prepare(int64_t sleep_duration)
int64_t ticks = rtc_time_us_to_slowclk(sleep_duration, s_config.rtc_clk_cal_period);
int64_t target_wakeup_tick = s_config.rtc_ticks_at_sleep_start + ticks;
#if SOC_LP_TIMER_SUPPORTED
#if CONFIG_PM_POWER_DOWN_PERIPHERAL_IN_LIGHT_SLEEP
int64_t backup_cost_ticks = rtc_time_us_to_slowclk(((pmu_sleep_machine_constant_t *)PMU_instance()->mc)->hp.regdma_a2s_work_time_us, s_config.rtc_clk_cal_period);
// Last timer wake-up validity check
@@ -1852,11 +1849,7 @@ static SLEEP_FN_ATTR esp_err_t timer_wakeup_prepare(int64_t sleep_duration)
return ESP_ERR_SLEEP_REJECT;
}
#endif
lp_timer_hal_set_alarm_target(0, target_wakeup_tick);
#else
rtc_hal_set_wakeup_timer(target_wakeup_tick);
#endif
rtc_timer_hal_set_wakeup_time(0, target_wakeup_tick);
return ESP_OK;
}
components/esp_hw_support/sleep_wake_stub.c
+5 -26
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -18,17 +18,8 @@
#include "soc/soc_caps.h"
#include "hal/uart_ll.h"
#include "hal/clk_tree_ll.h"
#if SOC_LP_TIMER_SUPPORTED
#include "hal/lp_timer_ll.h"
#include "hal/lp_timer_hal.h"
#else
#include "hal/rtc_cntl_ll.h"
#endif
#if SOC_PMU_SUPPORTED
#include "hal/pmu_ll.h"
#endif
#include "hal/rtc_hal.h"
#include "hal/rtc_timer_ll.h"
#include "sdkconfig.h"
#include "esp_rom_serial_output.h"
@@ -93,20 +84,8 @@ void RTC_IRAM_ATTR esp_wake_stub_uart_tx_wait_idle(uint8_t uart_no)
void RTC_IRAM_ATTR esp_wake_stub_set_wakeup_time(uint64_t time_in_us)
{
uint64_t rtc_count_delta = time_in_us * (1 << RTC_CLK_CAL_FRACT) / clk_ll_rtc_slow_load_cal();
#if SOC_LP_TIMER_SUPPORTED
lp_timer_ll_counter_snapshot(&LP_TIMER);
uint32_t lo = lp_timer_ll_get_counter_value_low(&LP_TIMER, 0);
uint32_t hi = lp_timer_ll_get_counter_value_high(&LP_TIMER, 0);
uint64_t rtc_curr_count = (uint64_t)hi << 32 | lo;
lp_timer_ll_clear_alarm_intr_status(&LP_TIMER);
lp_timer_ll_set_alarm_target(&LP_TIMER, 0, rtc_curr_count + rtc_count_delta);
lp_timer_ll_set_target_enable(&LP_TIMER, 0, true);
#else
uint64_t rtc_curr_count = rtc_cntl_ll_get_rtc_time();
rtc_cntl_ll_set_wakeup_timer(rtc_curr_count + rtc_count_delta);
#endif
uint64_t rtc_curr_count = rtc_timer_ll_get_cycle_count(0);
rtc_timer_ll_set_wakeup_time(0, rtc_curr_count + rtc_count_delta);
}
uint32_t RTC_IRAM_ATTR esp_wake_stub_get_wakeup_cause(void)
components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c
+2 -2
View File
@@ -243,7 +243,7 @@ static void start_freq(soc_rtc_slow_clk_src_t required_src, uint32_t start_delay
printf("PASS. Time measurement...");
}
uint32_t fail_measure = 0;
#if SOC_LP_TIMER_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
uint64_t clk_rtc_time;
for (int j = 0; j < 3; ++j) {
clk_rtc_time = esp_clk_rtc_time();
@@ -334,7 +334,7 @@ TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[rtc_
#endif // !defined(CONFIG_IDF_CI_BUILD) || !CONFIG_SPIRAM_BANKSWITCH_ENABLE
#endif // SOC_CLK_XTAL32K_SUPPORTED
#if SOC_LP_TIMER_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
TEST_CASE("Test rtc clk calibration compensation", "[rtc_clk]")
{
int64_t t1 = esp_rtc_get_time_us();
components/soc/esp32/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -83,6 +83,10 @@ config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V1_SUPPORTED
bool
default y
config SOC_I2S_SUPPORTED
bool
default y
components/soc/esp32/include/soc/soc_caps.h
+2
View File
@@ -86,6 +86,7 @@
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1
#define SOC_RTC_TIMER_V1_SUPPORTED 1
#define SOC_I2S_SUPPORTED 1
#define SOC_I2S_I80_LCD_SUPPORTED 1
#define SOC_LCD_I80_SUPPORTED 1
@@ -270,6 +271,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V1_SUPPORTED
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_VERSION (1U) /*!<Hardware version of touch sensor */
components/soc/esp32c2/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -99,6 +99,10 @@ config SOC_BOD_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V1_SUPPORTED
bool
default y
config SOC_CLK_TREE_SUPPORTED
bool
default y
components/soc/esp32c2/include/soc/soc_caps.h
+2
View File
@@ -47,6 +47,7 @@
#define SOC_SECURE_BOOT_SUPPORTED 1
#define SOC_SYSTIMER_SUPPORTED 1
#define SOC_BOD_SUPPORTED 1
#define SOC_RTC_TIMER_V1_SUPPORTED 1
#define SOC_CLK_TREE_SUPPORTED 1
#define SOC_ASSIST_DEBUG_SUPPORTED 1
#define SOC_WDT_SUPPORTED 1
@@ -248,6 +249,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V1_SUPPORTED
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
#define SOC_MWDT_SUPPORT_XTAL (1)
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -87,6 +87,10 @@ config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V1_SUPPORTED
bool
default y
config SOC_I2S_SUPPORTED
bool
default y
components/soc/esp32c3/include/soc/soc_caps.h
+2
View File
@@ -44,6 +44,7 @@
#define SOC_EFUSE_SUPPORTED 1
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1
#define SOC_RTC_TIMER_V1_SUPPORTED 1
#define SOC_I2S_SUPPORTED 1
#define SOC_RMT_SUPPORTED 1
#define SOC_SDM_SUPPORTED 1
@@ -323,6 +324,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V1_SUPPORTED
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
#define SOC_MWDT_SUPPORT_XTAL (1)
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+1 -1
View File
@@ -199,7 +199,7 @@ config SOC_PAU_SUPPORTED
bool
default y
config SOC_LP_TIMER_SUPPORTED
config SOC_RTC_TIMER_V2_SUPPORTED
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+2 -1
View File
@@ -72,7 +72,7 @@
#define SOC_APM_SUPPORTED 1 /*!< Support for APM peripheral */
#define SOC_PMU_SUPPORTED 1
#define SOC_PAU_SUPPORTED 1
#define SOC_LP_TIMER_SUPPORTED 1
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
#define SOC_LP_PERIPHERALS_SUPPORTED 1
#define SOC_LP_I2C_SUPPORTED 1
@@ -452,6 +452,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_ETM (1)
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
+1 -1
View File
@@ -195,7 +195,7 @@ config SOC_PAU_SUPPORTED
bool
default y
config SOC_LP_TIMER_SUPPORTED
config SOC_RTC_TIMER_V2_SUPPORTED
bool
default y
components/soc/esp32c6/include/soc/soc_caps.h
+2 -1
View File
@@ -71,7 +71,7 @@
#define SOC_PMU_SUPPORTED 1
#define SOC_PMU_PVT_SUPPORTED 1
#define SOC_PAU_SUPPORTED 1
#define SOC_LP_TIMER_SUPPORTED 1
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
#define SOC_LP_PERIPHERALS_SUPPORTED 1
#define SOC_LP_I2C_SUPPORTED 1
@@ -393,6 +393,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_ETM (1)
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
+1 -1
View File
@@ -119,7 +119,7 @@ config SOC_PMU_SUPPORTED
bool
default y
config SOC_LP_TIMER_SUPPORTED
config SOC_RTC_TIMER_V2_SUPPORTED
bool
default y
components/soc/esp32c61/include/soc/soc_caps.h
+2 -1
View File
@@ -54,7 +54,7 @@
#define SOC_BOD_SUPPORTED 1
#define SOC_APM_SUPPORTED 1 /*!< Support for APM peripheral */
#define SOC_PMU_SUPPORTED 1
#define SOC_LP_TIMER_SUPPORTED 1
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
#define SOC_CLK_TREE_SUPPORTED 1
#define SOC_ASSIST_DEBUG_SUPPORTED 1
@@ -352,6 +352,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
+1 -1
View File
@@ -199,7 +199,7 @@ config SOC_PMU_SUPPORTED
bool
default y
config SOC_LP_TIMER_SUPPORTED
config SOC_RTC_TIMER_V2_SUPPORTED
bool
default y
components/soc/esp32h2/include/soc/soc_caps.h
+2 -1
View File
@@ -88,7 +88,7 @@
#define SOC_VBAT_SUPPORTED 1
#define SOC_APM_SUPPORTED 1 /*!< Support for APM peripheral */
#define SOC_PMU_SUPPORTED 1
#define SOC_LP_TIMER_SUPPORTED 1
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
#define SOC_PAU_SUPPORTED 1
#define SOC_CLK_TREE_SUPPORTED 1
@@ -407,6 +407,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_ETM (1)
components/soc/esp32h21/include/soc/Kconfig.soc_caps.in
+1 -1
View File
@@ -111,7 +111,7 @@ config SOC_PMU_SUPPORTED
bool
default y
config SOC_LP_TIMER_SUPPORTED
config SOC_RTC_TIMER_V2_SUPPORTED
bool
default y
components/soc/esp32h21/include/soc/soc_caps.h
+2 -1
View File
@@ -61,7 +61,7 @@
// #define SOC_BOD_SUPPORTED 1 //TODO: [ESP32H21] IDF-11530
// #define SOC_APM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11494
#define SOC_PMU_SUPPORTED 1
#define SOC_LP_TIMER_SUPPORTED 1
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
// #define SOC_LP_PERIPHERALS_SUPPORTED 1
#define SOC_CLK_TREE_SUPPORTED 1
@@ -381,6 +381,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_ETM (1)
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+1 -1
View File
@@ -131,7 +131,7 @@ config SOC_PAU_SUPPORTED
bool
default y
config SOC_LP_TIMER_SUPPORTED
config SOC_RTC_TIMER_V2_SUPPORTED
bool
default y
components/soc/esp32h4/include/soc/soc_caps.h
+2 -1
View File
@@ -77,7 +77,7 @@
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12256
#define SOC_PMU_SUPPORTED 1 // TODO: [ESP32H4] IDF-12286
#define SOC_PAU_SUPPORTED 1
#define SOC_LP_TIMER_SUPPORTED 1
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
#define SOC_TOUCH_SENSOR_SUPPORTED 1
// #define SOC_LP_PERIPHERALS_SUPPORTED 1
@@ -398,6 +398,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_ETM (1)
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+1 -1
View File
@@ -259,7 +259,7 @@ config SOC_PAU_SUPPORTED
bool
default y
config SOC_LP_TIMER_SUPPORTED
config SOC_RTC_TIMER_V2_SUPPORTED
bool
default y
components/soc/esp32p4/include/soc/soc_caps.h
+2 -1
View File
@@ -87,7 +87,7 @@
#define SOC_PMU_PVT_SUPPORTED 1
#define SOC_DCDC_SUPPORTED 1
#define SOC_PAU_SUPPORTED 1 //TODO: IDF-7531
#define SOC_LP_TIMER_SUPPORTED 1
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_ULP_LP_UART_SUPPORTED 1
#define SOC_LP_GPIO_MATRIX_SUPPORTED 1
#define SOC_LP_PERIPHERALS_SUPPORTED 1
@@ -569,6 +569,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_SUPPORT_ETM 1
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -99,6 +99,10 @@ config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V1_SUPPORTED
bool
default y
config SOC_PSRAM_DMA_CAPABLE
bool
default y
components/soc/esp32s2/include/soc/soc_caps.h
+2
View File
@@ -67,6 +67,7 @@
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1
#define SOC_RTC_TIMER_V1_SUPPORTED 1
#define SOC_PSRAM_DMA_CAPABLE 1
#define SOC_XT_WDT_SUPPORTED 1
#define SOC_I2S_SUPPORTED 1
@@ -278,6 +279,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V1_SUPPORTED
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_VERSION (2) /*!< Hardware version of touch sensor */
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
+4
View File
@@ -135,6 +135,10 @@ config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_RTC_TIMER_V1_SUPPORTED
bool
default y
config SOC_PSRAM_DMA_CAPABLE
bool
default y
components/soc/esp32s3/include/soc/soc_caps.h
+2
View File
@@ -61,6 +61,7 @@
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1
#define SOC_RTC_TIMER_V1_SUPPORTED 1
#define SOC_PSRAM_DMA_CAPABLE 1
#define SOC_XT_WDT_SUPPORTED 1
#define SOC_I2S_SUPPORTED 1
@@ -317,6 +318,7 @@
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V1_SUPPORTED
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
#define SOC_TOUCH_SENSOR_VERSION (2) /*!< Hardware version of touch sensor */
components/soc/esp32s31/include/soc/soc_caps.h
+1 -1
View File
@@ -73,7 +73,7 @@
// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32S31] IDF-14658
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14620
// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32S31] IDF-14642
// #define SOC_LP_TIMER_SUPPORTED 1 // TODO: [ESP32S31] IDF-14638
// #define SOC_RTC_TIMER_V2_SUPPORTED 1 // TODO: [ESP32S31] IDF-14638
// #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32S31] IDF-14634
// #define SOC_LP_GPIO_MATRIX_SUPPORTED 1 // TODO: [ESP32S31] IDF-14785
// #define SOC_LP_PERIPHERALS_SUPPORTED 1 // TODO: [ESP32S31] IDF-14785
components/soc/include/soc/rtc_cntl_periph.h
+1 -1
View File
@@ -38,7 +38,7 @@
#include "soc/lp_i2c_reg.h"
#include "soc/lp_i2c_struct.h"
#endif
#if SOC_LP_TIMER_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
#include "soc/lp_timer_reg.h"
#include "soc/lp_timer_struct.h"
#endif
components/ulp/CMakeLists.txt
+1 -1
View File
@@ -65,7 +65,7 @@ if(CONFIG_ULP_COPROC_TYPE_LP_CORE)
list(APPEND srcs "lp_core/lp_core_i2c.c")
endif()
if(CONFIG_SOC_LP_TIMER_SUPPORTED)
if(CONFIG_SOC_RTC_TIMER_V2_SUPPORTED)
list(APPEND srcs "lp_core/shared/ulp_lp_core_lp_timer_shared.c")
endif()
components/ulp/lp_core/lp_core.c
+1 -1
View File
@@ -133,7 +133,7 @@ esp_err_t ulp_lp_core_run(ulp_lp_core_cfg_t* cfg)
}
#endif
#if SOC_LP_TIMER_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
ulp_lp_core_memory_shared_cfg_t* shared_mem = ulp_lp_core_memory_shared_cfg_get();
if (cfg->wakeup_source & ULP_LP_CORE_WAKEUP_SOURCE_LP_TIMER) {
components/ulp/lp_core/lp_core/include/ulp_lp_core_utils.h
+1 -1
View File
@@ -141,7 +141,7 @@ static inline void ulp_lp_core_sw_intr_clear(void)
return ulp_lp_core_sw_intr_from_hp_clear();
}
#if SOC_LP_TIMER_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
/**
* @brief Enable the LP Timer interrupt
*
components/ulp/lp_core/lp_core/lp_core_startup.c
+2 -2
View File
@@ -28,13 +28,13 @@ void lp_core_startup()
ulp_lp_core_memory_shared_cfg_t* shared_mem = ulp_lp_core_memory_shared_cfg_get();
#if SOC_LP_TIMER_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
uint64_t sleep_duration_ticks = shared_mem->sleep_duration_ticks;
if (sleep_duration_ticks) {
ulp_lp_core_lp_timer_set_wakeup_ticks(sleep_duration_ticks);
}
#endif //SOC_LP_TIMER_SUPPORTED
#endif // SOC_RTC_TIMER_V2_SUPPORTED
ulp_lp_core_halt();
}
components/ulp/lp_core/lp_core/lp_core_utils.c
+9 -9
View File
@@ -19,8 +19,8 @@
#include "hal/lp_i2s_ll.h"
#endif
#if SOC_LP_TIMER_SUPPORTED
#include "hal/lp_timer_ll.h"
#if SOC_RTC_TIMER_V2_SUPPORTED
#include "hal/rtc_timer_ll.h"
#endif
#include "esp_cpu.h"
@@ -82,13 +82,13 @@ void ulp_lp_core_update_wakeup_cause(void)
}
#endif /* SOC_ETM_SUPPORTED */
#if SOC_LP_TIMER_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER) \
&& (lp_timer_ll_get_lp_intr_raw(&LP_TIMER) & LP_TIMER_MAIN_TIMER_LP_INT_RAW)) {
&& (rtc_timer_ll_get_intr_raw(&LP_TIMER, 1) & LP_TIMER_MAIN_TIMER_LP_INT_RAW)) {
lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER;
lp_timer_ll_clear_lp_intsts_mask(&LP_TIMER, LP_TIMER_MAIN_TIMER_LP_INT_CLR);
rtc_timer_ll_clear_alarm_intr_status(&LP_TIMER, 1);
}
#endif /* SOC_LP_TIMER_SUPPORTED */
#endif /* SOC_RTC_TIMER_V2_SUPPORTED */
}
@@ -196,15 +196,15 @@ void ulp_lp_core_sw_intr_from_hp_clear(void)
pmu_ll_lp_clear_sw_intr_status(&PMU);
}
#if SOC_LP_TIMER_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
void ulp_lp_core_lp_timer_intr_enable(bool enable)
{
lp_timer_ll_lp_alarm_intr_enable(&LP_TIMER, enable);
rtc_timer_ll_alarm_intr_enable(&LP_TIMER, 1, enable);
}
void ulp_lp_core_lp_timer_intr_clear(void)
{
lp_timer_ll_clear_lp_alarm_intr_status(&LP_TIMER);
rtc_timer_ll_clear_alarm_intr_status(&LP_TIMER, 1);
}
#endif
components/ulp/lp_core/shared/ulp_lp_core_lp_timer_shared.c
+9 -30
View File
@@ -1,42 +1,21 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "ulp_lp_core_lp_timer_shared.h"
#include "soc/soc_caps.h"
#if SOC_LP_TIMER_SUPPORTED
#include "hal/lp_timer_ll.h"
#if SOC_RTC_TIMER_V2_SUPPORTED
#include "hal/rtc_timer_ll.h"
#include "hal/clk_tree_ll.h"
#include "soc/rtc.h"
#define TIMER_ID 1
static struct {
lp_timer_dev_t *dev;
} lp_timer_context = { .dev = &LP_TIMER };
static void lp_timer_hal_set_alarm_target(uint64_t value)
{
lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_context.dev);
lp_timer_ll_set_alarm_target(lp_timer_context.dev, TIMER_ID, value);
lp_timer_ll_set_target_enable(lp_timer_context.dev, TIMER_ID, true);
}
uint64_t ulp_lp_core_lp_timer_get_cycle_count(void)
{
lp_timer_ll_counter_snapshot(lp_timer_context.dev);
uint32_t lo = lp_timer_ll_get_counter_value_low(lp_timer_context.dev, 0);
uint32_t hi = lp_timer_ll_get_counter_value_high(lp_timer_context.dev, 0);
lp_timer_counter_value_t result = {
.lo = lo,
.hi = hi
};
return result.val;
return rtc_timer_ll_get_cycle_count(0);
}
void ulp_lp_core_lp_timer_set_wakeup_time(uint64_t sleep_duration_us)
@@ -44,7 +23,7 @@ void ulp_lp_core_lp_timer_set_wakeup_time(uint64_t sleep_duration_us)
uint64_t cycle_cnt = ulp_lp_core_lp_timer_get_cycle_count();
uint64_t alarm_target = cycle_cnt + ulp_lp_core_lp_timer_calculate_sleep_ticks(sleep_duration_us);
lp_timer_hal_set_alarm_target(alarm_target);
rtc_timer_ll_set_wakeup_time(TIMER_ID, alarm_target);
}
void ulp_lp_core_lp_timer_set_wakeup_ticks(uint64_t sleep_duration_ticks)
@@ -52,13 +31,13 @@ void ulp_lp_core_lp_timer_set_wakeup_ticks(uint64_t sleep_duration_ticks)
uint64_t cycle_cnt = ulp_lp_core_lp_timer_get_cycle_count();
uint64_t alarm_target = cycle_cnt + sleep_duration_ticks;
lp_timer_hal_set_alarm_target(alarm_target);
rtc_timer_ll_set_wakeup_time(TIMER_ID, alarm_target);
}
void ulp_lp_core_lp_timer_disable(void)
{
lp_timer_ll_set_target_enable(lp_timer_context.dev, TIMER_ID, false);
lp_timer_ll_clear_lp_alarm_intr_status(lp_timer_context.dev);
rtc_timer_ll_set_target_enable(&LP_TIMER, TIMER_ID, false);
rtc_timer_ll_clear_alarm_intr_status(&LP_TIMER, TIMER_ID);
}
uint64_t ulp_lp_core_lp_timer_calculate_sleep_ticks(uint64_t sleep_duration_us)
@@ -66,4 +45,4 @@ uint64_t ulp_lp_core_lp_timer_calculate_sleep_ticks(uint64_t sleep_duration_us)
return (sleep_duration_us * (1 << RTC_CLK_CAL_FRACT) / clk_ll_rtc_slow_load_cal());
}
#endif //SOC_LP_TIMER_SUPPORTED
#endif // SOC_RTC_TIMER_V2_SUPPORTED
components/ulp/test_apps/lp_core/lp_core_basic_tests/main/CMakeLists.txt
+2 -2
View File
@@ -30,7 +30,7 @@ list(APPEND app_sources "test_lp_core_prefix.c")
set(lp_core_sources "lp_core/test_main.c")
set(lp_core_sources_counter "lp_core/test_main_counter.c")
if(CONFIG_SOC_LP_TIMER_SUPPORTED)
if(CONFIG_SOC_RTC_TIMER_V2_SUPPORTED)
set(lp_core_sources_set_timer_wakeup "lp_core/test_main_set_timer_wakeup.c")
endif()
@@ -71,7 +71,7 @@ ulp_embed_binary(lp_core_test_app "${lp_core_sources}" "${lp_core_exp_dep_srcs}"
ulp_embed_binary(lp_core_test_app_counter "${lp_core_sources_counter}" "${lp_core_exp_dep_srcs}")
ulp_embed_binary(lp_core_test_app_isr "lp_core/test_main_isr.c" "${lp_core_exp_dep_srcs}")
if(CONFIG_SOC_LP_TIMER_SUPPORTED)
if(CONFIG_SOC_RTC_TIMER_V2_SUPPORTED)
ulp_embed_binary(lp_core_test_app_set_timer_wakeup "${lp_core_sources_set_timer_wakeup}" "${lp_core_exp_dep_srcs}")
endif()
components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core.c
+3 -3
View File
@@ -13,7 +13,7 @@
#include "lp_core_test_app_counter.h"
#include "lp_core_test_app_isr.h"
#if SOC_LP_TIMER_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
#include "lp_core_test_app_set_timer_wakeup.h"
#endif
@@ -295,7 +295,7 @@ TEST_CASE("LP core can be stopped and and started again from main CPU", "[ulp]")
}
}
#if SOC_LP_TIMER_SUPPORTED
#if SOC_RTC_TIMER_V2_SUPPORTED
TEST_CASE("LP core can schedule next wake-up time by itself", "[ulp]")
{
int64_t start, test_duration;
@@ -342,7 +342,7 @@ TEST_CASE("LP core gpio tests", "[ulp]")
}
#endif //SOC_RTCIO_PIN_COUNT > 0
#endif //SOC_LP_TIMER_SUPPORTED
#endif // SOC_RTC_TIMER_V2_SUPPORTED
#define ISR_TEST_ITERATIONS 100
#define IO_TEST_PIN 0
examples/openthread/ot_sleepy_device/deep_sleep/sdkconfig.defaults
-2
View File
@@ -41,8 +41,6 @@ CONFIG_IEEE802154_ENABLED=y
#
# deep sleep
#
CONFIG_ULP_COPROC_ENABLED=y
CONFIG_ULP_COPROC_RESERVE_MEM=512
CONFIG_LIBC_TIME_SYSCALL_USE_RTC_HRT=y
CONFIG_RTC_CLK_SRC_INT_RC=y
CONFIG_BOOTLOADER_SKIP_VALIDATE_IN_DEEP_SLEEP=y
examples/system/.build-test-rules.yml
+1 -1
View File
@@ -373,7 +373,7 @@ examples/system/ulp/lp_core/lp_spi:
examples/system/ulp/lp_core/lp_timer_interrupt:
disable:
- if: (SOC_LP_CORE_SUPPORTED != 1) or (SOC_LP_TIMER_SUPPORTED != 1)
- if: (SOC_LP_CORE_SUPPORTED != 1) or (SOC_RTC_TIMER_V2_SUPPORTED != 1)
depends_components:
- ulp