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ci(esp_timer): re-enable ci tests for esp-timer on p4 eco5

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This commit is contained in:
Marius Vikhammer
2025-11-21 09:47:40 +08:00
committed by Sudeep Mohanty
parent 2c54fd0738
commit 4920666a03
2 changed files with 0 additions and 6 deletions
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components/esp_timer/test_apps/.build-test-rules.yml
-4
View File
@@ -4,7 +4,3 @@ components/esp_timer/test_apps:
disable:
- if: CONFIG_NAME == "dfs" and SOC_CLK_XTAL32K_SUPPORTED != 1
reason: The test requires the XTAL32K clock to measure the esp_timer timing accuracy
disable_test:
- if: IDF_TARGET == "esp32p4"
temporary: true
reason: p4 rev3 migration # TODO: IDF-14420
components/esp_timer/test_apps/pytest_esp_timer_ut.py
-2
View File
@@ -22,7 +22,6 @@ from pytest_embedded_idf.utils import idf_parametrize
],
indirect=['config', 'target'],
)
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14420')
def test_esp_timer(dut: Dut) -> None:
dut.run_all_single_board_cases(timeout=120)
@@ -37,7 +36,6 @@ def test_esp_timer(dut: Dut) -> None:
indirect=True,
)
@idf_parametrize('target', ['esp32'], indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32p4'], reason='p4 rev3 migration # TODO: IDF-14420')
def test_esp_timer_psram(dut: Dut) -> None:
dut.run_all_single_board_cases(timeout=120)