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fix(cache): fixed cache sys clk not on issue

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This commit is contained in:
armando
2026-03-26 17:19:25 +08:00
parent ebbd9cdb59
commit 4bea0ccb22
17 changed files with 130 additions and 39 deletions
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components/bootloader_support/src/esp32s31/bootloader_esp32s31.c
-8
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@@ -23,7 +23,6 @@
#include "soc/rtc_wdt_reg.h"
#include "hal/rwdt_ll.h"
#endif
#include "soc/hp_sys_clkrst_reg.h"
#include "soc/pmu_reg.h"
#include "hal/regi2c_ctrl_ll.h"
#include "hal/modem_lpcon_ll.h"
@@ -32,13 +31,6 @@ ESP_LOG_ATTR_TAG(TAG, "boot.esp32s31");
static inline void bootloader_hardware_init(void)
{
// IDF-15507: Work around ESP32-S31 cache/MSPI issues by keeping the cache path clocks ungated.
REG_SET_BIT(HP_SYS_CLKRST_CACHE_CTRL0_REG,
HP_SYS_CLKRST_REG_CPU_ACACHE_CPU_CLK_FORCE_ON |
HP_SYS_CLKRST_REG_ROM_ACACHE_MEM_CLK_FORCE_ON |
HP_SYS_CLKRST_REG_CPU_CACHE_CPU_CLK_FORCE_ON |
HP_SYS_CLKRST_REG_MSPI_CACHE_SYS_CLK_FORCE_ON);
/* Disable RF pll by default */
REG_SET_FIELD(PMU_RF_PWC_REG, PMU_XPD_RF_CIRCUIT, 0xFFFF);
components/esp_hw_support/mspi/mspi_timing_tuning/mspi_timing_tuning.c
+14 -2
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@@ -245,9 +245,9 @@ static void s_sweep_for_success_sample_points(uint8_t *reference_data, void *con
}
}
ESP_DRAM_LOGW(TAG, "test nums: %" PRIu32 ", test result: [id][good/bad][good_times]:", s_tuning_cfg_drv.sweep_test_nums);
ESP_DRAM_LOGD(TAG, "test nums: %" PRIu32 ", test result: [id][good/bad][good_times]:", s_tuning_cfg_drv.sweep_test_nums);
for (config_idx = 0; config_idx < timing_config->available_config_num; config_idx++) {
ESP_DRAM_LOGW(TAG, "[%"PRIu32"][%s][%" PRIu32 "] ", config_idx, out_array[config_idx] == s_tuning_cfg_drv.sweep_test_nums ? "good" : "bad", out_array[config_idx]);
ESP_DRAM_LOGD(TAG, "[%"PRIu32"][%s][%" PRIu32 "] ", config_idx, out_array[config_idx] == s_tuning_cfg_drv.sweep_test_nums ? "good" : "bad", out_array[config_idx]);
}
}
@@ -481,6 +481,18 @@ void mspi_timing_psram_tuning(void)
/*------------------------------------------------------------------------------
* APIs to make SPI0 (and SPI1) FLASH work for high/low freq
*----------------------------------------------------------------------------*/
void __attribute__((weak)) mspi_timing_flash_config_clear_tuning_regs(bool control_both_mspi)
{
(void)control_both_mspi;
//for compatibility, will be replaced by the actual implementation once flash timing tuning is ready
}
void __attribute__((weak)) mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi)
{
(void)control_both_mspi;
//for compatibility, will be replaced by the actual implementation once flash timing tuning is ready
}
uint32_t mspi_timing_get_psram_low_speed_freq_mhz(void)
{
return 20;
components/esp_hw_support/mspi/mspi_timing_tuning/tuning_scheme_impl/include/esp_private/mspi_timing_by_dqs.h
+1 -19
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -157,24 +157,6 @@ void mspi_timing_psram_config_set_tuning_regs(bool control_both_mspi);
*/
void mspi_timing_psram_config_clear_tuning_regs(bool control_both_mspi);
/**
* @brief Set Flash timing tuning settings
*
* This is used when the system is going to high speed mode / MSPI needs to be run in high speed
*
* @param[in] control_both_mspi Control MSPI1 as well
*/
void mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi);
/**
* @brief Clear Flash timing tuning settings
*
* This is used when the system is going into low speed mode / MSPI doesn't need to be run in high speed
*
* @param[in] control_both_mspi Control MSPI1 as well
*/
void mspi_timing_flash_config_clear_tuning_regs(bool control_both_mspi);
#endif //#if SOC_MEMSPI_TIMING_TUNING_BY_DQS
#ifdef __cplusplus
components/esp_hw_support/mspi/mspi_timing_tuning/tuning_scheme_impl/mspi_timing_by_dqs.c
-10
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@@ -240,13 +240,3 @@ void mspi_timing_psram_config_set_tuning_regs(bool control_both_mspi)
}
}
}
void mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi)
{
//for compatibility
}
void mspi_timing_flash_config_clear_tuning_regs(bool control_both_mspi)
{
//for compatibility
}
components/hal/cache_hal.c
+2
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@@ -81,6 +81,8 @@ void cache_hal_init(const cache_hal_config_t *config)
{
s_cache_hal_init_ctx();
cache_ll_clk_init();
if (CACHE_LL_LEVEL_EXT_MEM == 1) {
cache_ll_enable_cache(1, CACHE_TYPE_ALL, CACHE_LL_ID_ALL, ctx.l1.i_autoload_en, ctx.l1.d_autoload_en);
} else if (CACHE_LL_LEVEL_EXT_MEM == 2) {
components/hal/esp32c2/include/hal/cache_ll.h
+9
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@@ -53,6 +53,15 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
__attribute__((always_inline))
static inline void cache_ll_clk_init(void)
{
//for compatibility
}
/**
* @brief Check if Cache auto preload is enabled or not.
*
components/hal/esp32c3/include/hal/cache_ll.h
+9
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@@ -52,6 +52,15 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
__attribute__((always_inline))
static inline void cache_ll_clk_init(void)
{
//for compatibility
}
/**
* @brief Check if Cache auto preload is enabled or not.
*
components/hal/esp32c5/include/hal/cache_ll.h
+9
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@@ -43,6 +43,15 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
__attribute__((always_inline))
static inline void cache_ll_clk_init(void)
{
//for compatibility
}
/**
* @brief Check if Cache auto preload is enabled or not.
*
components/hal/esp32c6/include/hal/cache_ll.h
+10
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@@ -1,3 +1,4 @@
/*
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
@@ -42,6 +43,15 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
__attribute__((always_inline))
static inline void cache_ll_clk_init(void)
{
//for compatibility
}
/**
* @brief Check if Cache auto preload is enabled or not.
*
components/hal/esp32c61/include/hal/cache_ll.h
+9
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@@ -42,6 +42,15 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
__attribute__((always_inline))
static inline void cache_ll_clk_init(void)
{
//for compatibility
}
/**
* @brief Check if Cache auto preload is enabled or not.
*
components/hal/esp32h2/include/hal/cache_ll.h
+9
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@@ -42,6 +42,15 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
__attribute__((always_inline))
static inline void cache_ll_clk_init(void)
{
//for compatibility
}
/**
* @brief Check if Cache auto preload is enabled or not.
*
components/hal/esp32h21/include/hal/cache_ll.h
+9
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@@ -43,6 +43,15 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
__attribute__((always_inline))
static inline void cache_ll_clk_init(void)
{
//for compatibility
}
/**
* @brief Check if Cache auto preload is enabled or not.
*
components/hal/esp32h4/include/hal/cache_ll.h
+9
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@@ -43,6 +43,15 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
__attribute__((always_inline))
static inline void cache_ll_clk_init(void)
{
//for compatibility
}
/**
* @brief Check if L1 ICache autoload is enabled or not
*
components/hal/esp32p4/include/hal/cache_ll.h
+9
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@@ -63,6 +63,15 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
__attribute__((always_inline))
static inline void cache_ll_clk_init(void)
{
//for compatibility
}
/*------------------------------------------------------------------------------
* Autoload
*----------------------------------------------------------------------------*/
components/hal/esp32s2/include/hal/cache_ll.h
+9
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@@ -40,6 +40,15 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
__attribute__((always_inline))
static inline void cache_ll_clk_init(void)
{
//for compatibility
}
/**
* @brief Check if ICache auto preload is enabled or not
*
components/hal/esp32s3/include/hal/cache_ll.h
+9
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@@ -55,6 +55,15 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
__attribute__((always_inline))
static inline void cache_ll_clk_init(void)
{
//for compatibility
}
/**
* @brief Check if ICache auto preload is enabled or not
*
components/hal/esp32s31/include/hal/cache_ll.h
+13
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@@ -15,6 +15,7 @@
#include "hal/cache_types.h"
#include "hal/assert.h"
#include "esp32s31/rom/cache.h"
#include "soc/hp_sys_clkrst_struct.h"
#ifdef __cplusplus
extern "C" {
@@ -51,6 +52,18 @@ typedef enum {
CACHE_LL_PRELOAD_ARBITRARY = 2,
} cache_ll_preload_strategy_t;
/**
* @brief Initialize the cache clock
*/
__attribute__((always_inline))
static inline void cache_ll_clk_init(void)
{
HP_SYS_CLKRST.cache_ctrl0.reg_cpu_acache_cpu_clk_force_on = 1;
HP_SYS_CLKRST.cache_ctrl0.reg_rom_acache_mem_clk_force_on = 1;
HP_SYS_CLKRST.cache_ctrl0.reg_cpu_cache_cpu_clk_force_on = 1;
HP_SYS_CLKRST.cache_ctrl0.reg_mspi_cache_sys_clk_force_on = 1;
}
/*------------------------------------------------------------------------------
* Autoload
*----------------------------------------------------------------------------*/