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Fix output bit range in bitscrambler documentation

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Destination bit range incorrect in `Sub-instructions` example
This commit is contained in:
Xorlent
2026-04-15 20:16:22 -07:00
committed by C.S.M
parent dfc5bbb58c
commit 51d059232b
20 changed files with 188 additions and 61 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s31.c
+3 -1
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@@ -45,7 +45,8 @@ void IRAM_ATTR bootloader_flash_cs_timing_config(void)
void IRAM_ATTR bootloader_init_mspi_clock(void)
{
// IDF-14777
_mspi_timing_ll_set_flash_clk_src(0, FLASH_CLK_SRC_DEFAULT);
_mspi_timing_ll_set_flash_core_clock(0, 80);
}
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
@@ -224,6 +225,7 @@ static void bootloader_spi_flash_resume(void)
esp_err_t bootloader_init_spi_flash(void)
{
bootloader_init_mspi_clock();
bootloader_init_flash_configure();
#if CONFIG_BOOTLOADER_FLASH_DC_AWARE
components/esp_hal_clock/esp32s31/include/hal/clk_tree_ll.h
-1
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@@ -30,7 +30,6 @@
#define CLK_LL_PLL_80M_FREQ_MHZ (80)
#define CLK_LL_PLL_160M_FREQ_MHZ (160)
#define CLK_LL_PLL_240M_FREQ_MHZ (240)
#define CLK_LL_PLL_320M_FREQ_MHZ (320)
#define CLK_LL_PLL_480M_FREQ_MHZ (480)
components/esp_hal_mspi/esp32s31/include/hal/gpspi_flash_ll.h
+99 -28
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -15,6 +15,8 @@
#include <stdlib.h>
#include "soc/spi_reg.h"
#include "soc/spi_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "hal/assert.h"
#include "hal/spi_types.h"
#include "hal/spi_flash_types.h"
#include <sys/param.h> // For MIN/MAX
@@ -26,31 +28,41 @@
extern "C" {
#endif
// TODO: ["ESP32S31"] IDF-14778
#define gpspi_flash_ll_get_hw(host_id) (((host_id)==SPI2_HOST ? &GPSPI2 \
: ((host_id)==SPI3_HOST ? &GPSPI3 \
: ({abort();(spi_dev_t*)0;}))))
#define gpspi_flash_ll_hw_get_id(dev) ( ((dev) == (void*)&GPSPI2) ? SPI2_HOST : (\
((dev) == (void*)&GPSPI3) ? SPI3_HOST : (\
-1 \
((dev) == (void*)&GPSPI3) ? SPI3_HOST : (\
-1 \
)) )
typedef typeof(GPSPI2.clock.val) gpspi_flash_ll_clock_reg_t;
#define GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ 80
#define GPSPI_FLASH_LL_PERIPHERAL_FREQUENCY_MHZ (80)
#define GPSPI_FLASH_LL_SUPPORT_CLK_SRC_PRE_DIV (1)
#define GPSPI_FLASH_LL_PERIPH_CLK_DIV_MAX ((SPI_CLKCNT_N + 1) * (SPI_CLKDIV_PRE + 1)) //peripheral internal maxmum clock divider
/*------------------------------------------------------------------------------
* Control
*----------------------------------------------------------------------------*/
/**
* Reset peripheral registers before configuration and starting control.
*
* @param dev Beginning address of the peripheral registers.
*/
* Reset peripheral registers before configuration and starting control
*
* @param dev Beginning address of the peripheral registers.
*/
static inline void gpspi_flash_ll_reset(spi_dev_t *dev)
{
// TODO: [ESP32S31] IDF-14778
dev->user.val = 0;
dev->ctrl.val = 0;
dev->clk_gate.clk_en = 1;
dev->clk_gate.mst_clk_active = 1;
dev->clk_gate.mst_clk_sel = 1;
dev->dma_conf.val = 0;
dev->dma_conf.slv_tx_seg_trans_clr_en = 1;
dev->dma_conf.slv_rx_seg_trans_clr_en = 1;
dev->dma_conf.dma_slv_seg_trans_en = 0;
}
/**
@@ -71,10 +83,23 @@ static inline bool gpspi_flash_ll_cmd_is_done(const spi_dev_t *dev)
* @param dev Beginning address of the peripheral registers.
* @param buffer Buffer to hold the output data
* @param read_len Length to get out of the buffer
*/
*/
static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer, uint32_t read_len)
{
// TODO: ["ESP32S31"] IDF-14778
if (((intptr_t)buffer % 4 == 0) && (read_len % 4 == 0)) {
// If everything is word-aligned, do a faster memcpy
memcpy(buffer, (void *)dev->data_buf, read_len);
} else {
// Otherwise, slow(er) path copies word by word
int copy_len = read_len;
for (int i = 0; i < (read_len + 3) / 4; i++) {
int word_len = MIN(sizeof(uint32_t), copy_len);
uint32_t word = dev->data_buf[i].buf;
memcpy(buffer, &word, word_len);
buffer = (void *)((intptr_t)buffer + word_len);
copy_len -= word_len;
}
}
}
/**
@@ -85,7 +110,7 @@ static inline void gpspi_flash_ll_get_buffer_data(spi_dev_t *dev, void *buffer,
*/
static inline void gpspi_flash_ll_write_word(spi_dev_t *dev, uint32_t word)
{
// TODO: ["ESP32S31"] IDF-14778
dev->data_buf[0].buf = word;
}
/**
@@ -97,7 +122,16 @@ static inline void gpspi_flash_ll_write_word(spi_dev_t *dev, uint32_t word)
*/
static inline void gpspi_flash_ll_set_buffer_data(spi_dev_t *dev, const void *buffer, uint32_t length)
{
// TODO: ["ESP32S31"] IDF-14778
// Load data registers, word at a time
int num_words = (length + 3) / 4;
for (int i = 0; i < num_words; i++) {
uint32_t word = 0;
uint32_t word_len = MIN(length, sizeof(word));
memcpy(&word, buffer, word_len);
dev->data_buf[i].buf = word;
length -= word_len;
buffer = (void *)((intptr_t)buffer + word_len);
}
}
/**
@@ -165,11 +199,11 @@ static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
* Configs
*----------------------------------------------------------------------------*/
/**
* Select which pin to use for the flash
*
* @param dev Beginning address of the peripheral registers.
* @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins.
*/
* Select which pin to use for the flash
*
* @param dev Beginning address of the peripheral registers.
* @param pin Pin ID to use, 0-2. Set to other values to disable all the CS pins.
*/
static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
{
dev->misc.cs0_dis = (pin == 0) ? 0 : 1;
@@ -311,7 +345,9 @@ static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitle
*/
static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
// TODO: ["ESP32S31"] IDF-14778
// The blank region should be all ones
uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen);
dev->addr.val = (addr << (32 - bitlen)) | padding_ones;
}
/**
@@ -322,7 +358,7 @@ static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr,
*/
static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
{
// dev->addr = addr;
dev->addr.val = addr;
}
/**
@@ -335,7 +371,7 @@ static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
{
dev->user.usr_dummy = dummy_n ? 1 : 0;
if (dummy_n > 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1)
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
}
}
@@ -408,13 +444,42 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
*/
static inline void gpspi_flash_ll_set_clk_source(spi_dev_t *hw, spi_clock_source_t clk_source)
{
uint32_t clk_id = 0;
switch (clk_source) {
case SPI_CLK_SRC_BBPLL:
clk_id = 2;
break;
case SPI_CLK_SRC_RC_FAST:
clk_id = 1;
break;
case SPI_CLK_SRC_XTAL:
hw->clk_gate.mst_clk_sel = 0;
clk_id = 0;
break;
default:
hw->clk_gate.mst_clk_sel = 1;
break;
HAL_ASSERT(false);
}
if (hw == &GPSPI2) {
HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_clk_src_sel = clk_id;
} else if (hw == &GPSPI3) {
HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_clk_src_sel = clk_id;
}
}
/**
* Enable/disable SPI flash module clock
*
* @param host_id SPI host ID
* @param enable true to enable, false to disable
*/
static inline void gpspi_flash_ll_enable_clock(spi_dev_t *hw, bool enable)
{
if (hw == &GPSPI2) {
HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_hs_clk_en = enable;
HP_SYS_CLKRST.gpspi2_ctrl0.reg_gpspi2_mst_clk_en = enable;
} else if (hw == &GPSPI3) {
HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_hs_clk_en = enable;
HP_SYS_CLKRST.gpspi3_ctrl0.reg_gpspi3_mst_clk_en = enable;
}
}
@@ -424,9 +489,15 @@ static inline void gpspi_flash_ll_set_clk_source(spi_dev_t *hw, spi_clock_source
* @param hw Beginning address of the peripheral registers.
* @param enable true to enable, false to disable
*/
static inline void gpspi_flash_ll_enable_clock(spi_dev_t *hw, bool enable)
static inline void gpspi_flash_ll_clk_source_pre_div(spi_dev_t *hw, uint8_t hs_div, uint8_t mst_div)
{
hw->clk_gate.clk_en = enable;
if (hw == &GPSPI2) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.gpspi2_ctrl0, reg_gpspi2_hs_clk_div_num, hs_div - 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.gpspi2_ctrl0, reg_gpspi2_mst_clk_div_num, mst_div - 1);
} else if (hw == &GPSPI3) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.gpspi3_ctrl0, reg_gpspi3_hs_clk_div_num, hs_div - 1);
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.gpspi3_ctrl0, reg_gpspi3_mst_clk_div_num, mst_div - 1);
}
}
#ifdef __cplusplus
components/esp_hal_mspi/esp32s31/include/hal/mspi_ll.h
+21
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@@ -39,6 +39,7 @@
#include "soc/spi_mem_c_reg.h"
#include "soc/spi1_mem_c_reg.h"
#include "soc/clk_tree_defs.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@@ -47,6 +48,7 @@ extern "C" {
#define MSPI_LL_PERIPH_NUM 4
#define MSPI_TIMING_LL_MSPI_ID_0 0
#define MSPI_TIMING_LL_MSPI_ID_1 1
#define MSPI_TIMING_LL_FLASH_CORE_80M_CLK_DIV 6
// PSRAM frequency should be constrained by AXI frequency to avoid FIFO underflow.
#define MSPI_TIMING_LL_PSRAM_FREQ_AXI_CONSTRAINED 1
@@ -216,6 +218,25 @@ static inline void _mspi_timing_ll_set_flash_clk_src(uint32_t mspi_id, soc_perip
HP_SYS_CLKRST.flash_ctrl0.reg_flash_clk_src_sel = clk_val;
}
/**
* Set MSPI Flash core clock
*
* @param spi_num SPI0 / SPI1
* @param core_clk_mhz core clock mhz
*/
__attribute__((always_inline))
static inline void _mspi_timing_ll_set_flash_core_clock(int spi_num, uint32_t core_clk_mhz)
{
HAL_ASSERT(spi_num == MSPI_TIMING_LL_MSPI_ID_0);
if (core_clk_mhz == 80) {
HAL_FORCE_MODIFY_U32_REG_FIELD(HP_SYS_CLKRST.flash_ctrl0, reg_flash_core_clk_div_num, (MSPI_TIMING_LL_FLASH_CORE_80M_CLK_DIV - 1));
HP_SYS_CLKRST.flash_ctrl0.reg_flash_core_clk_en = 1;
} else {
//ESP32S31 flash timing tuning is based on SPLL==480MHz, flash_core_clock==120MHz / 80MHz. We add assertion here to ensure this
HAL_ASSERT(false);
}
}
/*---------------------------------------------------------------
Misc
---------------------------------------------------------------*/
components/esp_hal_mspi/esp32s31/include/hal/spimem_flash_ll.h
+5 -6
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -240,7 +240,7 @@ static inline void spimem_flash_ll_set_sus_delay(spi_mem_dev_t *dev, uint32_t dl
*/
static inline void spimem_flash_set_cs_hold_delay(spi_mem_dev_t *dev, uint32_t cs_hold_delay)
{
// SPIMEM0ctrl2.cs_hold_delay = cs_hold_delay;
SPIMEM0.mem_ctrl2.mem_cs_hold_delay = cs_hold_delay;
}
/**
@@ -296,7 +296,7 @@ static inline bool spimem_flash_ll_sus_status(spi_mem_dev_t *dev)
static inline void spimem_flash_ll_sus_set_spi0_lock_trans(spi_mem_dev_t *dev, uint32_t lock_time)
{
dev->sus_status.spi0_lock_en = 1;
// SPIMEM0fsm.lock_delay_time = lock_time;
SPIMEM0.mem_fsm.mem_lock_delay_time = lock_time;
}
/**
@@ -677,7 +677,6 @@ static inline void spimem_flash_ll_set_fdummy_rin(spi_mem_dev_t *dev, uint32_t f
*/
static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
{
return 80;
int source_clk_mhz = 0;
switch (HP_SYS_CLKRST.flash_ctrl0.reg_flash_clk_src_sel) {
@@ -685,7 +684,7 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
source_clk_mhz = clk_ll_xtal_get_freq_mhz();
break;
case 1:
source_clk_mhz = CLK_LL_PLL_480M_FREQ_MHZ; // SPLL
source_clk_mhz = CLK_LL_PLL_480M_FREQ_MHZ; // BBPLL
break;
case 2:
source_clk_mhz = CLK_LL_PLL_320M_FREQ_MHZ; // CPLL
@@ -812,7 +811,7 @@ static inline void spimem_flash_ll_set_common_command_register_info(spi_mem_dev_
}
#define SPIMEM_FLASH_LL_SUSPEND_END_INTR SPI1_MEM_C_PES_END_INT_ENA_M
#define SPIMEM_FLASH_LL_INTERRUPT_SOURCE ETS_MSPI_INTR_SOURCE
#define SPIMEM_FLASH_LL_INTERRUPT_SOURCE ETS_MSPI_FLASH_INTR_SOURCE
/**
* @brief Get the address of the interrupt status register.
components/esp_hw_support/port/esp32s31/esp_clk_tree.c
+1
View File
@@ -94,6 +94,7 @@ void esp_clk_tree_initialize(void)
}
// Gating
// flash clock source is set to BBPLL in bootloader
}
bool esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+32 -4
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@@ -579,6 +579,30 @@ config SOC_SPIRAM_XIP_SUPPORTED
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_AUTO_RESUME
bool
default y
config SOC_SPI_MEM_SUPPORT_IDLE_INTR
bool
default y
config SOC_SPI_MEM_SUPPORT_SW_SUSPEND
bool
default y
config SOC_SPI_MEM_SUPPORT_CHECK_SUS
bool
default y
config SOC_SPI_MEM_SUPPORT_TIMING_TUNING
bool
default y
@@ -587,6 +611,14 @@ config SOC_MEMSPI_TIMING_TUNING_BY_DQS
bool
default y
config SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP
bool
default y
config SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR
bool
default y
config SOC_MSPI_HAS_INDEPENT_IOMUX
bool
default y
@@ -595,10 +627,6 @@ config SOC_MEMSPI_IS_INDEPENDENT
bool
default y
config SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT
bool
default y
config SOC_MEMSPI_ENCRYPTION_ALIGNMENT
int
default 16
components/soc/esp32s31/include/soc/soc_caps.h
+8 -1
View File
@@ -272,12 +272,19 @@
#define SOC_SPIRAM_XIP_SUPPORTED 1
/*-------------------------- SPI MEM CAPS ---------------------------------------*/
#define SOC_SPI_MEM_SUPPORT_AUTO_WAIT_IDLE (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_AUTO_RESUME (1)
#define SOC_SPI_MEM_SUPPORT_IDLE_INTR (1)
#define SOC_SPI_MEM_SUPPORT_SW_SUSPEND (1)
#define SOC_SPI_MEM_SUPPORT_CHECK_SUS (1)
#define SOC_SPI_MEM_SUPPORT_TIMING_TUNING (1)
#define SOC_MEMSPI_TIMING_TUNING_BY_DQS (1)
#define SOC_SPI_MEM_SUPPORT_CACHE_32BIT_ADDR_MAP (1)
#define SOC_SPI_MEM_SUPPORT_TSUS_TRES_SEPERATE_CTR (1)
#define SOC_MSPI_HAS_INDEPENT_IOMUX 1
#define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT 1
#define SOC_MEMSPI_ENCRYPTION_ALIGNMENT 16 /*!< 16-byte alignment restriction to mem addr and size if encryption is enabled */
components/spi_flash/esp32s31/Kconfig.flash_freq
+1 -1
View File
@@ -1,6 +1,6 @@
choice ESPTOOLPY_FLASHFREQ
prompt "Flash SPI speed"
default ESPTOOLPY_FLASHFREQ_40M
default ESPTOOLPY_FLASHFREQ_80M
config ESPTOOLPY_FLASHFREQ_80M
bool "80 MHz"
config ESPTOOLPY_FLASHFREQ_40M
components/spi_flash/test_apps/.build-test-rules.yml
-8
View File
@@ -1,10 +1,6 @@
# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
components/spi_flash/test_apps/esp_flash:
disable:
- if: IDF_TARGET in ["esp32s31"]
temporary: true
reason: not support yet # TODO: TODO: [esp32s31] IDF-14777
depends_filepatterns:
- components/bootloader_support/bootloader_flash/**/*
depends_components:
@@ -37,10 +33,6 @@ components/spi_flash/test_apps/esp_flash_freq_limit:
- esp_hw_support
components/spi_flash/test_apps/esp_flash_stress:
disable:
- if: IDF_TARGET in ["esp32s31"]
temporary: true
reason: not support yet # TODO: [ESP32S31] IDF-14777
depends_components:
- *common_components
- esp_mm
components/spi_flash/test_apps/components/test_flash_utils/test_flash_utils.c
+6 -1
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -14,6 +14,7 @@
#include "esp_partition.h"
#include "esp_log.h"
#include "esp_check.h"
#include "rom/cache.h"
#define ALIGN_UP_TO_64KB(x) (((x) + 0xFFFF) & ~0xFFFF)
@@ -137,7 +138,11 @@ esp_err_t spi_flash_suspend_test_deinit(flash_test_handle_t *handle)
void spi_flash_suspend_test_invalidate_cache(void)
{
#if CONFIG_IDF_TARGET_ESP32S31
Cache_Invalidate_All(CACHE_MAP_MASK);
#else
cache_ll_invalidate_all(CACHE_LL_LEVEL_ALL, CACHE_TYPE_ALL, CACHE_LL_ID_ALL);
#endif
}
#endif // SOC_SPI_MEM_SUPPORT_AUTO_SUSPEND
components/spi_flash/test_apps/esp_flash/README.md
+2 -2
View File
@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
components/spi_flash/test_apps/esp_flash/main/test_esp_flash_def.h
+1 -1
View File
@@ -77,7 +77,7 @@
#define SPI2_PIN_NUM_WP 2
#define SPI2_PIN_NUM_CS 1
#elif CONFIG_IDF_TARGET_ESP32P4
#elif CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32S31
// Just use the same pins for HSPI
#define SPI2_PIN_NUM_MOSI 8
components/spi_flash/test_apps/esp_flash/main/test_esp_flash_drv.c
+2
View File
@@ -1113,6 +1113,7 @@ void test_flash_counter(const esp_partition_t* part)
// check for resset_counter after used
TEST_ASSERT_EACH_EQUAL_HEX8(0, &flash_counter, sizeof(esp_flash_counters_t));
#if SOC_FLASH_ENC_SUPPORTED
TEST_ASSERT_EQUAL(ESP_OK, esp_flash_write_encrypted(chip, offs, write_buf, TEST_CNT_RW_LEN) );
TEST_ASSERT_EQUAL(ESP_OK, esp_flash_read_encrypted(chip, offs, read_buf, TEST_CNT_RW_LEN) );
@@ -1127,6 +1128,7 @@ void test_flash_counter(const esp_partition_t* part)
TEST_ASSERT_EQUAL_UINT32(1 * TEST_CNT_RW_LEN, flash_counter.read.bytes);
TEST_ASSERT_EQUAL_UINT32(1 * TEST_CNT_RW_LEN, flash_counter.write.bytes);
TEST_ASSERT_EQUAL_UINT32(0, flash_counter.erase.bytes);
#endif //SOC_FLASH_ENC_SUPPORTED
}
TEST_CASE_FLASH("SPI flash counter test", test_flash_counter);
components/spi_flash/test_apps/esp_flash/main/test_spi_flash.c
+1 -1
View File
@@ -122,7 +122,7 @@ TEST_CASE("flash write and erase work both on PRO CPU and on APP CPU", "[spi_fla
}
// TODO: This test is disabled on S3 with legacy impl - IDF-3505
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32P4)
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32, ESP32S2, ESP32S3, ESP32C3, ESP32P4, ESP32S31)
#if CONFIG_FREERTOS_NUMBER_OF_CORES > 1
typedef struct {
components/spi_flash/test_apps/esp_flash/pytest_esp_flash.py
-1
View File
@@ -17,7 +17,6 @@ from pytest_embedded_idf.utils import idf_parametrize
indirect=True,
)
@idf_parametrize('target', ['supported_targets'], indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done')
def test_esp_flash(dut: Dut) -> None:
dut.run_all_single_board_cases(group='esp_flash')
components/spi_flash/test_apps/esp_flash_stress/README.md
+2 -2
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
components/spi_flash/test_apps/esp_flash_stress/pytest_esp_flash_stress.py
-1
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@@ -14,7 +14,6 @@ from pytest_embedded_idf.utils import idf_parametrize
indirect=True,
)
@idf_parametrize('target', ['supported_targets'], indirect=['target'])
@pytest.mark.temp_skip_ci(targets=['esp32s31'], reason='s31 bringup on this module is not done')
def test_esp_flash_stress(dut: Dut) -> None:
dut.run_all_single_board_cases(group='esp_flash')
components/spi_flash/test_apps/flash_suspend/README.md
+2 -2
View File
@@ -1,2 +1,2 @@
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | ESP32-S31 |
| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | --------- |
components/spi_flash/test_apps/flash_suspend/main/test_flash_suspend.c
+2
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@@ -82,6 +82,8 @@ static bool IRAM_ATTR gptimer_alarm_suspend_cb(gptimer_handle_t timer, const gpt
cache_ll_invalidate_all(CACHE_LL_LEVEL_ALL, CACHE_TYPE_ALL, CACHE_LL_ID_ALL);
#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
Cache_Invalidate_All();
#elif CONFIG_IDF_TARGET_ESP32S31
Cache_Invalidate_All(CACHE_MAP_MASK);
#else
Cache_Invalidate_ICache_All();
#endif