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Merge branch 'fix/efuse_regs_store_operations' into 'master'

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feat(hal): Adds half-word read/write checks for efuse

Closes IDF-13567

See merge request espressif/esp-idf!41308
This commit is contained in:
Konstantin Kondrashov
2025-12-11 17:20:15 +08:00
parent 44de3dab81 4616a8269f
commit 52473e8638
13 changed files with 96 additions and 79 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/efuse/test_apps/CMakeLists.txt
+5
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@@ -5,3 +5,8 @@ set(COMPONENTS main)
include($ENV{IDF_PATH}/tools/cmake/project.cmake)
project(efuse_test)
message(STATUS "Checking efuse registers are not read-write by half-word")
include($ENV{IDF_PATH}/tools/ci/check_register_rw_half_word.cmake)
check_register_rw_half_word(SOC_MODULES "efuse"
HAL_MODULES "efuse")
components/hal/esp32/include/hal/efuse_ll.h
+7 -6
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/efuse_periph.h"
#include "hal/assert.h"
@@ -207,27 +208,27 @@ __attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(void)
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_READ_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_WRITE_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint32_t value)
{
EFUSE.dac_conf.dac_clk_div = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_clk_div, value);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_sel0(uint32_t value)
{
EFUSE.clk.clk_sel0 = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.clk, clk_sel0, value);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_sel1(uint32_t value)
{
EFUSE.clk.clk_sel1 = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.clk, clk_sel1, value);
}
/******************* eFuse control functions *************************/
components/hal/esp32c2/include/hal/efuse_ll.h
+10 -9
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "rom/efuse.h"
@@ -168,42 +169,42 @@ __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.cmd, val, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_READ_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_WRITE_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
{
EFUSE.dac_conf.dac_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
{
EFUSE.dac_conf.dac_clk_div = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_clk_div, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
{
EFUSE.wr_tim_conf1.pwr_on_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf1, pwr_on_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
{
EFUSE.wr_tim_conf2.pwr_off_num = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf2, pwr_off_num, value);
}
__attribute__((always_inline)) static inline void efuse_ll_set_tpgm_inactive(uint8_t value)
{
EFUSE.wr_tim_conf0.tpgm_inactive = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf0, tpgm_inactive, value);
}
/******************* eFuse control functions *************************/
components/hal/esp32c3/include/hal/efuse_ll.h
+9 -8
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "rom/efuse.h"
@@ -143,37 +144,37 @@ __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.cmd, val, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_READ_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_WRITE_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
{
EFUSE.dac_conf.dac_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
{
EFUSE.dac_conf.dac_clk_div = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_clk_div, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
{
EFUSE.wr_tim_conf1.pwr_on_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf1, pwr_on_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
{
EFUSE.wr_tim_conf2.pwr_off_num = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf2, pwr_off_num, value);
}
/******************* eFuse control functions *************************/
components/hal/esp32c5/include/hal/efuse_ll.h
+5 -4
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@@ -8,6 +8,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/efuse_defs.h"
#include "soc/efuse_reg.h"
#include "soc/efuse_periph.h"
@@ -158,22 +159,22 @@ __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.cmd, val, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_READ_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_WRITE_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
{
EFUSE.wr_tim_conf2.pwr_off_num = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf2, pwr_off_num, value);
}
__attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void)
components/hal/esp32c6/include/hal/efuse_ll.h
+9 -8
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "rom/efuse.h"
@@ -151,37 +152,37 @@ __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.cmd, val, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_READ_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_WRITE_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
{
EFUSE.dac_conf.dac_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
{
EFUSE.dac_conf.dac_clk_div = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_clk_div, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
{
EFUSE.wr_tim_conf1.pwr_on_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf1, pwr_on_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
{
EFUSE.wr_tim_conf2.pwr_off_num = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf2, pwr_off_num, value);
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_controller_state(void)
components/hal/esp32c61/include/hal/efuse_ll.h
+8 -7
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@@ -8,6 +8,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/efuse_defs.h"
#include "soc/efuse_reg.h"
#include "soc/efuse_struct.h"
@@ -164,37 +165,37 @@ __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
EFUSE0.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE0.cmd, val, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE0.conf.op_code = EFUSE_READ_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE0.conf, op_code, EFUSE_READ_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE0.conf.op_code = EFUSE_WRITE_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE0.conf, op_code, EFUSE_WRITE_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
{
EFUSE0.dac_conf.dac_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE0.dac_conf, dac_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
{
EFUSE0.dac_conf.dac_clk_div = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE0.dac_conf, dac_clk_div, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
{
EFUSE0.wr_tim_conf1.pwr_on_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE0.wr_tim_conf1, pwr_on_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
{
EFUSE0.wr_tim_conf2.pwr_off_num = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE0.wr_tim_conf2, pwr_off_num, value);
}
__attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void)
components/hal/esp32h2/include/hal/efuse_ll.h
+8 -7
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@@ -8,6 +8,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "rom/efuse.h"
@@ -132,37 +133,37 @@ __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.cmd, val, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_READ_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_WRITE_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
{
EFUSE.dac_conf.dac_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
{
EFUSE.dac_conf.dac_clk_div = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_clk_div, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
{
EFUSE.wr_tim_conf1.pwr_on_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf1, pwr_on_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
{
EFUSE.wr_tim_conf2.pwr_off_num = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf2, pwr_off_num, value);
}
__attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void)
components/hal/esp32h21/include/hal/efuse_ll.h
+8 -7
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@@ -8,6 +8,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "rom/efuse.h"
@@ -122,37 +123,37 @@ __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.cmd, val, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_READ_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_WRITE_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
{
EFUSE.dac_conf.dac_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
{
EFUSE.dac_conf.dac_clk_div = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_clk_div, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
{
EFUSE.wr_tim_conf1.pwr_on_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf1, pwr_on_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
{
EFUSE.wr_tim_conf2.pwr_off_num = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf2, pwr_off_num, value);
}
__attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void)
components/hal/esp32h4/include/hal/efuse_ll.h
+8 -7
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@@ -8,6 +8,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "rom/efuse.h"
@@ -117,12 +118,12 @@ __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.cmd, val, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_READ_OP_CODE);
}
__attribute__((always_inline)) static inline int efuse_ll_get_ocode(void)
@@ -132,27 +133,27 @@ __attribute__((always_inline)) static inline int efuse_ll_get_ocode(void)
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_WRITE_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
{
//EFUSE.dac_conf.dac_num = val;
//HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
{
//EFUSE.dac_conf.dac_clk_div = val;
//HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_clk_div, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
{
//EFUSE.wr_tim_conf1.pwr_on_num = val;
//HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf1, pwr_on_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
{
EFUSE.wr_tim_conf2.pwr_off_num = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf2, pwr_off_num, value);
}
__attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void)
components/hal/esp32p4/include/hal/efuse_ll.h
+5 -4
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@@ -8,6 +8,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "rom/efuse.h"
@@ -131,22 +132,22 @@ __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.cmd, val, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_READ_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_WRITE_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
{
EFUSE.wr_tim_conf2.pwr_off_num = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf2, pwr_off_num, value);
}
__attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void)
components/hal/esp32s2/include/hal/efuse_ll.h
+5 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "rom/efuse.h"
@@ -140,17 +141,17 @@ __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.cmd, val, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_READ_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_WRITE_OP_CODE);
}
/******************* eFuse control functions *************************/
components/hal/esp32s3/include/hal/efuse_ll.h
+9 -8
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,7 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/misc.h"
#include "soc/efuse_periph.h"
#include "hal/assert.h"
#include "rom/efuse.h"
@@ -143,37 +144,37 @@ __attribute__((always_inline)) static inline void efuse_ll_set_read_cmd(void)
__attribute__((always_inline)) static inline void efuse_ll_set_pgm_cmd(uint32_t block)
{
HAL_ASSERT(block < ETS_EFUSE_BLOCK_MAX);
EFUSE.cmd.val = ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.cmd, val, ((block << EFUSE_BLK_NUM_S) & EFUSE_BLK_NUM_M) | EFUSE_PGM_CMD);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code(void)
{
EFUSE.conf.op_code = EFUSE_READ_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_READ_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
{
EFUSE.conf.op_code = EFUSE_WRITE_OP_CODE;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.conf, op_code, EFUSE_WRITE_OP_CODE);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
{
EFUSE.dac_conf.dac_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
{
EFUSE.dac_conf.dac_clk_div = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_clk_div, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
{
EFUSE.wr_tim_conf1.pwr_on_num = val;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf1, pwr_on_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
{
EFUSE.wr_tim_conf2.pwr_off_num = value;
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf2, pwr_off_num, value);
}
/******************* eFuse control functions *************************/