espressif/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-04-27 19:13:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

fix(wifi): fix external coexistence depends on wifi connect issue

Browse Source
This commit is contained in:
muhaidong
2025-11-24 15:02:16 +08:00
parent a2704d67b7
commit 543bc1358c
7 changed files with 88 additions and 28 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_coex/src/coexist.c
+3 -10
View File
@@ -17,9 +17,7 @@
#include "esp_private/gpio.h"
#endif
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
#include "esp_private/esp_modem_clock.h"
#endif
#include "esp_private/periph_ctrl.h"
#if CONFIG_ESP_COEX_SW_COEXIST_ENABLE && CONFIG_SOC_IEEE802154_SUPPORTED
#include "esp_coex_i154.h"
@@ -267,16 +265,11 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
return ESP_ERR_INVALID_ARG;
#endif /* SOC_EXTERNAL_COEX_ADVANCE */
}
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_enable(PERIPH_COEX_MODULE);
#endif
coex_module_enable();
#if SOC_EXTERNAL_COEX_ADVANCE
esp_coex_external_params(g_external_coex_params, 0, 0);
#endif
esp_err_t ret = esp_coex_external_set(EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_MID, EXTERN_COEX_PTI_HIGH);
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_disable(PERIPH_COEX_MODULE);
#endif
if (ESP_OK != ret) {
return ESP_FAIL;
}
@@ -286,7 +279,7 @@ esp_err_t esp_enable_extern_coex_gpio_pin(external_coex_wire_t wire_type, esp_ex
esp_err_t esp_disable_extern_coex_gpio_pin(void)
{
esp_coex_external_stop();
coex_module_disable();
return ESP_OK;
}
#endif /* External Coex */
components/esp_coex/src/coexist_debug.c
+6 -16
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2018-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2018-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -19,9 +19,7 @@
#include "soc/gpio_sig_map.h"
#include "esp_rom_gpio.h"
#include "soc/soc.h"
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
#include "esp_private/esp_modem_clock.h"
#endif
#include "esp_private/periph_ctrl.h"
#if CONFIG_ESP_COEX_GPIO_DEBUG
static char* TAG = "coexist debug";
@@ -192,13 +190,9 @@ esp_err_t esp_coexist_debug_matrix_init(int evt, int sig, bool rev)
esp_err_t esp_coexist_gpio_debug_matrix_config(int event)
{
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_enable(PERIPH_COEX_MODULE);
#endif
coex_module_enable();
esp_err_t ret = coex_gpio_debug_matrix_config(event);
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_disable(PERIPH_COEX_MODULE);
#endif
coex_module_disable();
return ret;
}
@@ -265,14 +259,10 @@ esp_err_t esp_coexist_debug_init(void)
gpio_set_level(s_io_nums[i], false);
}
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_enable(PERIPH_COEX_MODULE);
#endif
coex_module_enable();
/* Init coexist hardware signal */
ESP_ERROR_CHECK(coex_gpio_debug_matrix_init());
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_disable(PERIPH_COEX_MODULE);
#endif
coex_module_disable();
return ESP_OK;
}
components/esp_hw_support/include/esp_private/periph_ctrl.h
+19
View File
@@ -175,6 +175,25 @@ void phy_module_disable(void);
*/
bool phy_module_has_clock_bits(uint32_t mask);
/**
* @brief Enable coex module
*
* @note Calling this function will only enable coex module.
* @note For ESP32S2, ESP32S3, and ESP32C3, this function has no effect because
* the coex module clock is controlled by the modem clock. On these chips,
* you must call esp_wifi_init() to enable the modem clock before using
* external coexistence features.
*/
void coex_module_enable(void);
/**
* @brief Disable coex module
*
* @note Calling this function will only disable coex module.
* @note For ESP32S2, ESP32S3, and ESP32C3, this function has no effect because
* the coex module clock is controlled by the modem clock.
*/
void coex_module_disable(void);
#undef __PERIPH_CTRL_DEPRECATE_ATTR
#ifdef __cplusplus
components/esp_hw_support/periph_ctrl.c
+44
View File
@@ -104,6 +104,12 @@ IRAM_ATTR void wifi_bt_common_module_enable(void)
periph_ll_wifi_bt_module_enable_clk();
}
ref_counts[PERIPH_WIFI_BT_COMMON_MODULE]++;
#if CONFIG_IDF_TARGET_ESP32C2
if (ref_counts[PERIPH_COEX_MODULE] == 0) {
periph_ll_coex_module_enable_clk_clear_rst();
}
ref_counts[PERIPH_COEX_MODULE]++;
#endif
portEXIT_CRITICAL_SAFE(&periph_spinlock);
#endif
}
@@ -118,6 +124,12 @@ IRAM_ATTR void wifi_bt_common_module_disable(void)
if (ref_counts[PERIPH_WIFI_BT_COMMON_MODULE] == 0) {
periph_ll_wifi_bt_module_disable_clk();
}
#if CONFIG_IDF_TARGET_ESP32C2
ref_counts[PERIPH_COEX_MODULE]--;
if (ref_counts[PERIPH_COEX_MODULE] == 0) {
periph_ll_coex_module_disable_clk_set_rst();
}
#endif
portEXIT_CRITICAL_SAFE(&periph_spinlock);
#endif
}
@@ -230,4 +242,36 @@ IRAM_ATTR bool phy_module_has_clock_bits(uint32_t mask)
}
return true;
}
IRAM_ATTR void coex_module_enable(void)
{
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_enable(PERIPH_COEX_MODULE);
#else
portENTER_CRITICAL_SAFE(&periph_spinlock);
#if CONFIG_IDF_TARGET_ESP32C2
if (ref_counts[PERIPH_COEX_MODULE] == 0) {
periph_ll_coex_module_enable_clk_clear_rst();
}
ref_counts[PERIPH_COEX_MODULE]++;
#endif
portEXIT_CRITICAL_SAFE(&periph_spinlock);
#endif
}
IRAM_ATTR void coex_module_disable(void)
{
#if SOC_MODEM_CLOCK_IS_INDEPENDENT
modem_clock_module_disable(PERIPH_COEX_MODULE);
#else
portENTER_CRITICAL_SAFE(&periph_spinlock);
#if CONFIG_IDF_TARGET_ESP32C2
ref_counts[PERIPH_COEX_MODULE]--;
if (ref_counts[PERIPH_COEX_MODULE] == 0) {
periph_ll_coex_module_disable_clk_set_rst();
}
#endif
portEXIT_CRITICAL_SAFE(&periph_spinlock);
#endif
}
#endif //#if SOC_BT_SUPPORTED || SOC_WIFI_SUPPORTED || SOC_IEEE802154_SUPPORTED
components/hal/esp32c2/include/hal/clk_gate_ll.h
+11
View File
@@ -226,6 +226,17 @@ static inline void periph_ll_phy_calibration_module_disable_clk_set_rst(void)
DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_coex_module_enable_clk_clear_rst(void)
{
DPORT_SET_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_COEX_EN_M);
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
static inline void periph_ll_coex_module_disable_clk_set_rst(void)
{
DPORT_CLEAR_PERI_REG_MASK(SYSTEM_WIFI_CLK_EN_REG, SYSTEM_WIFI_CLK_COEX_EN_M);
DPORT_SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG, 0);
}
#ifdef __cplusplus
}
#endif
components/soc/esp32c2/include/soc/periph_defs.h
+1
View File
@@ -38,6 +38,7 @@ typedef enum {
PERIPH_MODEM_RPA_MODULE,
PERIPH_ASSIST_DEBUG_MODULE,
PERIPH_PHY_CALIBRATION_MODULE,
PERIPH_COEX_MODULE,
PERIPH_MODULE_MAX
} periph_module_t;
components/soc/esp32c2/register/soc/syscon_reg.h
+4 -2
View File
@@ -178,8 +178,10 @@ extern "C" {
#define SYSTEM_WIFI_CLK_BT_EN_S 0
/* Mask for clock bits used by both WIFI and Bluetooth, 0, 1, 2, 3, 7, 8, 9, 10, 19, 20, 21, 22, 23 */
#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x78078F
/* Mask for clock bits used by phy calibration, bit 22, 29, 30, 31 */
#define SYSTEM_WIFI_CLK_PHY_EN_M 0xE0400000
/* Mask for clock bits used by phy calibration, bit 22, 30, 31 */
#define SYSTEM_WIFI_CLK_PHY_EN_M 0xC0400000
/* Mask for clock bits used by coex, bit 29 */
#define SYSTEM_WIFI_CLK_COEX_EN_M 0x20000000
/* Digital team to check */
//bluetooth baseband bit11