espressif/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-04-27 19:13:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

feat(mcpwm): support mcpwm on esp32s31

Browse Source 
- Remove duplicate 'MCPWM ETM timer event table' comment (esp32h2, esp32c6, esp32h21)
- esp32s31 clk_tree_defs: add PLL20M enum for MCPWM timer/capture/carrier to match SOC_MCPWM_*_CLKS

Made-with: Cursor
This commit is contained in:
Chen Chen
2026-02-12 16:46:07 +08:00
parent a7cd298f02
commit 675aa0695c
19 changed files with 2362 additions and 378 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_driver_mcpwm/test_apps/mcpwm/README.md
+2 -2
View File
@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | --------- |
components/esp_driver_mcpwm/test_apps/mcpwm/main/test_mcpwm_gen.c
+13 -13
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -417,18 +417,18 @@ static void mcpwm_gen_action_test_template(uint32_t timer_resolution, uint32_t p
}
TEST_ESP_OK(mcpwm_timer_disable(timer));
TEST_ESP_OK(mcpwm_del_generator(generator_a));
TEST_ESP_OK(mcpwm_del_generator(generator_b));
TEST_ESP_OK(mcpwm_del_comparator(comparator_a));
TEST_ESP_OK(mcpwm_del_comparator(comparator_b));
TEST_ESP_OK(mcpwm_del_operator(oper));
TEST_ESP_OK(mcpwm_del_timer(timer));
TEST_ESP_OK(mcpwm_capture_channel_disable(cap_channel_a));
TEST_ESP_OK(mcpwm_del_capture_channel(cap_channel_a));
TEST_ESP_OK(mcpwm_capture_channel_disable(cap_channel_b));
TEST_ESP_OK(mcpwm_del_capture_channel(cap_channel_b));
TEST_ESP_OK(mcpwm_capture_timer_disable(cap_timer));
TEST_ESP_OK(mcpwm_del_capture_timer(cap_timer));
TEST_ESP_OK(mcpwm_del_generator(generator_a));
TEST_ESP_OK(mcpwm_del_generator(generator_b));
TEST_ESP_OK(mcpwm_del_comparator(comparator_a));
TEST_ESP_OK(mcpwm_del_comparator(comparator_b));
TEST_ESP_OK(mcpwm_del_operator(oper));
TEST_ESP_OK(mcpwm_del_timer(timer));
}
static void single_edge_active_high(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb)
@@ -651,18 +651,18 @@ static void mcpwm_deadtime_test_template(uint32_t timer_resolution, uint32_t per
ret_capb[1] = cap_value_b[1] * 1000 / clk_src_res;
TEST_ESP_OK(mcpwm_timer_disable(timer));
TEST_ESP_OK(mcpwm_del_generator(generator_a));
TEST_ESP_OK(mcpwm_del_generator(generator_b));
TEST_ESP_OK(mcpwm_del_comparator(comparator_a));
TEST_ESP_OK(mcpwm_del_comparator(comparator_b));
TEST_ESP_OK(mcpwm_del_operator(oper));
TEST_ESP_OK(mcpwm_del_timer(timer));
TEST_ESP_OK(mcpwm_capture_channel_disable(cap_channel_a));
TEST_ESP_OK(mcpwm_del_capture_channel(cap_channel_a));
TEST_ESP_OK(mcpwm_capture_channel_disable(cap_channel_b));
TEST_ESP_OK(mcpwm_del_capture_channel(cap_channel_b));
TEST_ESP_OK(mcpwm_capture_timer_disable(cap_timer));
TEST_ESP_OK(mcpwm_del_capture_timer(cap_timer));
TEST_ESP_OK(mcpwm_del_generator(generator_a));
TEST_ESP_OK(mcpwm_del_generator(generator_b));
TEST_ESP_OK(mcpwm_del_comparator(comparator_a));
TEST_ESP_OK(mcpwm_del_comparator(comparator_b));
TEST_ESP_OK(mcpwm_del_operator(oper));
TEST_ESP_OK(mcpwm_del_timer(timer));
}
static void ahc_set_generator_actions(mcpwm_gen_handle_t gena, mcpwm_gen_handle_t genb, mcpwm_cmpr_handle_t cmpa, mcpwm_cmpr_handle_t cmpb)
components/esp_hal_mcpwm/esp32c6/include/hal/mcpwm_ll.h
-1
View File
@@ -70,7 +70,6 @@ extern "C" {
#define MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) ((uint8_t[]) {0, 1, 2, 3}[(action)])
#define MCPWM_LL_BRAKE_MODE_TO_REG_VAL(mode) ((uint8_t[]) {0, 1}[(mode)])
// MCPWM ETM timer event table
// MCPWM ETM timer event table
#define MCPWM_LL_ETM_TIMER_EVENT_TABLE(group, timer_id, event) \
(uint32_t[1][MCPWM_TIMER_ETM_EVENT_MAX]){{ \
components/esp_hal_mcpwm/esp32h2/include/hal/mcpwm_ll.h
-1
View File
@@ -68,7 +68,6 @@ extern "C" {
#define MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) ((uint8_t[]) {0, 1, 2, 3}[(action)])
#define MCPWM_LL_BRAKE_MODE_TO_REG_VAL(mode) ((uint8_t[]) {0, 1}[(mode)])
// MCPWM ETM timer event table
// MCPWM ETM timer event table
#define MCPWM_LL_ETM_TIMER_EVENT_TABLE(group, timer_id, event) \
(uint32_t[1][MCPWM_TIMER_ETM_EVENT_MAX]){{ \
components/esp_hal_mcpwm/esp32h21/include/hal/mcpwm_ll.h
-1
View File
@@ -68,7 +68,6 @@ extern "C" {
#define MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) ((uint8_t[]) {0, 1, 2, 3}[(action)])
#define MCPWM_LL_BRAKE_MODE_TO_REG_VAL(mode) ((uint8_t[]) {0, 1}[(mode)])
// MCPWM ETM timer event table
// MCPWM ETM timer event table
#define MCPWM_LL_ETM_TIMER_EVENT_TABLE(group, timer_id, event) \
(uint32_t[1][MCPWM_TIMER_ETM_EVENT_MAX]){{ \
components/esp_hal_mcpwm/esp32s31/include/hal/mcpwm_ll.h
+1782
View File
File diff suppressed because it is too large Load Diff
components/esp_hal_mcpwm/esp32s31/mcpwm_periph.c
+355
View File
@@ -0,0 +1,355 @@
/*
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/soc.h"
#include "hal/mcpwm_periph.h"
#include "soc/mcpwm_reg.h"
#include "soc/gpio_sig_map.h"
const soc_mcpwm_signal_desc_t soc_mcpwm_signals[4] = {
{
.module_name = "MCPWM0",
.irq_id = ETS_PWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_CH0_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM0_CH0_B_PAD_OUT_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_CH1_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM0_CH1_B_PAD_OUT_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_CH2_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM0_CH2_B_PAD_OUT_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_PAD_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_PAD_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_PAD_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_PAD_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_PAD_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_PAD_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_PAD_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_PAD_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_PAD_IN_IDX
}
}
},
{
.module_name = "MCPWM1",
.irq_id = ETS_PWM1_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM1_CH0_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM1_CH0_B_PAD_OUT_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM1_CH1_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM1_CH1_B_PAD_OUT_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM1_CH2_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM1_CH2_B_PAD_OUT_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM1_F0_PAD_IN_IDX
},
[1] = {
.fault_sig = PWM1_F1_PAD_IN_IDX
},
[2] = {
.fault_sig = PWM1_F2_PAD_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM1_CAP0_PAD_IN_IDX
},
[1] = {
.cap_sig = PWM1_CAP1_PAD_IN_IDX
},
[2] = {
.cap_sig = PWM1_CAP2_PAD_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM1_SYNC0_PAD_IN_IDX
},
[1] = {
.sync_sig = PWM1_SYNC1_PAD_IN_IDX
},
[2] = {
.sync_sig = PWM1_SYNC2_PAD_IN_IDX
}
}
},
{
.module_name = "MCPWM2",
.irq_id = ETS_PWM2_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM2_CH0_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM2_CH0_B_PAD_OUT_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM2_CH1_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM2_CH1_B_PAD_OUT_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM2_CH2_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM2_CH2_B_PAD_OUT_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM2_F0_PAD_IN_IDX
},
[1] = {
.fault_sig = PWM2_F1_PAD_IN_IDX
},
[2] = {
.fault_sig = PWM2_F2_PAD_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM2_CAP0_PAD_IN_IDX
},
[1] = {
.cap_sig = PWM2_CAP1_PAD_IN_IDX
},
[2] = {
.cap_sig = PWM2_CAP2_PAD_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM2_SYNC0_PAD_IN_IDX
},
[1] = {
.sync_sig = PWM2_SYNC1_PAD_IN_IDX
},
[2] = {
.sync_sig = PWM2_SYNC2_PAD_IN_IDX
}
}
},
{
.module_name = "MCPWM3",
.irq_id = ETS_PWM3_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM3_CH0_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM3_CH0_B_PAD_OUT_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM3_CH1_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM3_CH1_B_PAD_OUT_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM3_CH2_A_PAD_OUT_IDX
},
[1] = {
.pwm_sig = PWM3_CH2_B_PAD_OUT_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM3_F0_PAD_IN_IDX
},
[1] = {
.fault_sig = PWM3_F1_PAD_IN_IDX
},
[2] = {
.fault_sig = PWM3_F2_PAD_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM3_CAP0_PAD_IN_IDX
},
[1] = {
.cap_sig = PWM3_CAP1_PAD_IN_IDX
},
[2] = {
.cap_sig = PWM3_CAP2_PAD_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM3_SYNC0_PAD_IN_IDX
},
[1] = {
.sync_sig = PWM3_SYNC1_PAD_IN_IDX
},
[2] = {
.sync_sig = PWM3_SYNC2_PAD_IN_IDX
}
}
}
};
#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
/**
* MCPWM Registers to be saved during sleep retention
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG2_REG, MCPWM_TIMER0_CFG3_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
* |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG
* └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG
* - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG
* - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG
* - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
* - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
*/
#define MCPWM_RETENTION_REGS_CNT 73
#define MCPWM_RETENTION_REGS_BASE(i) REG_MCPWM_BASE(i)
static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0x1f8ff8c, 0x0};
#define MCPWM_SLEEP_RETENTION_ENTRIES(mcpwm_port) { \
/* backup stage: save configuration registers \
restore stage: restore the configuration registers */ \
[0] = { .config = REGDMA_LINK_ADDR_MAP_INIT( \
REGDMA_MCPWM_LINK(0x00), \
MCPWM_RETENTION_REGS_BASE(mcpwm_port), \
MCPWM_RETENTION_REGS_BASE(mcpwm_port), \
MCPWM_RETENTION_REGS_CNT, 0, 0, \
mcpwm_regs_map[0], mcpwm_regs_map[1], \
mcpwm_regs_map[2], mcpwm_regs_map[3]), \
.owner = ENTRY(0)}, \
/* restore stage: trigger a forced update of all active registers*/ \
[1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01), \
MCPWM_UPDATE_CFG_REG(mcpwm_port), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), \
.owner = ENTRY(0) }, \
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02), \
MCPWM_UPDATE_CFG_REG(mcpwm_port), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0), \
.owner = ENTRY(0) }, \
};
static const regdma_entries_config_t mcpwm0_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(0);
static const regdma_entries_config_t mcpwm1_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(1);
static const regdma_entries_config_t mcpwm2_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(2);
static const regdma_entries_config_t mcpwm3_regs_retention[] = MCPWM_SLEEP_RETENTION_ENTRIES(3);
const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[4] = {
[0] = {
.regdma_entry_array = mcpwm0_regs_retention,
.array_size = ARRAY_SIZE(mcpwm0_regs_retention),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM0
},
[1] = {
.regdma_entry_array = mcpwm1_regs_retention,
.array_size = ARRAY_SIZE(mcpwm1_regs_retention),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM1
},
[2] = {
.regdma_entry_array = mcpwm2_regs_retention,
.array_size = ARRAY_SIZE(mcpwm2_regs_retention),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM2
},
[3] = {
.regdma_entry_array = mcpwm3_regs_retention,
.array_size = ARRAY_SIZE(mcpwm3_regs_retention),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM3
},
};
#endif //SOC_MCPWM_SUPPORT_SLEEP_RETENTION
components/soc/esp32s31/include/soc/Kconfig.soc_caps.in
+20
View File
@@ -31,6 +31,10 @@ config SOC_GPTIMER_SUPPORTED
bool
default y
config SOC_MCPWM_SUPPORTED
bool
default y
config SOC_ASYNC_MEMCPY_SUPPORTED
bool
default y
@@ -526,3 +530,19 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
config SOC_RTC_TIMER_V3
bool
default y
config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
config SOC_MCPWM_SUPPORT_ETM
bool
default y
config SOC_MCPWM_SUPPORT_EVENT_COMPARATOR
bool
default y
config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
bool
default y
components/soc/esp32s31/include/soc/clk_tree_defs.h
+47
View File
@@ -317,6 +317,53 @@ typedef enum {
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M clock as the default clock choice */
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MCPWM Timer
*/
#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F160M}
/**
* @brief Type of MCPWM timer clock source
*/
typedef enum {
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_TIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
MCPWM_TIMER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */
} soc_periph_mcpwm_timer_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Capture Timer
*/
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_PLL_F160M}
/**
* @brief Type of MCPWM capture clock source
*/
typedef enum {
MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CAPTURE_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
MCPWM_CAPTURE_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */
} soc_periph_mcpwm_capture_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Carrier
*/
#define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F20M, SOC_MOD_CLK_PLL_F160M}
/**
* @brief Type of MCPWM carrier clock source
*/
typedef enum {
MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CARRIER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
MCPWM_CARRIER_CLK_SRC_PLL160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default choice */
} soc_periph_mcpwm_carrier_clk_src_t;
//////////////////////////////////////////////CLOCK OUTPUT///////////////////////////////////////////////////////////
typedef enum {
CLKOUT_SIG_MPLL = 0, /*!< MPLL is from 40MHz XTAL oscillator frequency multipliers */
components/soc/esp32s31/include/soc/soc_caps.h
+8 -1
View File
@@ -39,7 +39,7 @@
// #define SOC_LCDCAM_CAM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14722
// #define SOC_LCDCAM_I80_LCD_SUPPORTED 1 // TODO: [ESP32S31] IDF-14722
// #define SOC_LCDCAM_RGB_LCD_SUPPORTED 1 // TODO: [ESP32S31] IDF-14722
// #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14756
#define SOC_MCPWM_SUPPORTED 1
// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32S31] IDF-14719
// #define SOC_ETM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14724
// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32S31] IDF-14711
@@ -325,3 +325,10 @@
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
#define SOC_RTC_TIMER_V3 1
/*-------------------------- MCPWM CAPS --------------------------------------*/
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
#define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
#define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR (1) ///< Support event comparator (based on ETM)
#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
// #define SOC_MCPWM_SUPPORT_SLEEP_RETENTION (1) ///< Support back up registers before sleep
components/soc/esp32s31/register/soc/mcpwm_reg.h
+3
View File
@@ -7,6 +7,9 @@
#include <stdint.h>
#include "soc/soc.h"
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM0_BASE + (i) * 0x1000)
#ifdef __cplusplus
extern "C" {
#endif
components/soc/esp32s31/register/soc/mcpwm_struct.h
+113 -341
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -242,33 +242,19 @@ typedef union {
uint32_t val;
} mcpwm_genn_stmp_cfg_reg_t;
/** Type of genn_tstmp_a register
* Generatorn time stamp A's shadow register
/** Type of genn_tstmp register
* Generatorn time stamp shadow register (unified type for array access)
*/
typedef union {
struct {
/** cmprn_a : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator n time stamp A's shadow register.
/** cmprn : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator n time stamp shadow register.
*/
uint32_t cmprn_a:16;
uint32_t cmprn:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_genn_tstmp_a_reg_t;
/** Type of genn_tstmp_b register
* Generatorn time stamp B's shadow register
*/
typedef union {
struct {
/** cmprn_b : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator n time stamp B's shadow register.
*/
uint32_t cmprn_b:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_genn_tstmp_b_reg_t;
} mcpwm_genn_tstmp_reg_t;
/** Type of genn_cfg0 register
* Generatorn fault event T0 and T1 configuration register
@@ -371,217 +357,76 @@ typedef union {
uint32_t val;
} mcpwm_genn_force_reg_t;
/** Type of genn_a register
* PWMn output signal A actions configuration register
*/
typedef union {
struct {
/** genn_a_utez : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWMn A triggered by event TEZ when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_utez:2;
/** genn_a_utep : R/W; bitpos: [3:2]; default: 0;
* Configures action on PWMn A triggered by event TEP when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_utep:2;
/** genn_a_utea : R/W; bitpos: [5:4]; default: 0;
* Configures action on PWMn A triggered by event TEA when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_utea:2;
/** genn_a_uteb : R/W; bitpos: [7:6]; default: 0;
* Configures action on PWMn A triggered by event TEB when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_uteb:2;
/** genn_a_ut0 : R/W; bitpos: [9:8]; default: 0;
* Configures action on PWMn A triggered by event_t0 when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_ut0:2;
/** genn_a_ut1 : R/W; bitpos: [11:10]; default: 0;
* Configures action on PWMn A triggered by event_t1 when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_ut1:2;
/** genn_a_dtez : R/W; bitpos: [13:12]; default: 0;
* Configures action on PWMn A triggered by event TEZ when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_dtez:2;
/** genn_a_dtep : R/W; bitpos: [15:14]; default: 0;
* Configures action on PWMn A triggered by event TEP when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_dtep:2;
/** genn_a_dtea : R/W; bitpos: [17:16]; default: 0;
* Configures action on PWMn A triggered by event TEA when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_dtea:2;
/** genn_a_dteb : R/W; bitpos: [19:18]; default: 0;
* Configures action on PWMn A triggered by event TEB when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_dteb:2;
/** genn_a_dt0 : R/W; bitpos: [21:20]; default: 0;
* Configures action on PWMn A triggered by event_t0 when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_dt0:2;
/** genn_a_dt1 : R/W; bitpos: [23:22]; default: 0;
* Configures action on PWMn A triggered by event_t1 when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_dt1:2;
uint32_t reserved_24:8;
};
uint32_t val;
} mcpwm_genn_a_reg_t;
/** Type of genn_b register
* PWMn output signal B actions configuration register
/** Type of genn register
* PWMn output signal actions configuration register (unified type for array access)
*/
typedef union {
struct {
/** genn_b_utez : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWMn B triggered by event TEZ when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
/** genn_utez : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWMn triggered by event TEZ when timer increasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_utez:2;
/** genn_b_utep : R/W; bitpos: [3:2]; default: 0;
* Configures action on PWMn B triggered by event TEP when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_utez:2;
/** genn_utep : R/W; bitpos: [3:2]; default: 0;
* Configures action on PWMn triggered by event TEP when timer increasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_utep:2;
/** genn_b_utea : R/W; bitpos: [5:4]; default: 0;
* Configures action on PWMn B triggered by event TEA when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_utep:2;
/** genn_utea : R/W; bitpos: [5:4]; default: 0;
* Configures action on PWMn triggered by event TEA when timer increasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_utea:2;
/** genn_b_uteb : R/W; bitpos: [7:6]; default: 0;
* Configures action on PWMn B triggered by event TEB when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_utea:2;
/** genn_uteb : R/W; bitpos: [7:6]; default: 0;
* Configures action on PWMn triggered by event TEB when timer increasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_uteb:2;
/** genn_b_ut0 : R/W; bitpos: [9:8]; default: 0;
* Configures action on PWMn B triggered by event_t0 when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_uteb:2;
/** genn_ut0 : R/W; bitpos: [9:8]; default: 0;
* Configures action on PWMn triggered by event_t0 when timer increasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_ut0:2;
/** genn_b_ut1 : R/W; bitpos: [11:10]; default: 0;
* Configures action on PWMn B triggered by event_t1 when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_ut0:2;
/** genn_ut1 : R/W; bitpos: [11:10]; default: 0;
* Configures action on PWMn triggered by event_t1 when timer increasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_ut1:2;
/** genn_b_dtez : R/W; bitpos: [13:12]; default: 0;
* Configures action on PWMn B triggered by event TEZ when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_ut1:2;
/** genn_dtez : R/W; bitpos: [13:12]; default: 0;
* Configures action on PWMn triggered by event TEZ when timer decreasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_dtez:2;
/** genn_b_dtep : R/W; bitpos: [15:14]; default: 0;
* Configures action on PWMn B triggered by event TEP when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_dtez:2;
/** genn_dtep : R/W; bitpos: [15:14]; default: 0;
* Configures action on PWMn triggered by event TEP when timer decreasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_dtep:2;
/** genn_b_dtea : R/W; bitpos: [17:16]; default: 0;
* Configures action on PWMn B triggered by event TEA when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_dtep:2;
/** genn_dtea : R/W; bitpos: [17:16]; default: 0;
* Configures action on PWMn triggered by event TEA when timer decreasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_dtea:2;
/** genn_b_dteb : R/W; bitpos: [19:18]; default: 0;
* Configures action on PWMn B triggered by event TEB when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_dtea:2;
/** genn_dteb : R/W; bitpos: [19:18]; default: 0;
* Configures action on PWMn triggered by event TEB when timer decreasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_dteb:2;
/** genn_b_dt0 : R/W; bitpos: [21:20]; default: 0;
* Configures action on PWMn B triggered by event_t0 when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_dteb:2;
/** genn_dt0 : R/W; bitpos: [21:20]; default: 0;
* Configures action on PWMn triggered by event_t0 when timer decreasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_dt0:2;
/** genn_b_dt1 : R/W; bitpos: [23:22]; default: 0;
* Configures action on PWMn B triggered by event_t1 when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_dt0:2;
/** genn_dt1 : R/W; bitpos: [23:22]; default: 0;
* Configures action on PWMn triggered by event_t1 when timer decreasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_dt1:2;
uint32_t genn_dt1:2;
uint32_t reserved_24:8;
};
uint32_t val;
} mcpwm_genn_b_reg_t;
} mcpwm_genn_reg_t;
/** Type of dtn_cfg register
* Dead time configuration register
@@ -1570,33 +1415,19 @@ typedef union {
uint32_t val;
} mcpwm_evt_en2_reg_t;
/** Type of opn_tstmp_e1 register
* Generatorn timer stamp E1 value register
/** Type of opn_tstmp register
* Operator timestamp register (unified type for array access)
*/
typedef union {
struct {
/** opn_tstmp_e1 : R/W; bitpos: [15:0]; default: 0;
* Configures generatorn timer stamp E1 value register
/** opn_tstmp_e : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM operator timestamp.
*/
uint32_t opn_tstmp_e1:16;
uint32_t opn_tstmp_e:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_opn_tstmp_e1_reg_t;
/** Type of opn_tstmp_e2 register
* Generatorn timer stamp E2 value register
*/
typedef union {
struct {
/** opn_tstmp_e2 : R/W; bitpos: [15:0]; default: 0;
* Configures generatorn timer stamp E2 value register
*/
uint32_t opn_tstmp_e2:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_opn_tstmp_e2_reg_t;
} mcpwm_opn_tstmp_reg_t;
/** Type of clk register
* Global configuration register
@@ -1614,65 +1445,35 @@ typedef union {
uint32_t val;
} mcpwm_clk_reg_t;
/** Type of timern_cfg2 register
* PWM timern timestamp a configuration register.
/** Type of timer_tstmp_cfg register
* PWM timern timestamp a configuration register. (unified type for array access)
*/
typedef union {
struct {
/** timern_a : R/W; bitpos: [15:0]; default: 255;
* Configures the timestamp a shadow of PWM timern
/** timern_tstmp : R/W; bitpos: [15:0]; default: 255;
* Configures the timestamp shadow of PWM timern
*/
uint32_t timern_a:16;
/** timern_a_upmethod : R/W; bitpos: [17:16]; default: 0;
* Configures the update method for active register of PWM timern timestamp a.
uint32_t timern_tstmp:16;
/** timern_upmethod : R/W; bitpos: [17:16]; default: 0;
* Configures the update method for active register of PWM timern timestamp.
* 0: Immediate
* 1: TEZ
* 2: Sync
* 3: TEZ or sync
* TEZ here and below means timer equal zero event
*/
uint32_t timern_a_upmethod:2;
/** timern_a_dir : R/W; bitpos: [18]; default: 0;
* Configures the direction of the timer when timern value equal a value for event
uint32_t timern_upmethod:2;
/** timern_dir : R/W; bitpos: [18]; default: 0;
* Configures the direction of the timer when timern value equal value for event
* trigger.
* 0: up
* 1: down
*/
uint32_t timern_a_dir:1;
uint32_t timern_dir:1;
uint32_t reserved_19:13;
};
uint32_t val;
} mcpwm_timern_cfg2_reg_t;
/** Type of timern_cfg3 register
* PWM timern timestamp b configuration register.
*/
typedef union {
struct {
/** timern_b : R/W; bitpos: [15:0]; default: 255;
* Configures the timestamp b shadow of PWM timern
*/
uint32_t timern_b:16;
/** timern_b_upmethod : R/W; bitpos: [17:16]; default: 0;
* Configures the update method for active register of PWM timern timestamp b.
* 0: Immediate
* 1: TEZ
* 2: Sync
* 3: TEZ or sync
* TEZ here and below means timer equal zero event
*/
uint32_t timern_b_upmethod:2;
/** timern_b_dir : R/W; bitpos: [18]; default: 0;
* Configures the direction of the timer when timern value equal b value for event
* trigger.
* 0: up
* 1: down
*/
uint32_t timern_b_dir:1;
uint32_t reserved_19:13;
};
uint32_t val;
} mcpwm_timern_cfg3_reg_t;
} mcpwm_timern_tstmp_cfg_reg_t;
/** Group: Status register */
@@ -2369,64 +2170,41 @@ typedef union {
uint32_t val;
} mcpwm_version_reg_t;
typedef struct {
volatile mcpwm_timern_cfg0_reg_t timern_cfg0;
volatile mcpwm_timern_cfg1_reg_t timern_cfg1;
volatile mcpwm_timern_sync_reg_t timern_sync;
volatile mcpwm_timern_status_reg_t timern_status;
} mcpwm_timer_regs_t;
typedef struct {
volatile mcpwm_timern_cfg0_reg_t timer0_cfg0;
volatile mcpwm_timern_cfg1_reg_t timer0_cfg1;
volatile mcpwm_timern_sync_reg_t timer0_sync;
volatile mcpwm_timern_status_reg_t timer0_status;
volatile mcpwm_timern_cfg0_reg_t timer1_cfg0;
volatile mcpwm_timern_cfg1_reg_t timer1_cfg1;
volatile mcpwm_timern_sync_reg_t timer1_sync;
volatile mcpwm_timern_status_reg_t timer1_status;
volatile mcpwm_timern_cfg0_reg_t timer2_cfg0;
volatile mcpwm_timern_cfg1_reg_t timer2_cfg1;
volatile mcpwm_timern_sync_reg_t timer2_sync;
volatile mcpwm_timern_status_reg_t timer2_status;
volatile mcpwm_genn_stmp_cfg_reg_t gen_stmp_cfg;
volatile mcpwm_genn_tstmp_reg_t timestamp[2];
volatile mcpwm_genn_cfg0_reg_t gen_cfg0;
volatile mcpwm_genn_force_reg_t gen_force;
volatile mcpwm_genn_reg_t generator[2];
volatile mcpwm_dtn_cfg_reg_t dt_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh_cfg1;
volatile mcpwm_fhn_status_reg_t fh_status;
} mcpwm_operator_reg_t;
typedef struct {
volatile mcpwm_opn_tstmp_reg_t timestamp[2];
} mcpwm_operator_tstmp_reg_t;
typedef struct {
volatile mcpwm_timern_tstmp_cfg_reg_t timer_tstmp_cfg[2];
} mcpwm_timer_tstmp_reg_t;
typedef struct mcpwm_dev_t {
volatile mcpwm_timer_regs_t timer[3];
volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
volatile mcpwm_operator_timersel_reg_t operator_timersel;
volatile mcpwm_genn_stmp_cfg_reg_t gen0_stmp_cfg;
volatile mcpwm_genn_tstmp_a_reg_t gen0_tstmp_a;
volatile mcpwm_genn_tstmp_b_reg_t gen0_tstmp_b;
volatile mcpwm_genn_cfg0_reg_t gen0_cfg0;
volatile mcpwm_genn_force_reg_t gen0_force;
volatile mcpwm_genn_a_reg_t gen0_a;
volatile mcpwm_genn_b_reg_t gen0_b;
volatile mcpwm_dtn_cfg_reg_t dt0_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt0_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt0_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier0_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh0_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh0_cfg1;
volatile mcpwm_fhn_status_reg_t fh0_status;
volatile mcpwm_genn_stmp_cfg_reg_t gen1_stmp_cfg;
volatile mcpwm_genn_tstmp_a_reg_t gen1_tstmp_a;
volatile mcpwm_genn_tstmp_b_reg_t gen1_tstmp_b;
volatile mcpwm_genn_cfg0_reg_t gen1_cfg0;
volatile mcpwm_genn_force_reg_t gen1_force;
volatile mcpwm_genn_a_reg_t gen1_a;
volatile mcpwm_genn_b_reg_t gen1_b;
volatile mcpwm_dtn_cfg_reg_t dt1_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt1_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt1_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier1_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh1_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh1_cfg1;
volatile mcpwm_fhn_status_reg_t fh1_status;
volatile mcpwm_genn_stmp_cfg_reg_t gen2_stmp_cfg;
volatile mcpwm_genn_tstmp_a_reg_t gen2_tstmp_a;
volatile mcpwm_genn_tstmp_b_reg_t gen2_tstmp_b;
volatile mcpwm_genn_cfg0_reg_t gen2_cfg0;
volatile mcpwm_genn_force_reg_t gen2_force;
volatile mcpwm_genn_a_reg_t gen2_a;
volatile mcpwm_genn_b_reg_t gen2_b;
volatile mcpwm_dtn_cfg_reg_t dt2_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt2_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt2_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier2_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh2_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh2_cfg1;
volatile mcpwm_fhn_status_reg_t fh2_status;
volatile mcpwm_operator_reg_t operators[3];
volatile mcpwm_fault_detect_reg_t fault_detect;
volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
@@ -2441,23 +2219,17 @@ typedef struct {
volatile mcpwm_evt_en_reg_t evt_en;
volatile mcpwm_task_en_reg_t task_en;
volatile mcpwm_evt_en2_reg_t evt_en2;
volatile mcpwm_opn_tstmp_e1_reg_t op0_tstmp_e1;
volatile mcpwm_opn_tstmp_e2_reg_t op0_tstmp_e2;
volatile mcpwm_opn_tstmp_e1_reg_t op1_tstmp_e1;
volatile mcpwm_opn_tstmp_e2_reg_t op1_tstmp_e2;
volatile mcpwm_opn_tstmp_e1_reg_t op2_tstmp_e1;
volatile mcpwm_opn_tstmp_e2_reg_t op2_tstmp_e2;
volatile mcpwm_operator_tstmp_reg_t operators_timestamp[3];
volatile mcpwm_clk_reg_t clk;
volatile mcpwm_version_reg_t version;
uint32_t reserved_148;
volatile mcpwm_timern_cfg2_reg_t timer0_cfg2;
volatile mcpwm_timern_cfg3_reg_t timer0_cfg3;
volatile mcpwm_timern_cfg2_reg_t timer1_cfg2;
volatile mcpwm_timern_cfg3_reg_t timer1_cfg3;
volatile mcpwm_timern_cfg2_reg_t timer2_cfg2;
volatile mcpwm_timern_cfg3_reg_t timer2_cfg3;
volatile mcpwm_timer_tstmp_reg_t timers_timestamp[3];
} mcpwm_dev_t;
extern mcpwm_dev_t MCPWM0;
extern mcpwm_dev_t MCPWM1;
extern mcpwm_dev_t MCPWM2;
extern mcpwm_dev_t MCPWM3;
#ifndef __cplusplus
_Static_assert(sizeof(mcpwm_dev_t) == 0x164, "Invalid size of mcpwm_dev_t structure");
docs/en/api-reference/peripherals/mcpwm.rst
+4 -4
View File
@@ -48,7 +48,7 @@ Description of the MCPWM functionality is divided into the following sections:
- :ref:`mcpwm-generator-force-actions` - describes how to control the generator output level asynchronously in a forceful way.
- :ref:`mcpwm-synchronization` - describes how to synchronize the MCPWM timers and get a fixed phase difference between the generated PWM signals.
- :ref:`mcpwm-capture` - describes how to use the MCPWM capture module to measure the pulse width of a signal.
:SOC_MCPWM_SUPPORT_ETM: - :ref:`mcpwm-etm-event-and-task` - describes what the events and tasks can be connected to the ETM channel.
:SOC_MCPWM_SUPPORT_ETM and SOC_ETM_SUPPORTED: - :ref:`mcpwm-etm-event-and-task` - describes what the events and tasks can be connected to the ETM channel.
- :ref:`mcpwm-power-management` - describes how different source clocks affects power consumption.
- :ref:`mcpwm-resolution-config` - describes the resolution configuration rules for the MCPWM submodule.
- :ref:`mcpwm-iram-safe` - describes tips on how to make the RMT interrupt work better along with a disabled cache.
@@ -121,7 +121,7 @@ The :cpp:func:`mcpwm_new_comparator` will return a pointer to the allocated comp
On the contrary, calling the :cpp:func:`mcpwm_del_comparator` function will free the allocated comparator object.
.. only:: SOC_MCPWM_SUPPORT_EVENT_COMPARATOR and SOC_MCPWM_SUPPORT_ETM
.. only:: SOC_MCPWM_SUPPORT_EVENT_COMPARATOR and SOC_MCPWM_SUPPORT_ETM and SOC_ETM_SUPPORTED
There's another kind of comparator called "Event Comparator", which **can not** control the final PWM directly but only generates the ETM events at a configurable time stamp. You can allocate an event comparator by calling the :cpp:func:`mcpwm_new_event_comparator` function. This function will return the same handle type as :cpp:func:`mcpwm_new_comparator`, but with a different configuration structure :cpp:type:`mcpwm_event_comparator_config_t`. For more information, please refer to :ref:`mcpwm-etm-event-and-task`.
@@ -953,7 +953,7 @@ Get the Last Captured Value
If you don't want to process the captured value in the capture event callback function, but want to process it in other places, you can call :cpp:func:`mcpwm_capture_get_latched_value` to get the last captured value.
.. only:: SOC_MCPWM_SUPPORT_ETM
.. only:: SOC_MCPWM_SUPPORT_ETM and SOC_ETM_SUPPORTED
.. _mcpwm-etm-event-and-task:
@@ -966,7 +966,7 @@ If you don't want to process the captured value in the capture event callback fu
.. _mcpwm-power-management:
.. only:: not SOC_MCPWM_SUPPORT_ETM
.. only:: not (SOC_MCPWM_SUPPORT_ETM and SOC_ETM_SUPPORTED)
.. _mcpwm-power-management:
docs/zh_CN/api-reference/peripherals/mcpwm.rst
+5 -4
View File
@@ -48,7 +48,7 @@ MCPWM 外设是一个多功能 PWM 生成器，集成多个子模块，在电力
- :ref:`mcpwm-generator-force-actions` - 介绍如何强制异步控制生成器的输出水平。
- :ref:`mcpwm-synchronization` - 介绍如何同步 MCPWM 定时器，并确保生成的最终输出 PWM 信号具有固定的相位差。
- :ref:`mcpwm-capture` - 介绍如何使用 MCPWM 捕获模块测量信号脉宽。
:SOC_MCPWM_SUPPORT_ETM: - :ref:`mcpwm-etm-event-and-task` - MCPWM 提供了哪些事件和任务可以连接到 ETM 通道上。
:SOC_MCPWM_SUPPORT_ETM and SOC_ETM_SUPPORTED: - :ref:`mcpwm-etm-event-and-task` - MCPWM 提供了哪些事件和任务可以连接到 ETM 通道上。
- :ref:`mcpwm-power-management` - 介绍不同的时钟源对功耗的影响。
- :ref:`mcpwm-resolution-config` - 介绍 MCPWM 子模块的分辨率配置规则。
- :ref:`mcpwm-iram-safe` - 介绍如何协调 RMT 中断与禁用缓存。
@@ -121,7 +121,7 @@ MCPWM 比较器
反之，调用 :cpp:func:`mcpwm_del_comparator` 函数将释放已分配的比较器。
.. only:: SOC_MCPWM_SUPPORT_EVENT_COMPARATOR and SOC_MCPWM_SUPPORT_ETM
.. only:: SOC_MCPWM_SUPPORT_EVENT_COMPARATOR and SOC_MCPWM_SUPPORT_ETM and SOC_ETM_SUPPORTED
MCPWM 中还有另外一种比较器 —— “事件比较器”，它不能直接控制 PWM 的输出，只能用来产生 EMT 子系统中使用到的事件。事件比较器能够设置的阈值也是可配的。调用 :cpp:func:`mcpwm_new_event_comparator` 函数可以申请一个事件比较器，该函数返回的句柄类型和 :cpp:func:`mcpwm_new_comparator` 函数一样，但是需要的配置结构体是不同的。事件比较器的配置位于 :cpp:type:`mcpwm_event_comparator_config_t`。更多相关内容请参阅 :ref:`mcpwm-etm-event-and-task`。
@@ -953,7 +953,7 @@ MCPWM 捕获通道支持在信号上检测到有效边沿时发送通知。须
如果不想在捕获事件回调函数中处理捕获值，而是想在其他地方处理，可以调用 :cpp:func:`mcpwm_capture_get_latched_value` 获得上一次锁存的捕获值。
.. only:: SOC_MCPWM_SUPPORT_ETM
.. only:: SOC_MCPWM_SUPPORT_ETM and SOC_ETM_SUPPORTED
.. _mcpwm-etm-event-and-task:
@@ -962,11 +962,12 @@ MCPWM 捕获通道支持在信号上检测到有效边沿时发送通知。须
MCPWM 的定时器和比较器可以产生事件，这些事件可以连接到 :doc:`ETM </api-reference/peripherals/etm>` 模块。:cpp:type:`mcpwm_timer_etm_event_type_t` 和 :cpp:type:`mcpwm_comparator_etm_event_type_t` 中分别列出了 MCPWM 定时器和比较器能够产生的事件类型。用户可以通过调用 :cpp:func:`mcpwm_timer_new_etm_event` 或 :cpp:func:`mcpwm_comparator_new_etm_event` 来获得相应事件的 ETM event 句柄。
关于如何将 MCPWM 事件连接到 ETM 通道中，请参阅 :doc:`ETM </api-reference/peripherals/etm>` 文档。
.. _mcpwm-power-management:
.. only:: not SOC_MCPWM_SUPPORT_ETM
.. only:: not (SOC_MCPWM_SUPPORT_ETM and SOC_ETM_SUPPORTED)
.. _mcpwm-power-management:
examples/peripherals/mcpwm/mcpwm_bldc_hall_control/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | --------- |
# MCPWM BLDC Motor Control with HALL Sensor Example
examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | --------- |
# HC-SR04 Example based on MCPWM Capture
examples/peripherals/mcpwm/mcpwm_foc_svpwm_open_loop/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | --------- |
# MCPWM FOC SVPWM Generation Open Loop Example
examples/peripherals/mcpwm/mcpwm_servo_control/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | --------- |
# MCPWM RC Servo Control Example
(See the README.md file in the upper level 'examples' directory for more information about examples.)
examples/peripherals/mcpwm/mcpwm_sync/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S3 | ESP32-S31 |
| ----------------- | ----- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | --------- |
# MCPWM Sync Example