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fix(mcpwm): fixed several errors on mcpwm

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This commit is contained in:
Chen Chen
2026-02-11 11:22:16 +08:00
parent 7f7f40404b
commit a7cd298f02
21 changed files with 65 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_driver_mcpwm/src/mcpwm_etm.c
+1 -1
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@@ -130,7 +130,7 @@ esp_err_t mcpwm_timer_new_etm_event(mcpwm_timer_handle_t timer, const mcpwm_time
portENTER_CRITICAL(&group->spinlock);
mcpwm_ll_etm_enable_timer_event(hal->dev, timer_id, config->event_type, true);
portEXIT_CRITICAL(&group->spinlock);
event_id = MCPWM_LL_TIMER_ETM_EVENT_TABLE(group_id, timer_id, config->event_type);
event_id = MCPWM_LL_ETM_TIMER_EVENT_TABLE(group_id, timer_id, config->event_type);
event->event_type = config->event_type;
ESP_GOTO_ON_FALSE(event_id != 0, ESP_ERR_NOT_SUPPORTED, err, TAG, "not supported event type");
ESP_LOGD(TAG, "MCPWM (%d) timer (%d) event_id (%"PRId32")", group_id, timer_id, event_id);
components/esp_hal_mcpwm/esp32c5/include/hal/mcpwm_ll.h
+1 -1
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@@ -71,7 +71,7 @@ extern "C" {
#define MCPWM_LL_BRAKE_MODE_TO_REG_VAL(mode) ((uint8_t[]) {0, 1}[(mode)])
// MCPWM ETM timer event table
#define MCPWM_LL_TIMER_ETM_EVENT_TABLE(group, timer_id, event) \
#define MCPWM_LL_ETM_TIMER_EVENT_TABLE(group, timer_id, event) \
(uint32_t[1][MCPWM_TIMER_ETM_EVENT_MAX]){{ \
[MCPWM_TIMER_ETM_EVENT_TEZ] = MCPWM0_EVT_TIMER0_TEZ + timer_id, \
[MCPWM_TIMER_ETM_EVENT_TEP] = MCPWM0_EVT_TIMER0_TEP + timer_id, \
components/esp_hal_mcpwm/esp32c5/mcpwm_periph.c
+1 -1
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@@ -84,7 +84,7 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
/**
* MCPWM Registers to be saved during sleep retention
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
components/esp_hal_mcpwm/esp32c6/include/hal/mcpwm_ll.h
+2 -1
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@@ -71,7 +71,8 @@ extern "C" {
#define MCPWM_LL_BRAKE_MODE_TO_REG_VAL(mode) ((uint8_t[]) {0, 1}[(mode)])
// MCPWM ETM timer event table
#define MCPWM_LL_TIMER_ETM_EVENT_TABLE(group, timer_id, event) \
// MCPWM ETM timer event table
#define MCPWM_LL_ETM_TIMER_EVENT_TABLE(group, timer_id, event) \
(uint32_t[1][MCPWM_TIMER_ETM_EVENT_MAX]){{ \
[MCPWM_TIMER_ETM_EVENT_TEZ] = MCPWM_EVT_TIMER0_TEZ + timer_id, \
[MCPWM_TIMER_ETM_EVENT_TEP] = MCPWM_EVT_TIMER0_TEP + timer_id, \
components/esp_hal_mcpwm/esp32c6/mcpwm_periph.c
+1 -1
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@@ -83,7 +83,7 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
/**
* MCPWM Registers to be saved during sleep retention
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
components/esp_hal_mcpwm/esp32h2/include/hal/mcpwm_ll.h
+2 -1
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@@ -69,7 +69,8 @@ extern "C" {
#define MCPWM_LL_BRAKE_MODE_TO_REG_VAL(mode) ((uint8_t[]) {0, 1}[(mode)])
// MCPWM ETM timer event table
#define MCPWM_LL_TIMER_ETM_EVENT_TABLE(group, timer_id, event) \
// MCPWM ETM timer event table
#define MCPWM_LL_ETM_TIMER_EVENT_TABLE(group, timer_id, event) \
(uint32_t[1][MCPWM_TIMER_ETM_EVENT_MAX]){{ \
[MCPWM_TIMER_ETM_EVENT_TEZ] = MCPWM_EVT_TIMER0_TEZ + timer_id, \
[MCPWM_TIMER_ETM_EVENT_TEP] = MCPWM_EVT_TIMER0_TEP + timer_id, \
components/esp_hal_mcpwm/esp32h2/mcpwm_periph.c
+1 -1
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@@ -82,7 +82,7 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
/**
* MCPWM Registers to be saved during sleep retention
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
components/esp_hal_mcpwm/esp32h21/include/hal/mcpwm_ll.h
+5 -1
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@@ -69,7 +69,8 @@ extern "C" {
#define MCPWM_LL_BRAKE_MODE_TO_REG_VAL(mode) ((uint8_t[]) {0, 1}[(mode)])
// MCPWM ETM timer event table
#define MCPWM_LL_TIMER_ETM_EVENT_TABLE(group, timer_id, event) \
// MCPWM ETM timer event table
#define MCPWM_LL_ETM_TIMER_EVENT_TABLE(group, timer_id, event) \
(uint32_t[1][MCPWM_TIMER_ETM_EVENT_MAX]){{ \
[MCPWM_TIMER_ETM_EVENT_TEZ] = MCPWM_EVT_TIMER0_TEZ + timer_id, \
[MCPWM_TIMER_ETM_EVENT_TEP] = MCPWM_EVT_TIMER0_TEP + timer_id, \
@@ -140,6 +141,9 @@ static inline void mcpwm_ll_group_set_clock_source(int group_id, soc_module_clk_
case SOC_MOD_CLK_XTAL:
PCR.pwm_clk_conf.pwm_clkm_sel = 0;
break;
case SOC_MOD_CLK_RC_FAST:
PCR.pwm_clk_conf.pwm_clkm_sel = 1;
break;
case SOC_MOD_CLK_PLL_F96M:
PCR.pwm_clk_conf.pwm_clkm_sel = 2;
break;
components/esp_hal_mcpwm/esp32h21/mcpwm_periph.c
+1 -1
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@@ -82,7 +82,7 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
/**
* MCPWM Registers to be saved during sleep retention
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
components/esp_hal_mcpwm/esp32h4/include/hal/mcpwm_ll.h
+1 -1
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@@ -71,7 +71,7 @@ extern "C" {
#define MCPWM_LL_BRAKE_MODE_TO_REG_VAL(mode) ((uint8_t[]) {0, 1}[(mode)])
// MCPWM ETM timer event table
#define MCPWM_LL_TIMER_ETM_EVENT_TABLE(group, timer_id, event) \
#define MCPWM_LL_ETM_TIMER_EVENT_TABLE(group, timer_id, event) \
(uint32_t[2][MCPWM_TIMER_ETM_EVENT_MAX]){ \
{ \
[MCPWM_TIMER_ETM_EVENT_TEZ] = MCPWM0_EVT_TIMER0_TEZ + timer_id, \
components/esp_hal_mcpwm/esp32h4/mcpwm_periph.c
+31 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -150,9 +150,10 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[2] = {
}
};
#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
/**
* MCPWM Registers to be saved during sleep retention
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG，MCPWM_TIMER0_SYNC_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG，MCPWM_TIMER0_SYNC_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
@@ -168,6 +169,8 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[2] = {
#define MCPWM_RETENTION_REGS_BASE(i) DR_REG_MCPWM_BASE(i)
static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0xff8c, 0x0};
static const regdma_entries_config_t mcpwm0_regdma_entries[] = {
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00),
MCPWM_RETENTION_REGS_BASE(0), MCPWM_RETENTION_REGS_BASE(0),
@@ -176,8 +179,21 @@ static const regdma_entries_config_t mcpwm0_regdma_entries[] = {
mcpwm_regs_map[2], mcpwm_regs_map[3]),
.owner = ENTRY(0) | ENTRY(2),
},
// restore stage: trigger a forced update of all active registers
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01),
MCPWM_UPDATE_CFG_REG(0), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2),
},
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02),
MCPWM_UPDATE_CFG_REG(0), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2),
},
};
static const regdma_entries_config_t mcpwm1_regdma_entries[] = {
// backup stage: save configuration registers
// restore stage: restore the configuration registers
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00),
MCPWM_RETENTION_REGS_BASE(1), MCPWM_RETENTION_REGS_BASE(1),
@@ -186,6 +202,17 @@ static const regdma_entries_config_t mcpwm1_regdma_entries[] = {
mcpwm_regs_map[2], mcpwm_regs_map[3]),
.owner = ENTRY(0) | ENTRY(2),
},
// restore stage: trigger a forced update of all active registers
[1] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x01),
MCPWM_UPDATE_CFG_REG(1), MCPWM_GLOBAL_FORCE_UP, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2),
},
[2] = {
.config = REGDMA_LINK_WRITE_INIT(REGDMA_MCPWM_LINK(0x02),
MCPWM_UPDATE_CFG_REG(1), 0, MCPWM_GLOBAL_FORCE_UP_M, 1, 0),
.owner = ENTRY(0) | ENTRY(2),
},
};
const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[2] = {
@@ -195,8 +222,9 @@ const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[2] = {
.retention_module = SLEEP_RETENTION_MODULE_MCPWM0
},
[1] = {
.regdma_entry_array = mcpwm0_regdma_entries,
.regdma_entry_array = mcpwm1_regdma_entries,
.array_size = ARRAY_SIZE(mcpwm1_regdma_entries),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM1
},
};
#endif // SOC_MCPWM_SUPPORT_SLEEP_RETENTION
components/esp_hal_mcpwm/esp32p4/include/hal/mcpwm_ll.h
+2 -1
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@@ -72,7 +72,8 @@ extern "C" {
#define MCPWM_LL_GEN_ACTION_TO_REG_CAL(action) ((uint8_t[]) {0, 1, 2, 3}[(action)])
#define MCPWM_LL_BRAKE_MODE_TO_REG_VAL(mode) ((uint8_t[]) {0, 1}[(mode)])
#define MCPWM_LL_TIMER_ETM_EVENT_TABLE(group, timer_id, event) \
// MCPWM ETM timer event table
#define MCPWM_LL_ETM_TIMER_EVENT_TABLE(group, timer_id, event) \
(uint32_t[2][MCPWM_TIMER_ETM_EVENT_MAX]){ \
{ \
[MCPWM_TIMER_ETM_EVENT_TEZ] = MCPWM0_EVT_TIMER0_TEZ + timer_id, \
components/esp_hal_mcpwm/esp32p4/mcpwm_periph.c
+1 -1
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@@ -153,7 +153,7 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[2] = {
#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
/**
* MCPWM Registers to be saved during sleep retention
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
components/soc/esp32c5/include/soc/soc.h
-1
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@@ -21,7 +21,6 @@
#define REG_TIMG_BASE(i) (DR_REG_TIMERG0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_SPIMEM0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_I2C_BASE(i) (DR_REG_I2C_BASE) // only one I2C on C5
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C5
#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1
//Registers Operation {{
components/soc/esp32c5/register/soc/mcpwm_reg.h
+2
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@@ -11,6 +11,8 @@
extern "C" {
#endif
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE)
/** MCPWM_CLK_CFG_REG register
* PWM clock prescaler register.
*/
components/soc/esp32c6/include/soc/soc.h
-1
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@@ -24,7 +24,6 @@
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C6
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C6
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C6
#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1
//Registers Operation {{
components/soc/esp32c6/register/soc/mcpwm_reg.h
+2
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@@ -11,6 +11,8 @@
extern "C" {
#endif
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE)
/** MCPWM_CLK_CFG_REG register
* PWM clock prescaler register.
*/
components/soc/esp32h21/include/soc/clk_tree_defs.h
+7 -4
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -282,13 +282,14 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of MCPWM Timer
*/
#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL}
#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM timer clock source
*/
typedef enum {
MCPWM_TIMER_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
MCPWM_TIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
} soc_periph_mcpwm_timer_clk_src_t;
@@ -296,13 +297,14 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of MCPWM Capture Timer
*/
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL}
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM capture clock source
*/
typedef enum {
MCPWM_CAPTURE_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
MCPWM_CAPTURE_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
} soc_periph_mcpwm_capture_clk_src_t;
@@ -310,13 +312,14 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of MCPWM Carrier
*/
#define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_XTAL}
#define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM carrier clock source
*/
typedef enum {
MCPWM_CARRIER_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
MCPWM_CARRIER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
} soc_periph_mcpwm_carrier_clk_src_t;
components/soc/esp32p4/include/soc/soc.h
-1
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@@ -22,7 +22,6 @@
#define REG_SPI_MEM_BASE(i) (DR_REG_FLASH_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3
#define REG_I2C_BASE(i) (DR_REG_I2C0_BASE + (i) * 0x1000)
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE + (i) * 0x1000)
#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x1000) // TWAI0 and TWAI1
//Registers Operation {{
components/soc/esp32p4/register/hw_ver1/soc/mcpwm_reg.h
+2
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@@ -11,6 +11,8 @@
extern "C" {
#endif
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE + (i) * 0x1000)
/** MCPWM_CLK_CFG_REG register
* PWM clock prescaler register.
*/
components/soc/esp32p4/register/hw_ver3/soc/mcpwm_reg.h
+2
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@@ -11,6 +11,8 @@
extern "C" {
#endif
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE + (i) * 0x1000)
/** MCPWM_CLK_CFG_REG register
* PWM clock prescaler register.
*/