espressif/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-04-27 19:13:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

fix(interrupts): cleanup leftover todo from H4 bringup

Browse Source
This commit is contained in:
Marius Vikhammer
2026-04-17 16:41:52 +08:00
parent 96a8cdff23
commit 6879cec1f3
5 changed files with 2 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/soc/esp32h4/include/soc/clic_reg.h
-2
View File
@@ -10,8 +10,6 @@
extern "C" {
#endif
//TODO: [ESP32H4] IDF-12303
#define NLBITS 3
#define CLIC_EXT_INTR_NUM_OFFSET 16
#define DUALCORE_CLIC_CTRL_OFF 0x10000
components/soc/esp32h4/include/soc/clint_reg.h
-2
View File
@@ -10,8 +10,6 @@
extern "C" {
#endif
//TODO: [ESP32H4] IDF-12303
/*CLINT MINT*/
#define CLINT_MINT_SIP_REG (DR_REG_CLINT_M_BASE + 0x0)
/* CLINT_CPU_MINT_SIP : R/W ;bitpos:[0] ;default: 1'b0 ; */
components/soc/esp32h4/include/soc/interrupt_reg.h
-2
View File
@@ -8,8 +8,6 @@
#include "soc/clic_reg.h"
#include "soc/soc_caps.h"
// TODO: [ESP32H4] IDF-12303 inherit from verify code, need check
#define INTERRUPT_CURRENT_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG)
#define INTERRUPT_OTHER_CORE_INT_THRESH_REG (CLIC_INT_THRESH_REG + DUALCORE_CLIC_CTRL_OFF)
components/soc/esp32h4/include/soc/reg_base.h
+1 -1
View File
@@ -76,7 +76,7 @@
#define DR_REG_TOUCH_SENS_BASE 0x600B5800
#define DR_REG_TOUCH_AON_BASE 0x600B5C00
#define DR_REG_CLINT_M_BASE 0x20000000 // TODO: [ESP32H4] IDF-12303 inherit from verify code, need check
#define DR_REG_CLINT_M_BASE 0x20000000
#define IEEE802154_REG_BASE 0x600C3000
#define PWDET_CONF_REG 0x600C0808
components/soc/esp32h4/include/soc/soc.h
+1 -1
View File
@@ -150,7 +150,7 @@
#define SOC_IRAM_HIGH 0x40860000
#define SOC_DRAM_LOW 0x40810000
#define SOC_DRAM_HIGH 0x40860000
#define SOC_RTC_IRAM_LOW 0x50000000 // TODO：[ESP32H4] IDF-12303 inherit from verify code, need remove
#define SOC_RTC_IRAM_LOW 0x50000000
#define SOC_RTC_IRAM_HIGH 0x50004000
#define SOC_RTC_DRAM_LOW 0x50000000
#define SOC_RTC_DRAM_HIGH 0x50004000