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fix(esp_hw_support): fix LP core exception interrupt not being cleared

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This commit is contained in:
hebinglin
2026-04-21 15:25:00 +08:00
parent b8e0ee431c
commit 6ce373ccfb
5 changed files with 24 additions and 3 deletions
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components/esp_hal_pmu/esp32c5/include/hal/pmu_ll.h
+6 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -519,6 +519,11 @@ FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw)
hw->hp_ext.int_clr.reject = 1;
}
FORCE_INLINE_ATTR void pmu_ll_hp_clear_lp_cpu_exc_intr_status(pmu_dev_t *hw)
{
hw->hp_ext.int_clr.lp_cpu_exc = 1;
}
FORCE_INLINE_ATTR void pmu_ll_hp_enable_sw_intr(pmu_dev_t *hw, bool enable)
{
hw->hp_ext.int_ena.sw = enable;
components/esp_hal_pmu/esp32c6/include/hal/pmu_ll.h
+6 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -519,6 +519,11 @@ FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw)
hw->hp_ext.int_clr.reject = 1;
}
FORCE_INLINE_ATTR void pmu_ll_hp_clear_lp_cpu_exc_intr_status(pmu_dev_t *hw)
{
hw->hp_ext.int_clr.lp_cpu_exc = 1;
}
FORCE_INLINE_ATTR void pmu_ll_hp_enable_sw_intr(pmu_dev_t *hw, bool enable)
{
hw->hp_ext.int_ena.sw = enable;
components/esp_hal_pmu/esp32p4/include/hal/pmu_ll.h
+6 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -567,6 +567,11 @@ FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw)
hw->hp_ext.int_clr.reject = 1;
}
FORCE_INLINE_ATTR void pmu_ll_hp_clear_lp_cpu_exc_intr_status(pmu_dev_t *hw)
{
hw->hp_ext.int_clr.lp_exception = 1;
}
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_wakeup_cause(pmu_dev_t *hw)
{
return hw->wakeup.status0;
components/esp_hal_pmu/esp32s31/include/hal/pmu_ll.h
+5
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@@ -595,6 +595,11 @@ FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw)
hw->hp_ext.int_clr.soc_sleep_reject = 1;
}
FORCE_INLINE_ATTR void pmu_ll_hp_clear_lp_cpu_exc_intr_status(pmu_dev_t *hw)
{
hw->hp_ext.int_clr.lp_cpu_exc = 1;
}
FORCE_INLINE_ATTR void pmu_ll_hp_enable_sw_intr(pmu_dev_t *hw, bool enable)
{
hw->hp_ext.int_ena.sw = enable;
components/esp_hw_support/sleep_modes.c
+1
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@@ -1101,6 +1101,7 @@ static esp_err_t SLEEP_FN_ATTR esp_sleep_start(uint32_t sleep_flags, uint32_t cl
#if CONFIG_ULP_COPROC_TYPE_LP_CORE
if (s_config.wakeup_triggers & (RTC_LP_CORE_TRIG_EN | RTC_LP_CORE_TRAP_TRIG_EN)) {
pmu_ll_hp_clear_sw_intr_status(&PMU);
pmu_ll_hp_clear_lp_cpu_exc_intr_status(&PMU);
}
#endif
#endif // CONFIG_ULP_COPROC_ENABLED