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https://github.com/espressif/esp-idf.git
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feat(regi2c): add test app for esp_hal_regi2c component
This commit is contained in:
Song Ruo Jing
@@ -0,0 +1,9 @@
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components/esp_hal_regi2c/test_apps:
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enable:
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- if: INCLUDE_DEFAULT == 1
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disable:
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- if: IDF_TARGET in ["esp32s31"]
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temporary: true
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reason: not support yet # TODO: [ESP32S31] IDF-14680
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depends_components:
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- esp_hal_regi2c
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@@ -0,0 +1,6 @@
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# The following lines of boilerplate have to be in your project's
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# CMakeLists in this exact order for cmake to work correctly
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cmake_minimum_required(VERSION 3.22)
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include($ENV{IDF_PATH}/tools/cmake/project.cmake)
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project(test_regi2c)
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| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
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| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
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@@ -0,0 +1,8 @@
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set(srcs "test_app_main.c"
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"test_regi2c.c")
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# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
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# the component can be registered as WHOLE_ARCHIVE
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idf_component_register(SRCS ${srcs}
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INCLUDE_DIRS "."
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WHOLE_ARCHIVE)
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@@ -0,0 +1,37 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "unity.h"
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#include "unity_test_runner.h"
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#include "esp_heap_caps.h"
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#include "esp_newlib.h"
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#include "unity_test_utils.h"
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// Some resources are lazy allocated in the driver, the threshold is left for that case
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#define TEST_MEMORY_LEAK_THRESHOLD (0)
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void setUp(void)
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{
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unity_utils_record_free_mem();
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}
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void tearDown(void)
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{
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esp_reent_cleanup(); //clean up some of the newlib's lazy allocations
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unity_utils_evaluate_leaks_direct(TEST_MEMORY_LEAK_THRESHOLD);
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}
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void app_main(void)
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{
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printf(" _ ____ \n");
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printf(" _ __ ___ __ _(_)___ \\ ___ \n");
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printf(" | '__/ _ \\/ _` | | __) / __| \n");
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printf(" | | | __/ (_| | |/ __/ (__ \n");
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printf(" |_| \\___|\\__, |_|_____\\___| \n");
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printf(" |___/ \n");
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unity_run_menu();
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}
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@@ -0,0 +1,91 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include <stdint.h>
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#include "unity.h"
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#include "test_regi2c.h"
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#include "esp_private/regi2c_ctrl.h"
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TEST_CASE("regi2c basic read/write test", "[regi2c]")
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{
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#if CONFIG_IDF_TARGET_ESP32
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// For ESP32, we need to enable the APLL clock before accessing the APLL regi2c registers
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periph_rtc_apll_acquire();
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#endif
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/* ---- Part 1: full-register read / write ---- */
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printf("Test regi2c read/write: block=0x%02X host=%d reg=%d\n",
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TEST_BLOCK, TEST_HOST_ID, TEST_REG_FULL);
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uint8_t orig_full = regi2c_ctrl_read_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_FULL);
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printf(" Original value: 0x%02X\n", orig_full);
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const uint8_t patterns[] = {0xA5, 0x5A, 0xFF, 0x00};
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for (size_t i = 0; i < sizeof(patterns) / sizeof(patterns[0]); i++) {
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regi2c_ctrl_write_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_FULL, patterns[i]);
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uint8_t rb = regi2c_ctrl_read_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_FULL);
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printf(" Write 0x%02X -> Read 0x%02X\n", patterns[i], rb);
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TEST_ASSERT_EQUAL_HEX8(patterns[i], rb);
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}
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/* ---- Part 2: masked read / write ---- */
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const uint8_t field_width = TEST_REG_MASK_MSB - TEST_REG_MASK_LSB + 1;
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const uint8_t field_max = (uint8_t)((1U << field_width) - 1);
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const uint8_t reg_mask = (uint8_t)(field_max << TEST_REG_MASK_LSB);
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printf("Test regi2c read_mask/write_mask: block=0x%02X host=%d reg=%d bits[%d:%d]\n",
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TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK,
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TEST_REG_MASK_MSB, TEST_REG_MASK_LSB);
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uint8_t orig_mask = regi2c_ctrl_read_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK);
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printf(" Original full reg value: 0x%02X\n", orig_mask);
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/* Write all-ones to masked field */
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regi2c_ctrl_write_reg_mask(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK,
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TEST_REG_MASK_MSB, TEST_REG_MASK_LSB, field_max);
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uint8_t mval = regi2c_ctrl_read_reg_mask(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK,
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TEST_REG_MASK_MSB, TEST_REG_MASK_LSB);
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printf(" write_mask(0x%02X) -> read_mask=0x%02X\n", field_max, mval);
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TEST_ASSERT_EQUAL_HEX8(field_max, mval);
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uint8_t full = regi2c_ctrl_read_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK);
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TEST_ASSERT_EQUAL_HEX8(orig_mask & (uint8_t)(~reg_mask), full & (uint8_t)(~reg_mask));
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/* Write all-zeros to masked field */
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regi2c_ctrl_write_reg_mask(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK,
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TEST_REG_MASK_MSB, TEST_REG_MASK_LSB, 0x00);
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mval = regi2c_ctrl_read_reg_mask(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK,
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TEST_REG_MASK_MSB, TEST_REG_MASK_LSB);
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printf(" write_mask(0x00) -> read_mask=0x%02X\n", mval);
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TEST_ASSERT_EQUAL_HEX8(0x00, mval);
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full = regi2c_ctrl_read_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK);
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TEST_ASSERT_EQUAL_HEX8(orig_mask & (uint8_t)(~reg_mask), full & (uint8_t)(~reg_mask));
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/* Write a mid-range value */
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uint8_t mid = field_max >> 1;
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if (mid == 0 && field_max > 0) {
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mid = 1;
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}
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regi2c_ctrl_write_reg_mask(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK,
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TEST_REG_MASK_MSB, TEST_REG_MASK_LSB, mid);
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mval = regi2c_ctrl_read_reg_mask(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK,
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TEST_REG_MASK_MSB, TEST_REG_MASK_LSB);
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printf(" write_mask(0x%02X) -> read_mask=0x%02X\n", mid, mval);
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TEST_ASSERT_EQUAL_HEX8(mid, mval);
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/* Restore all modified registers to their original values */
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regi2c_ctrl_write_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_FULL, orig_full);
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TEST_ASSERT_EQUAL_HEX8(orig_full,
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regi2c_ctrl_read_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_FULL));
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regi2c_ctrl_write_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK, orig_mask);
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TEST_ASSERT_EQUAL_HEX8(orig_mask,
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regi2c_ctrl_read_reg(TEST_BLOCK, TEST_HOST_ID, TEST_REG_MASK));
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#if CONFIG_IDF_TARGET_ESP32
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// Disable APLL clock
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periph_rtc_apll_release();
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#endif
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}
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@@ -0,0 +1,84 @@
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/*
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* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "sdkconfig.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* Target-specific regi2c test configuration
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*
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* For ESP32: test with the APLL regi2c block (I2C_APLL)
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* For other targets: test with the SAR ADC calibration regi2c block (I2C_SAR_ADC / I2C_SARADC)
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*
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* Each target configuration selects:
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* - A full 8-bit register for testing read/write
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* - A partial bit-field register for testing read_mask/write_mask
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*/
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#if CONFIG_IDF_TARGET_ESP32
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#include "clk_ctrl_os.h"
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#include "soc/regi2c_apll.h"
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#define TEST_BLOCK I2C_APLL
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#define TEST_HOST_ID I2C_APLL_HOSTID
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/* I2C_APLL_DSDM0: register 9, bits [7:0] — full 8-bit SDM parameter */
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#define TEST_REG_FULL I2C_APLL_DSDM0
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/* I2C_APLL_OC_DVDD: register 6, bits [4:0] — 5-bit output voltage divider */
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#define TEST_REG_MASK I2C_APLL_OC_DVDD
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#define TEST_REG_MASK_MSB I2C_APLL_OC_DVDD_MSB
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#define TEST_REG_MASK_LSB I2C_APLL_OC_DVDD_LSB
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#elif CONFIG_IDF_TARGET_ESP32H4
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#include "soc/regi2c_saradc.h"
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#define TEST_BLOCK I2C_SARADC
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#define TEST_HOST_ID I2C_SARADC_HOSTID
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/* I2C_SARADC_SAR1_INIT_CODE_LSB: register 0, bits [7:0] — full 8-bit */
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#define TEST_REG_FULL I2C_SARADC_SAR1_INIT_CODE_LSB
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/* I2C_SARADC_SAR1_INIT_CODE_MSB: register 1, bits [3:0] — 4-bit field */
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#define TEST_REG_MASK I2C_SARADC_SAR1_INIT_CODE_MSB
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#define TEST_REG_MASK_MSB I2C_SARADC_SAR1_INIT_CODE_MSB_MSB
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#define TEST_REG_MASK_LSB I2C_SARADC_SAR1_INIT_CODE_MSB_LSB
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#elif CONFIG_IDF_TARGET_ESP32H21 // TODO: IDF-11590 Replace with standard SARADC register field macros once they are defined in esp32h21/regi2c_saradc.h
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#include "soc/regi2c_saradc.h"
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#define TEST_BLOCK I2C_SAR_ADC
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#define TEST_HOST_ID I2C_SAR_ADC_HOSTID
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/*
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* ESP32-H21 regi2c_saradc.h only defines block and host ID without individual
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* register field macros. Use the standard SARADC register layout directly:
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* register 0 bits [7:0] = SAR1 initial code low byte
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* register 1 bits [3:0] = SAR1 initial code high nibble
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*/
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#define TEST_REG_FULL 0
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#define TEST_REG_MASK 1
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#define TEST_REG_MASK_MSB 3
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#define TEST_REG_MASK_LSB 0
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#else
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/* Standard SARADC register naming */
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#include "soc/regi2c_saradc.h"
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#define TEST_BLOCK I2C_SAR_ADC
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#define TEST_HOST_ID I2C_SAR_ADC_HOSTID
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/* ADC_SAR1_INITIAL_CODE_LOW_ADDR: register 0x0, bits [7:0] — full 8-bit */
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#define TEST_REG_FULL ADC_SAR1_INITIAL_CODE_LOW_ADDR
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/* ADC_SAR1_DREF_ADDR: register 0x2, bits [6:4] — 3-bit reference voltage */
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#define TEST_REG_MASK ADC_SAR1_DREF_ADDR
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#define TEST_REG_MASK_MSB ADC_SAR1_DREF_ADDR_MSB
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#define TEST_REG_MASK_LSB ADC_SAR1_DREF_ADDR_LSB
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#endif
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#ifdef __cplusplus
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}
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#endif
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@@ -0,0 +1,16 @@
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# SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
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# SPDX-License-Identifier: Apache-2.0
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import pytest
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from pytest_embedded import Dut
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from pytest_embedded_idf.utils import idf_parametrize
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@pytest.mark.generic
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@pytest.mark.parametrize(
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'config',
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['default'],
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indirect=True,
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)
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@idf_parametrize('target', ['supported_targets'], indirect=['target'])
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def test_regi2c(dut: Dut) -> None:
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dut.run_all_single_board_cases()
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@@ -0,0 +1,2 @@
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CONFIG_FREERTOS_HZ=1000
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CONFIG_ESP_TASK_WDT_EN=n
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