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feat(ble): support ble on esp32s31

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This commit is contained in:
cjin
2026-04-12 18:45:14 +08:00
committed by Wang Mengyang
parent 11268d8bfb
commit 6f7eec029b
110 changed files with 287 additions and 1901 deletions
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components/bt/common/ble_log/deprecated/ble_log_spi_out.c
+9 -3
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -98,7 +98,13 @@ static_assert(false, "BLE Log SPI Out: Unsupported target architecture");
SPI_OUT_MESH_QUEUE_SIZE)
#if SPI_OUT_LL_ENABLED && CONFIG_SOC_ESP_NIMBLE_CONTROLLER
#if CONFIG_BT_DUAL_MODE_ARCH
#include "ble_mbuf.h"
#define BLE_MBUF_COPY ble_mbuf_copydata
#else
#include "os/os_mbuf.h"
#define BLE_MBUF_COPY os_mbuf_copydata
#endif // CONFIG_BT_DUAL_MODE_ARCH
#endif /* SPI_OUT_LL_ENABLED && CONFIG_SOC_ESP_NIMBLE_CONTROLLER */
// Private typedefs
@@ -613,8 +619,8 @@ IRAM_ATTR static bool spi_out_log_cb_write(spi_out_log_cb_t *log_cb, const uint8
if (len_append && addr_append) {
#if SPI_OUT_LL_ENABLED && CONFIG_SOC_ESP_NIMBLE_CONTROLLER
if (omdata) {
os_mbuf_copydata((struct os_mbuf *)addr_append, 0,
len_append, buf + SPI_OUT_FRAME_HEAD_LEN + len);
BLE_MBUF_COPY((struct ble_mbuf *)addr_append, 0,
len_append, buf + SPI_OUT_FRAME_HEAD_LEN + len);
}
else
#endif /* SPI_OUT_LL_ENABLED && CONFIG_SOC_ESP_NIMBLE_CONTROLLER */
components/bt/common/ble_log/src/ble_log_lbm.c
+8 -2
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@@ -13,7 +13,13 @@
#include "ble_log_rt.h"
#if CONFIG_SOC_ESP_NIMBLE_CONTROLLER
#if CONFIG_BT_DUAL_MODE_ARCH
#include "ble_mbuf.h"
#define BLE_MBUF_COPY ble_mbuf_copydata
#else
#include "os/os_mbuf.h"
#define BLE_MBUF_COPY os_mbuf_copydata
#endif // CONFIG_BT_DUAL_MODE_ARCH
#endif /* CONFIG_SOC_ESP_NIMBLE_CONTROLLER */
/* VARIABLE */
@@ -133,8 +139,8 @@ void ble_log_lbm_write_trans(ble_log_prph_trans_t **trans, ble_log_src_t src_cod
if (len_append) {
#if CONFIG_SOC_ESP_NIMBLE_CONTROLLER
if (omdata) {
os_mbuf_copydata((struct os_mbuf *)addr_append, 0,
len_append, buf + BLE_LOG_FRAME_HEAD_LEN + len);
BLE_MBUF_COPY((struct ble_mbuf *)addr_append, 0,
len_append, buf + SPI_OUT_FRAME_HEAD_LEN + len);
}
else
#endif /* CONFIG_SOC_ESP_NIMBLE_CONTROLLER */
components/bt/controller/esp32s31/Kconfig.in
-1
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@@ -3,4 +3,3 @@ source "$IDF_PATH/components/bt/porting_btdm/Kconfig.in"
config BT_CTRL_MULTI_LINK_ENABLED
bool
default y
components/bt/controller/esp32s31/ble.c
-1642
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File diff suppressed because it is too large Load Diff
components/bt/controller/esp32s31/bt.c
+2
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@@ -36,6 +36,8 @@
#if UC_BT_CTRL_UART_HCI_DMA_MODE
#define BT_HCI_TRANSPORT_MODE HCI_TRANSPORT_UART_UHCI
#endif // UC_BT_CTRL_UART_HCI_DMA_MODE
#else
#error "Unknown HCI transport mode!!"
#endif // UC_BT_CTRL_HCI_INTERFACE_USE_RAM
/*
components/bt/porting_btdm/Kconfig.in
-5
View File
@@ -27,11 +27,6 @@ config BT_CTRL_TASK_STACK_SIZE
help
This configures stack size of NimBLE controller task
config BT_CTRL_MULTI_LINK_ENABLED
depends on SOC_BT_MULTI_LINK_SUPPORTED
bool "Enable multi-link mode"
default y
config BT_CTRL_SLEEP_ENABLE
bool "Enable Bluetooth Controller sleep"
default n
components/bt/porting_btdm/controller/ble/src/ble.c
-14
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@@ -1502,21 +1502,11 @@ int ble_stack_init(esp_bt_controller_config_t *cfg)
}
#endif // CONFIG_BT_LE_ISO_SUPPORT
#if CONFIG_SW_COEXIST_ENABLE
// Should be invoked in ble ?
extern int r_bt_rf_coex_env_init(void);
r_bt_rf_coex_env_init();
#endif /* CONFIG_SW_COEXIST_ENABLE */
return 0;
}
void ble_stack_deinit(void)
{
#if CONFIG_SW_COEXIST_ENABLE
extern void r_bt_rf_coex_env_deinit(void);
r_bt_rf_coex_env_deinit();
#endif /* CONFIG_SW_COEXIST_ENABLE */
#if CONFIG_BT_LE_ISO_SUPPORT
iso_stack_deinitEnv();
#endif // CONFIG_BT_LE_ISO_SUPPORT
@@ -1578,10 +1568,6 @@ int ble_stack_enable(void)
#endif // BT_LE_ISO_SUPPORT
#if CONFIG_SW_COEXIST_ENABLE
extern int r_bt_rf_coex_env_enable(void);
r_bt_rf_coex_env_enable();
#endif /* CONFIG_SW_COEXIST_ENABLE */
return 0;
}
components/bt/porting_btdm/controller/btdm_common/include/btdm_lp.h
+10
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@@ -5,6 +5,7 @@
*/
#ifndef _BTDM_LP_H_
#define _BTDM_LP_H_
#include "esp_private/esp_modem_clock.h"
void btdm_lp_enable_clock(esp_btdm_controller_config_t *cfg);
@@ -18,4 +19,13 @@ void btdm_lp_reset(bool enable_stage);
void btdm_lp_shutdown(void);
modem_clock_lpclk_src_t btdm_lp_get_lpclk_src(void);
void btdm_lp_set_lpclk_src(modem_clock_lpclk_src_t clk_src);
uint32_t btdm_lp_get_lpclk_freq(void);
void btdm_lp_set_lpclk_freq(uint32_t clk_freq);
#endif
components/bt/porting_btdm/controller/btdm_common/include/btdm_osal.h
+2 -2
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@@ -142,11 +142,11 @@ int wr_btdm_osal_intr_free(btdm_osal_intr_handle_t intr_handle);
void *wr_btdm_osal_malloc(uint32_t size, btdm_osal_malloc_flag_t flags);
void wr_btdm_osal_free(void *ptr);
#if !CONFIG_BTDM_CTRL_MULTI_LINK_ENABLED
#if !CONFIG_BT_CTRL_MULTI_LINK_ENABLED
void *wr_btdm_osal_mmgmt_block_malloc(uint32_t size);
void wr_btdm_osal_mmgmt_block_free(void *ptr);
void wr_btdm_osal_mmgmt_block_copy(void *dst, const void *src, uint16_t size);
#endif /* !CONFIG_BTDM_CTRL_MULTI_LINK_ENABLED */
#endif /* !CONFIG_BT_CTRL_MULTI_LINK_ENABLED */
// void * wr_btdm_osal_ets_delay_us(uint32_t us);
int wr_btdm_osal_read_efuse_mac(uint8_t *mac);
components/bt/porting_btdm/controller/btdm_common/src/btdm_lp.c
+13 -24
View File
@@ -24,6 +24,7 @@
#include "esp_private/sleep_modem.h"
#include "esp_private/sleep_retention.h"
#endif
#include "soc/rtc.h"
#if CONFIG_IDF_TARGET_ESP32S31
// TODO: remove this include after use of HP_SYS_CLKRST_MODEM_CONF_REG is removed
@@ -55,7 +56,7 @@ extern esp_err_t sleep_modem_bredr_mac_modem_state_init(void);
extern esp_err_t sleep_modem_ble_mac_modem_state_init(void);
#endif // UC_BT_CTRL_BLE_IS_ENABLEs
#endif /* CONFIG_FREERTOS_USE_TICKLESS_IDLE */
extern int r_btdm_hal_rtc_freq_set(uint64_t rtc_freq);
extern void r_btdm_sleep_set_sleep_cb(void *s_cb, void *w_cb, void *s_arg, void *w_arg,
uint32_t us_to_enabled);
@@ -70,8 +71,8 @@ static DRAM_ATTR modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_
#ifdef CONFIG_PM_ENABLE
static DRAM_ATTR esp_pm_lock_handle_t s_pm_lock = NULL;
#endif // CONFIG_PM_ENABLE
// static modem_clock_lpclk_src_t s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_INVALID;
static uint32_t s_bt_lpclk_freq = 100000;
static uint32_t s_bt_xtal_lpclk_freq = 100000;
static uint32_t s_bt_lpclk_freq = 0;
/*
***************************************************************************************************
@@ -85,7 +86,7 @@ btdm_lp_rtc_slow_clk_select(uint8_t slow_clk_src)
switch (slow_clk_src) {
case MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL:
ESP_LOGI(BTDM_LOG_TAG, "Using main XTAL as clock source");
modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (CONFIG_XTAL_FREQ * 1000000 / s_bt_lpclk_freq - 1));
modem_clock_select_lp_clock_source(PERIPH_BT_MODULE, slow_clk_src, (CONFIG_XTAL_FREQ * 1000000 / s_bt_xtal_lpclk_freq - 1));
break;
case MODEM_CLOCK_LPCLK_SRC_RC_SLOW:
ESP_LOGW(BTDM_LOG_TAG, "Using 136 kHz RC as clock source, use with caution as it may not maintain ACL or Sync process due to low clock accuracy!");
@@ -113,9 +114,11 @@ btdm_lp_timer_clk_init(esp_btdm_controller_config_t *cfg)
if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_INVALID) {
#if CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
s_bt_lpclk_freq = s_bt_xtal_lpclk_freq;
#else
#if CONFIG_RTC_CLK_SRC_INT_RC
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC_SLOW;
s_bt_lpclk_freq = esp_clk_tree_lp_slow_get_freq_hz(ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED) / 5;
#elif CONFIG_RTC_CLK_SRC_EXT_CRYS
uint32_t clk_freq = 0;
if ((rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_XTAL32K) &&
@@ -124,13 +127,16 @@ btdm_lp_timer_clk_init(esp_btdm_controller_config_t *cfg)
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_XTAL32K;
s_bt_lpclk_freq = 32768;
} else {
ESP_LOGW(BTDM_LOG_TAG, "32.768kHz XTAL not detected, fall back to main XTAL as Bluetooth sleep clock");
ESP_LOGW(BTDM_LOG_TAG, "32.768kHz XTAL detection error, switch to main XTAL as Bluetooth sleep clock");
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL;
s_bt_lpclk_freq = s_bt_xtal_lpclk_freq;
}
#elif CONFIG_RTC_CLK_SRC_INT_RC32K
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_RC32K;
s_bt_lpclk_freq = 32000;
#elif CONFIG_RTC_CLK_SRC_EXT_OSC
s_bt_lpclk_src = MODEM_CLOCK_LPCLK_SRC_EXT32K;
s_bt_lpclk_freq = 32000;
#else
ESP_LOGE(BTDM_LOG_TAG, "Unsupported clock source");
assert(0);
@@ -138,19 +144,6 @@ btdm_lp_timer_clk_init(esp_btdm_controller_config_t *cfg)
#endif /* CONFIG_BT_LE_LP_CLK_SRC_MAIN_XTAL */
}
// if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_MAIN_XTAL) {
// cfg->rtc_freq = s_bt_lpclk_freq;
// } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_XTAL32K) {
// cfg->rtc_freq = 32768;
// } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC_SLOW) {
// cfg->rtc_freq = esp_clk_tree_lp_slow_get_freq_hz(ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED) / 5;
// //TODO
// // cfg->ble_ll_sca = 3000;
// } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_RC32K) {
// cfg->rtc_freq = 32000;
// } else if (s_bt_lpclk_src == MODEM_CLOCK_LPCLK_SRC_EXT32K) {
// cfg->rtc_freq = 32000;
// }
btdm_lp_rtc_slow_clk_select(s_bt_lpclk_src);
}
@@ -198,7 +191,6 @@ void btdm_lp_set_lpclk_freq(uint32_t clk_freq)
s_bt_xtal_lpclk_freq = clk_freq;
}
>>>>>>> d8bcda6a345 (change(bt): Fix build issues and do code clean up)
static void
btdm_lp_timer_clk_deinit(void)
{
@@ -292,13 +284,9 @@ btdm_lp_enable_clock(esp_btdm_controller_config_t *cfg)
modem_clock_module_enable(PERIPH_BT_MODULE);
modem_clock_module_mac_reset(PERIPH_BT_MODULE);
#if CONFIG_IDF_TARGET_ESP32S31
// TODO: Remote this setting after WIFI is supported
REG_WRITE(MODEM_SYSCON_CLK_CONF1_REG, 0xffffffff);
// TODO: remove this include after low pwer clock init is performed in clk.c
// TODO: PM-704
REG_WRITE(HP_SYS_CLKRST_MODEM_CONF_REG, 0x3d);
#endif
// TODO: set the clock ion modem_clock_module_enable
REG_WRITE(MODEM_SYSCON_CLK_CONF_POWER_ST_REG, 0XFFFFFFFF);
btdm_lp_timer_clk_init(cfg);
}
@@ -347,6 +335,7 @@ btdm_lp_init(void)
}
#endif /* UC_BT_CTRL_SLEEP_ENABLE && CONFIG_FREERTOS_USE_TICKLESS_IDLE */
#endif /* CONFIG_PM_ENABLE */
r_btdm_hal_rtc_freq_set(s_bt_lpclk_freq);
return 0;
}
components/bt/porting_btdm/controller/btdm_common/src/btdm_osal_freertos.c
+3 -23
View File
@@ -9,6 +9,7 @@
#include <stdint.h>
#include <string.h>
#include "btdm_osal_freertos.h"
#include "btdm_user_cfg.h"
#include "btdm_mempool.h"
#include "esp_mac.h"
@@ -1147,8 +1148,7 @@ wr_btdm_osal_free(void *ptr)
heap_caps_free(ptr);
}
#if !CONFIG_BTDM_CTRL_MULTI_LINK_ENABLED
#if UC_BT_CTRL_BLE_IS_ENABLE
#if !CONFIG_BT_CTRL_MULTI_LINK_ENABLED
void *
wr_btdm_osal_mmgmt_block_malloc(uint32_t size)
{
@@ -1181,27 +1181,7 @@ wr_btdm_osal_mmgmt_block_copy(void *dst, const void *src, uint16_t size)
extern void r_ble_lll_mmgmt_block_copy(void *addr0, void *addr1, uint16_t size);
r_ble_lll_mmgmt_block_copy((void *)dst, (void *)src, size);
}
#else
void *
wr_btdm_osal_mmgmt_block_malloc(uint32_t size)
{
return NULL;
}
void
wr_btdm_osal_mmgmt_block_free(void *ptr)
{
(void)ptr;
}
void
wr_btdm_osal_mmgmt_block_copy(void *dst, const void *src, uint16_t size)
{
(void)dst;
(void)src;
(void)size;
}
#endif /* if UC_BT_CTRL_BR_EDR_IS_ENABLE */
#endif /* !CONFIG_BTDM_CTRL_MULTI_LINK_ENABLED */
#endif /* !CONFIG_BT_CTRL_MULTI_LINK_ENABLED */
/*
***************************************************************************************************
components/bt/porting_btdm/transport/driver/vhci/hci_driver_standard.c
+1 -1
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@@ -115,7 +115,7 @@ hci_driver_vhci_controller_tx(hci_driver_data_type_t data_type, uint8_t *data, u
} else if (data_type == HCI_DRIVER_TYPE_EVT) {
/* TODO: If there is no memory, should handle it in the controller. */
if (dir == HCI_DRIVER_DIR_LEC2H) {
#if UC_BTDM_CTRL_BLE_IS_ENABLE
#if UC_BT_CTRL_BLE_IS_ENABLE
buf = malloc(buf_len);
assert(buf != NULL);
buf[0] = HCI_DRIVER_TYPE_EVT;
components/esp_phy/esp32s31/include/btbb_retention_reg.h
+3 -2
View File
@@ -11,8 +11,7 @@ extern "C" {
#endif
// btbb sleep retention reg
#define BB_PART_CNT 3
#define BB_PART_CNT 4
#define BB_PART_0_SIZE 128
#define BB_PART_1_SIZE 68
#define BB_PART_2_SIZE 19
@@ -23,6 +22,8 @@ extern "C" {
#define BB_PART_2_ADDR 0x20102C00
#define BB_PART_3_ADDR 0x20102400
#ifdef __cplusplus
}
#endif
components/esp_phy/src/btbb_init.c
+4 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -37,6 +37,9 @@ static esp_err_t btbb_sleep_retention_init(void *arg)
#if BB_PART_CNT > 2
[2] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_BT_BB_LINK(0x02), BB_PART_2_ADDR, BB_PART_2_ADDR, BB_PART_2_SIZE, 0, 0), .owner = BTBB_LINK_OWNER },
#endif // BB_PART_CNT > 2
#if BB_PART_CNT > 3
[3] = { .config = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_BT_BB_LINK(0x03), BB_PART_3_ADDR, BB_PART_3_ADDR, BB_PART_3_SIZE, 0, 0), .owner = BTBB_LINK_OWNER },
#endif // BB_PART_CNT > 3
};
esp_err_t err = sleep_retention_entries_create(btbb_regs_retention, ARRAY_SIZE(btbb_regs_retention), REGDMA_LINK_PRI_BT_MAC_BB, SLEEP_RETENTION_MODULE_BT_BB);
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate memory for btbb retention");
@@ -57,7 +60,6 @@ static void btbb_sleep_retention_deinit(void)
}
#endif // SOC_PM_MODEM_RETENTION_BY_REGDMA && CONFIG_FREERTOS_USE_TICKLESS_IDLE
void esp_btbb_enable(void)
{
_lock_acquire(&s_btbb_access_lock);
components/esp_phy/src/phy_init.c
-1
View File
@@ -370,7 +370,6 @@ void esp_phy_enable(esp_phy_modem_t modem)
phy_ant_update();
phy_ant_clr_update_flag();
}
phy_module_disable();
}
phy_set_modem_flag(modem);
#if !CONFIG_IDF_TARGET_ESP32 && !CONFIG_ESP_PHY_DISABLE_PLL_TRACK