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feat(efuse): Adds calibration efuses for ESP32-P4 ECO5

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This commit is contained in:
Konstantin Kondrashov
2025-09-25 12:20:09 +03:00
parent 969d017c56
commit 6f9e137336
7 changed files with 1927 additions and 140 deletions
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components/efuse/esp32p4/esp_efuse_table_v3.0.c
+1054 -1
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File diff suppressed because it is too large Load Diff
components/efuse/esp32p4/esp_efuse_table_v3.0.csv
+118 -1
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@@ -9,7 +9,7 @@
# this will generate new source files, next rebuild all the sources.
# !!!!!!!!!!! #
# This file was generated by regtools.py based on the efuses.yaml file with the version: 8f99219081b5ec5521595bf60ed8b331
# This file was generated by regtools.py based on the efuses.yaml file with the version: 0b11fcae5408d9e48251cefb10178c11
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
@@ -87,7 +87,37 @@ WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
WR_DIS.WAFER_VERSION_MAJOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR_HI
WR_DIS.LDO_VO1_DREF, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO1_DREF
WR_DIS.LDO_VO2_DREF, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO2_DREF
WR_DIS.LDO_VO1_MUL, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO1_MUL
WR_DIS.LDO_VO2_MUL, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO2_MUL
WR_DIS.LDO_VO3_K, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO3_K
WR_DIS.LDO_VO3_VOS, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO3_VOS
WR_DIS.LDO_VO3_C, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO3_C
WR_DIS.LDO_VO4_K, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO4_K
WR_DIS.LDO_VO4_VOS, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO4_VOS
WR_DIS.LDO_VO4_C, EFUSE_BLK0, 20, 1, [] wr_dis of LDO_VO4_C
WR_DIS.ACTIVE_HP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_HP_DBIAS
WR_DIS.ACTIVE_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_LP_DBIAS
WR_DIS.DSLP_DBG, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_DBG
WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS
WR_DIS.LP_DCDC_DBIAS_VOL_GAP, EFUSE_BLK0, 20, 1, [] wr_dis of LP_DCDC_DBIAS_VOL_GAP
WR_DIS.PVT_400M_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_400M_BIAS
WR_DIS.PVT_40M_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_40M_BIAS
WR_DIS.PVT_100M_BIAS, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_100M_BIAS
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
WR_DIS.ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
WR_DIS.ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
WR_DIS.ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
WR_DIS.ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
WR_DIS.ADC2_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN0
WR_DIS.ADC2_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN1
WR_DIS.ADC2_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN2
WR_DIS.ADC2_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC2_AVE_INITCODE_ATTEN3
WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
@@ -97,6 +127,25 @@ WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.K
WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
WR_DIS.ADC2_HI_DOUT_ATTEN0, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN0
WR_DIS.ADC2_HI_DOUT_ATTEN1, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN1
WR_DIS.ADC2_HI_DOUT_ATTEN2, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN2
WR_DIS.ADC2_HI_DOUT_ATTEN3, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_HI_DOUT_ATTEN3
WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
WR_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 29, 1, [] wr_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
WR_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 29, 1, [] wr_dis of TEMPERATURE_SENSOR
WR_DIS.USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 29, 1, [] wr_dis of USB_DEVICE_EXCHG_PINS
WR_DIS.USB_OTG11_EXCHG_PINS, EFUSE_BLK0, 29, 1, [] wr_dis of USB_OTG11_EXCHG_PINS
WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG
@@ -108,6 +157,25 @@ RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.K
RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
RD_DIS.ADC2_HI_DOUT_ATTEN0, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN0
RD_DIS.ADC2_HI_DOUT_ATTEN1, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN1
RD_DIS.ADC2_HI_DOUT_ATTEN2, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN2
RD_DIS.ADC2_HI_DOUT_ATTEN3, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_HI_DOUT_ATTEN3
RD_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH5_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH6_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH6_ATTEN0_INITCODE_DIFF
RD_DIS.ADC1_CH7_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC1_CH7_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH0_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH1_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH2_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH3_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH4_ATTEN0_INITCODE_DIFF
RD_DIS.ADC2_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 38, 1, [] rd_dis of ADC2_CH5_ATTEN0_INITCODE_DIFF
RD_DIS.TEMPERATURE_SENSOR, EFUSE_BLK0, 38, 1, [] rd_dis of TEMPERATURE_SENSOR
RD_DIS.USB_DEVICE_EXCHG_PINS, EFUSE_BLK0, 38, 1, [] rd_dis of USB_DEVICE_EXCHG_PINS
RD_DIS.USB_OTG11_EXCHG_PINS, EFUSE_BLK0, 38, 1, [] rd_dis of USB_OTG11_EXCHG_PINS
RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1, EFUSE_BLK0, 39, 2, [] Represents the starting flash sector (flash sector size is 0x1000) of the recovery bootloader used by the ROM bootloader If the primary bootloader fails. 0 and 0xFFF - this feature is disabled
@@ -196,7 +264,37 @@ PSRAM_CAP, EFUSE_BLK1, 77, 3, [] PSRAM
TEMP, EFUSE_BLK1, 80, 2, [] Operating temperature of the ESP chip
PSRAM_VENDOR, EFUSE_BLK1, 82, 2, [] PSRAM vendor
PKG_VERSION, EFUSE_BLK1, 84, 3, [] Package version
LDO_VO1_DREF, EFUSE_BLK1, 88, 4, [] Output VO1 parameter
LDO_VO2_DREF, EFUSE_BLK1, 92, 4, [] Output VO2 parameter
LDO_VO1_MUL, EFUSE_BLK1, 96, 3, [] Output VO1 parameter
LDO_VO2_MUL, EFUSE_BLK1, 99, 3, [] Output VO2 parameter
LDO_VO3_K, EFUSE_BLK1, 102, 8, [] Output VO3 calibration parameter
LDO_VO3_VOS, EFUSE_BLK1, 110, 6, [] Output VO3 calibration parameter
LDO_VO3_C, EFUSE_BLK1, 116, 6, [] Output VO3 calibration parameter
LDO_VO4_K, EFUSE_BLK1, 122, 8, [] Output VO4 calibration parameter
LDO_VO4_VOS, EFUSE_BLK1, 130, 6, [] Output VO4 calibration parameter
LDO_VO4_C, EFUSE_BLK1, 136, 6, [] Output VO4 calibration parameter
ACTIVE_HP_DBIAS, EFUSE_BLK1, 144, 4, [] Active HP DBIAS of fixed voltage
ACTIVE_LP_DBIAS, EFUSE_BLK1, 148, 4, [] Active LP DBIAS of fixed voltage
DSLP_DBG, EFUSE_BLK1, 156, 4, [] DSLP BDG of fixed voltage
DSLP_LP_DBIAS, EFUSE_BLK1, 160, 5, [] DSLP LP DBIAS of fixed voltage
LP_DCDC_DBIAS_VOL_GAP, EFUSE_BLK1, 165, 5, [] DBIAS gap between LP and DCDC
PVT_400M_BIAS, EFUSE_BLK1, 171, 5, [] PVT_DCM_VSET when the CPU is at 400M
PVT_40M_BIAS, EFUSE_BLK1, 176, 5, [] PVT_DCM_VSET corresponding to about 0.9V fixed voltage when the CPU is at 40M
PVT_100M_BIAS, EFUSE_BLK1, 181, 5, [] PVT_DCM_VSET corresponding to about 1.0V fixed voltage when the CPU is at 100M
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 128, 10, [] Average initcode of ADC1 atten0
ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 138, 10, [] Average initcode of ADC1 atten1
ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 148, 10, [] Average initcode of ADC1 atten2
ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 158, 10, [] Average initcode of ADC1 atten3
ADC2_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 168, 10, [] Average initcode of ADC2 atten0
ADC2_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 178, 10, [] Average initcode of ADC2 atten1
ADC2_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 188, 10, [] Average initcode of ADC2 atten2
ADC2_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 198, 10, [] Average initcode of ADC2 atten3
ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 208, 10, [] HI_DOUT of ADC1 atten0
ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 218, 10, [] HI_DOUT of ADC1 atten1
ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 228, 10, [] HI_DOUT of ADC1 atten2
ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 238, 10, [] HI_DOUT of ADC1 atten3
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
@@ -205,5 +303,24 @@ KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KE
KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data
KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data
KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data
ADC2_HI_DOUT_ATTEN0, EFUSE_BLK10, 0, 10, [] HI_DOUT of ADC2 atten0
ADC2_HI_DOUT_ATTEN1, EFUSE_BLK10, 10, 10, [] HI_DOUT of ADC2 atten1
ADC2_HI_DOUT_ATTEN2, EFUSE_BLK10, 20, 10, [] HI_DOUT of ADC2 atten2
ADC2_HI_DOUT_ATTEN3, EFUSE_BLK10, 30, 10, [] HI_DOUT of ADC2 atten3
ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 40, 4, [] Gap between ADC1_ch0 and average initcode
ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 44, 4, [] Gap between ADC1_ch1 and average initcode
ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 48, 4, [] Gap between ADC1_ch2 and average initcode
ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 52, 4, [] Gap between ADC1_ch3 and average initcode
ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 56, 4, [] Gap between ADC1_ch4 and average initcode
ADC1_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 60, 4, [] Gap between ADC1_ch5 and average initcode
ADC1_CH6_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 64, 4, [] Gap between ADC1_ch6 and average initcode
ADC1_CH7_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 68, 4, [] Gap between ADC1_ch7 and average initcode
ADC2_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 72, 4, [] Gap between ADC2_ch0 and average initcode
ADC2_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 76, 4, [] Gap between ADC2_ch1 and average initcode
ADC2_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 80, 4, [] Gap between ADC2_ch2 and average initcode
ADC2_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 84, 4, [] Gap between ADC2_ch3 and average initcode
ADC2_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 88, 4, [] Gap between ADC2_ch4 and average initcode
ADC2_CH5_ATTEN0_INITCODE_DIFF, EFUSE_BLK10, 92, 4, [] Gap between ADC2_ch5 and average initcode
TEMPERATURE_SENSOR, EFUSE_BLK10, 96, 10, [] Temperature calibration data
USB_DEVICE_EXCHG_PINS, EFUSE_BLK10, 228, 1, [] Enable usb device exchange pins of D+ and D-
USB_OTG11_EXCHG_PINS, EFUSE_BLK10, 229, 1, [] Enable usb otg11 exchange pins of D+ and D-
Can't render this file because it contains an unexpected character in line 8 and column 53.
components/efuse/esp32p4/include/esp_efuse_table_v3.0.h
+118 -1
View File
@@ -10,7 +10,7 @@ extern "C" {
#include "esp_efuse.h"
// md5_digest_table 546834ca62bf5546bc26447554d7a099
// md5_digest_table d471a4221faaafb88f091d4549ecac55
// This file was generated from the file esp_efuse_table_v3.0.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table_v3.0.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -100,7 +100,37 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR_HI[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_DREF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_DREF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO1_MUL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO2_MUL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_K[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_VOS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO3_C[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_K[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_VOS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LDO_VO4_C[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_HP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_LP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_DBG[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LP_DCDC_DBIAS_VOL_GAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_400M_BIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_40M_BIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_100M_BIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_AVE_INITCODE_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
@@ -120,6 +150,25 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_HI_DOUT_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMPERATURE_SENSOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_DEVICE_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG11_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
@@ -138,6 +187,25 @@ extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_HI_DOUT_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_TEMPERATURE_SENSOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_USB_DEVICE_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_USB_OTG11_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_RECOVERY_BOOTLOADER_FLASH_SECTOR_0_1[];
@@ -218,7 +286,37 @@ extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_DREF[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_DREF[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO1_MUL[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO2_MUL[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_K[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_VOS[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO3_C[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_K[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_VOS[];
extern const esp_efuse_desc_t* ESP_EFUSE_LDO_VO4_C[];
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_HP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_LP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_DBG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_LP_DCDC_DBIAS_VOL_GAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_400M_BIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_40M_BIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_100M_BIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_AVE_INITCODE_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
@@ -236,6 +334,25 @@ extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_HI_DOUT_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMPERATURE_SENSOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_USB_DEVICE_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_USB_OTG11_EXCHG_PINS[];
components/hal/esp32p4/include/hal/efuse_ll.h
-12
View File
@@ -142,29 +142,17 @@ __attribute__((always_inline)) static inline uint32_t efuse_ll_get_controller_st
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_hp_dbias(void)
{
#ifdef EFUSE_ACTIVE_HP_DBIAS
return EFUSE.rd_mac_sys_4.active_hp_dbias;
#else
return 0;
#endif
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_active_lp_dbias(void)
{
#ifdef EFUSE_ACTIVE_LP_DBIAS
return EFUSE.rd_mac_sys_4.active_lp_dbias;
#else
return 0;
#endif
}
__attribute__((always_inline)) static inline int32_t efuse_ll_get_dbias_vol_gap(void)
{
#ifdef EFUSE_LP_DCDC_DBIAS_VOL_GAP
return EFUSE.rd_mac_sys_5.lp_dcdc_dbias_vol_gap;
#else
return 0;
#endif
}
/******************* eFuse control functions *************************/
components/hal/esp32p4/include/hal/ldo_ll.h
+3 -8
View File
@@ -69,16 +69,14 @@ static inline bool ldo_ll_is_valid_ldo_channel(int ldo_chan)
__attribute__((always_inline))
static inline void ldo_ll_voltage_to_dref_mul(int ldo_unit, int voltage_mv, uint8_t *dref, uint8_t *mul, bool *use_rail_voltage)
{
uint8_t efuse_k = 0;
uint8_t efuse_vos = 0;
uint8_t efuse_c = 0;
// to avoid using FPU, enlarge the constants by 1000 as fixed point
int K_1000 = 1000;
int Vos_1000 = 0;
int C_1000 = 1000;
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) < 300
uint8_t efuse_k = 0;
uint8_t efuse_vos = 0;
uint8_t efuse_c = 0;
if (efuse_hal_blk_version() >= 1) {
// load the calibration values from the eFuse
if (ldo_unit == 2) {
@@ -102,7 +100,6 @@ static inline void ldo_ll_voltage_to_dref_mul(int ldo_unit, int voltage_mv, uint
C_1000 = efuse_c & 0x20 ? -1 * (efuse_c & 0x1F) + 990 : efuse_c + 990;
}
}
#endif
// iterate all the possible dref and mul values to find the best match
int min_voltage_diff = 400000000;
@@ -124,7 +121,6 @@ static inline void ldo_ll_voltage_to_dref_mul(int ldo_unit, int voltage_mv, uint
}
}
#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) < 300
if (efuse_hal_blk_version() >= 1) {
// For unit0 and unit1, the mul and dref value are calibrated and saved in the efuse, load them when available
if (ldo_unit == 0 && voltage_mv == 1800) {
@@ -140,7 +136,6 @@ static inline void ldo_ll_voltage_to_dref_mul(int ldo_unit, int voltage_mv, uint
}
}
}
#endif
*dref = matched_dref;
*mul = matched_mul;
components/soc/esp32p4/register/hw_ver3/soc/efuse_reg.h
+407 -78
View File
@@ -893,56 +893,182 @@ extern "C" {
#define EFUSE_WAFER_VERSION_MAJOR_HI_M (EFUSE_WAFER_VERSION_MAJOR_HI_V << EFUSE_WAFER_VERSION_MAJOR_HI_S)
#define EFUSE_WAFER_VERSION_MAJOR_HI_V 0x00000001U
#define EFUSE_WAFER_VERSION_MAJOR_HI_S 23
/** EFUSE_RESERVED_1_88 : R; bitpos: [31:24]; default: 0;
* reserved
/** EFUSE_LDO_VO1_DREF : R; bitpos: [27:24]; default: 0;
* Output VO1 parameter
*/
#define EFUSE_RESERVED_1_88 0x000000FFU
#define EFUSE_RESERVED_1_88_M (EFUSE_RESERVED_1_88_V << EFUSE_RESERVED_1_88_S)
#define EFUSE_RESERVED_1_88_V 0x000000FFU
#define EFUSE_RESERVED_1_88_S 24
#define EFUSE_LDO_VO1_DREF 0x0000000FU
#define EFUSE_LDO_VO1_DREF_M (EFUSE_LDO_VO1_DREF_V << EFUSE_LDO_VO1_DREF_S)
#define EFUSE_LDO_VO1_DREF_V 0x0000000FU
#define EFUSE_LDO_VO1_DREF_S 24
/** EFUSE_LDO_VO2_DREF : R; bitpos: [31:28]; default: 0;
* Output VO2 parameter
*/
#define EFUSE_LDO_VO2_DREF 0x0000000FU
#define EFUSE_LDO_VO2_DREF_M (EFUSE_LDO_VO2_DREF_V << EFUSE_LDO_VO2_DREF_S)
#define EFUSE_LDO_VO2_DREF_V 0x0000000FU
#define EFUSE_LDO_VO2_DREF_S 28
/** EFUSE_RD_MAC_SYS_3_REG register
* Represents rd_mac_sys
*/
#define EFUSE_RD_MAC_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50)
/** EFUSE_MAC_RESERVED_2 : RO; bitpos: [17:0]; default: 0;
* Reserved.
/** EFUSE_LDO_VO1_MUL : R; bitpos: [2:0]; default: 0;
* Output VO1 parameter
*/
#define EFUSE_MAC_RESERVED_2 0x0003FFFFU
#define EFUSE_MAC_RESERVED_2_M (EFUSE_MAC_RESERVED_2_V << EFUSE_MAC_RESERVED_2_S)
#define EFUSE_MAC_RESERVED_2_V 0x0003FFFFU
#define EFUSE_MAC_RESERVED_2_S 0
/** EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0;
* Represents the first 14-bit of zeroth part of system data.
#define EFUSE_LDO_VO1_MUL 0x00000007U
#define EFUSE_LDO_VO1_MUL_M (EFUSE_LDO_VO1_MUL_V << EFUSE_LDO_VO1_MUL_S)
#define EFUSE_LDO_VO1_MUL_V 0x00000007U
#define EFUSE_LDO_VO1_MUL_S 0
/** EFUSE_LDO_VO2_MUL : R; bitpos: [5:3]; default: 0;
* Output VO2 parameter
*/
#define EFUSE_SYS_DATA_PART0_0 0x00003FFFU
#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S)
#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFFU
#define EFUSE_SYS_DATA_PART0_0_S 18
#define EFUSE_LDO_VO2_MUL 0x00000007U
#define EFUSE_LDO_VO2_MUL_M (EFUSE_LDO_VO2_MUL_V << EFUSE_LDO_VO2_MUL_S)
#define EFUSE_LDO_VO2_MUL_V 0x00000007U
#define EFUSE_LDO_VO2_MUL_S 3
/** EFUSE_LDO_VO3_K : R; bitpos: [13:6]; default: 0;
* Output VO3 calibration parameter
*/
#define EFUSE_LDO_VO3_K 0x000000FFU
#define EFUSE_LDO_VO3_K_M (EFUSE_LDO_VO3_K_V << EFUSE_LDO_VO3_K_S)
#define EFUSE_LDO_VO3_K_V 0x000000FFU
#define EFUSE_LDO_VO3_K_S 6
/** EFUSE_LDO_VO3_VOS : R; bitpos: [19:14]; default: 0;
* Output VO3 calibration parameter
*/
#define EFUSE_LDO_VO3_VOS 0x0000003FU
#define EFUSE_LDO_VO3_VOS_M (EFUSE_LDO_VO3_VOS_V << EFUSE_LDO_VO3_VOS_S)
#define EFUSE_LDO_VO3_VOS_V 0x0000003FU
#define EFUSE_LDO_VO3_VOS_S 14
/** EFUSE_LDO_VO3_C : R; bitpos: [25:20]; default: 0;
* Output VO3 calibration parameter
*/
#define EFUSE_LDO_VO3_C 0x0000003FU
#define EFUSE_LDO_VO3_C_M (EFUSE_LDO_VO3_C_V << EFUSE_LDO_VO3_C_S)
#define EFUSE_LDO_VO3_C_V 0x0000003FU
#define EFUSE_LDO_VO3_C_S 20
/** EFUSE_LDO_VO4_K : R; bitpos: [31:26]; default: 0;
* Output VO4 calibration parameter
*/
#define EFUSE_LDO_VO4_K 0x0000003FU
#define EFUSE_LDO_VO4_K_M (EFUSE_LDO_VO4_K_V << EFUSE_LDO_VO4_K_S)
#define EFUSE_LDO_VO4_K_V 0x0000003FU
#define EFUSE_LDO_VO4_K_S 26
/** EFUSE_RD_MAC_SYS_4_REG register
* Represents rd_mac_sys
*/
#define EFUSE_RD_MAC_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54)
/** EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0;
* Represents the second 32-bit of zeroth part of system data.
/** EFUSE_LDO_VO4_K_1 : R; bitpos: [1:0]; default: 0;
* Output VO4 calibration parameter
*/
#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S)
#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART0_1_S 0
#define EFUSE_LDO_VO4_K_1 0x00000003U
#define EFUSE_LDO_VO4_K_1_M (EFUSE_LDO_VO4_K_1_V << EFUSE_LDO_VO4_K_1_S)
#define EFUSE_LDO_VO4_K_1_V 0x00000003U
#define EFUSE_LDO_VO4_K_1_S 0
/** EFUSE_LDO_VO4_VOS : R; bitpos: [7:2]; default: 0;
* Output VO4 calibration parameter
*/
#define EFUSE_LDO_VO4_VOS 0x0000003FU
#define EFUSE_LDO_VO4_VOS_M (EFUSE_LDO_VO4_VOS_V << EFUSE_LDO_VO4_VOS_S)
#define EFUSE_LDO_VO4_VOS_V 0x0000003FU
#define EFUSE_LDO_VO4_VOS_S 2
/** EFUSE_LDO_VO4_C : R; bitpos: [13:8]; default: 0;
* Output VO4 calibration parameter
*/
#define EFUSE_LDO_VO4_C 0x0000003FU
#define EFUSE_LDO_VO4_C_M (EFUSE_LDO_VO4_C_V << EFUSE_LDO_VO4_C_S)
#define EFUSE_LDO_VO4_C_V 0x0000003FU
#define EFUSE_LDO_VO4_C_S 8
/** EFUSE_RESERVED_1_142 : R; bitpos: [15:14]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_1_142 0x00000003U
#define EFUSE_RESERVED_1_142_M (EFUSE_RESERVED_1_142_V << EFUSE_RESERVED_1_142_S)
#define EFUSE_RESERVED_1_142_V 0x00000003U
#define EFUSE_RESERVED_1_142_S 14
/** EFUSE_ACTIVE_HP_DBIAS : R; bitpos: [19:16]; default: 0;
* Active HP DBIAS of fixed voltage
*/
#define EFUSE_ACTIVE_HP_DBIAS 0x0000000FU
#define EFUSE_ACTIVE_HP_DBIAS_M (EFUSE_ACTIVE_HP_DBIAS_V << EFUSE_ACTIVE_HP_DBIAS_S)
#define EFUSE_ACTIVE_HP_DBIAS_V 0x0000000FU
#define EFUSE_ACTIVE_HP_DBIAS_S 16
/** EFUSE_ACTIVE_LP_DBIAS : R; bitpos: [23:20]; default: 0;
* Active LP DBIAS of fixed voltage
*/
#define EFUSE_ACTIVE_LP_DBIAS 0x0000000FU
#define EFUSE_ACTIVE_LP_DBIAS_M (EFUSE_ACTIVE_LP_DBIAS_V << EFUSE_ACTIVE_LP_DBIAS_S)
#define EFUSE_ACTIVE_LP_DBIAS_V 0x0000000FU
#define EFUSE_ACTIVE_LP_DBIAS_S 20
/** EFUSE_RESERVED_1_152 : R; bitpos: [27:24]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_1_152 0x0000000FU
#define EFUSE_RESERVED_1_152_M (EFUSE_RESERVED_1_152_V << EFUSE_RESERVED_1_152_S)
#define EFUSE_RESERVED_1_152_V 0x0000000FU
#define EFUSE_RESERVED_1_152_S 24
/** EFUSE_DSLP_DBG : R; bitpos: [31:28]; default: 0;
* DSLP BDG of fixed voltage
*/
#define EFUSE_DSLP_DBG 0x0000000FU
#define EFUSE_DSLP_DBG_M (EFUSE_DSLP_DBG_V << EFUSE_DSLP_DBG_S)
#define EFUSE_DSLP_DBG_V 0x0000000FU
#define EFUSE_DSLP_DBG_S 28
/** EFUSE_RD_MAC_SYS_5_REG register
* Represents rd_mac_sys
*/
#define EFUSE_RD_MAC_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58)
/** EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0;
* Represents the third 32-bit of zeroth part of system data.
/** EFUSE_DSLP_LP_DBIAS : R; bitpos: [4:0]; default: 0;
* DSLP LP DBIAS of fixed voltage
*/
#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S)
#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART0_2_S 0
#define EFUSE_DSLP_LP_DBIAS 0x0000001FU
#define EFUSE_DSLP_LP_DBIAS_M (EFUSE_DSLP_LP_DBIAS_V << EFUSE_DSLP_LP_DBIAS_S)
#define EFUSE_DSLP_LP_DBIAS_V 0x0000001FU
#define EFUSE_DSLP_LP_DBIAS_S 0
/** EFUSE_LP_DCDC_DBIAS_VOL_GAP : R; bitpos: [9:5]; default: 0;
* DBIAS gap between LP and DCDC
*/
#define EFUSE_LP_DCDC_DBIAS_VOL_GAP 0x0000001FU
#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_M (EFUSE_LP_DCDC_DBIAS_VOL_GAP_V << EFUSE_LP_DCDC_DBIAS_VOL_GAP_S)
#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_V 0x0000001FU
#define EFUSE_LP_DCDC_DBIAS_VOL_GAP_S 5
/** EFUSE_RESERVED_1_170 : R; bitpos: [10]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_1_170 (BIT(10))
#define EFUSE_RESERVED_1_170_M (EFUSE_RESERVED_1_170_V << EFUSE_RESERVED_1_170_S)
#define EFUSE_RESERVED_1_170_V 0x00000001U
#define EFUSE_RESERVED_1_170_S 10
/** EFUSE_PVT_400M_BIAS : R; bitpos: [15:11]; default: 0;
* PVT_DCM_VSET when the CPU is at 400M
*/
#define EFUSE_PVT_400M_BIAS 0x0000001FU
#define EFUSE_PVT_400M_BIAS_M (EFUSE_PVT_400M_BIAS_V << EFUSE_PVT_400M_BIAS_S)
#define EFUSE_PVT_400M_BIAS_V 0x0000001FU
#define EFUSE_PVT_400M_BIAS_S 11
/** EFUSE_PVT_40M_BIAS : R; bitpos: [20:16]; default: 0;
* PVT_DCM_VSET corresponding to about 0.9V fixed voltage when the CPU is at 40M
*/
#define EFUSE_PVT_40M_BIAS 0x0000001FU
#define EFUSE_PVT_40M_BIAS_M (EFUSE_PVT_40M_BIAS_V << EFUSE_PVT_40M_BIAS_S)
#define EFUSE_PVT_40M_BIAS_V 0x0000001FU
#define EFUSE_PVT_40M_BIAS_S 16
/** EFUSE_PVT_100M_BIAS : R; bitpos: [25:21]; default: 0;
* PVT_DCM_VSET corresponding to about 1.0V fixed voltage when the CPU is at 100M
*/
#define EFUSE_PVT_100M_BIAS 0x0000001FU
#define EFUSE_PVT_100M_BIAS_M (EFUSE_PVT_100M_BIAS_V << EFUSE_PVT_100M_BIAS_S)
#define EFUSE_PVT_100M_BIAS_V 0x0000001FU
#define EFUSE_PVT_100M_BIAS_S 21
/** EFUSE_RESERVED_1_186 : R; bitpos: [31:26]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_1_186 0x0000003FU
#define EFUSE_RESERVED_1_186_M (EFUSE_RESERVED_1_186_V << EFUSE_RESERVED_1_186_S)
#define EFUSE_RESERVED_1_186_V 0x0000003FU
#define EFUSE_RESERVED_1_186_S 26
/** EFUSE_RD_SYS_PART1_DATA0_REG register
* Represents rd_sys_part1_data0
@@ -996,49 +1122,133 @@ extern "C" {
* Represents rd_sys_part1_data4
*/
#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c)
/** EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0;
* Represents the zeroth 32-bit of first part of system data.
/** EFUSE_ADC1_AVE_INITCODE_ATTEN0 : R; bitpos: [9:0]; default: 0;
* Average initcode of ADC1 atten0
*/
#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S)
#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_4_S 0
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0 0x000003FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_M (EFUSE_ADC1_AVE_INITCODE_ATTEN0_V << EFUSE_ADC1_AVE_INITCODE_ATTEN0_S)
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_V 0x000003FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN0_S 0
/** EFUSE_ADC1_AVE_INITCODE_ATTEN1 : R; bitpos: [19:10]; default: 0;
* Average initcode of ADC1 atten1
*/
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1 0x000003FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN1_S)
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_V 0x000003FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN1_S 10
/** EFUSE_ADC1_AVE_INITCODE_ATTEN2 : R; bitpos: [29:20]; default: 0;
* Average initcode of ADC1 atten2
*/
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2 0x000003FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_M (EFUSE_ADC1_AVE_INITCODE_ATTEN2_V << EFUSE_ADC1_AVE_INITCODE_ATTEN2_S)
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_V 0x000003FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN2_S 20
/** EFUSE_ADC1_AVE_INITCODE_ATTEN3 : R; bitpos: [31:30]; default: 0;
* Average initcode of ADC1 atten3
*/
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3 0x00000003U
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_S)
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_V 0x00000003U
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_S 30
/** EFUSE_RD_SYS_PART1_DATA5_REG register
* Represents rd_sys_part1_data5
*/
#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70)
/** EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0;
* Represents the zeroth 32-bit of first part of system data.
/** EFUSE_ADC1_AVE_INITCODE_ATTEN3_1 : R; bitpos: [7:0]; default: 0;
* Average initcode of ADC1 atten3
*/
#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S)
#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_5_S 0
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1 0x000000FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_M (EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_V << EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_S)
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_V 0x000000FFU
#define EFUSE_ADC1_AVE_INITCODE_ATTEN3_1_S 0
/** EFUSE_ADC2_AVE_INITCODE_ATTEN0 : R; bitpos: [17:8]; default: 0;
* Average initcode of ADC2 atten0
*/
#define EFUSE_ADC2_AVE_INITCODE_ATTEN0 0x000003FFU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_M (EFUSE_ADC2_AVE_INITCODE_ATTEN0_V << EFUSE_ADC2_AVE_INITCODE_ATTEN0_S)
#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_V 0x000003FFU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN0_S 8
/** EFUSE_ADC2_AVE_INITCODE_ATTEN1 : R; bitpos: [27:18]; default: 0;
* Average initcode of ADC2 atten1
*/
#define EFUSE_ADC2_AVE_INITCODE_ATTEN1 0x000003FFU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_M (EFUSE_ADC2_AVE_INITCODE_ATTEN1_V << EFUSE_ADC2_AVE_INITCODE_ATTEN1_S)
#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_V 0x000003FFU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN1_S 18
/** EFUSE_ADC2_AVE_INITCODE_ATTEN2 : R; bitpos: [31:28]; default: 0;
* Average initcode of ADC2 atten2
*/
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2 0x0000000FU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_M (EFUSE_ADC2_AVE_INITCODE_ATTEN2_V << EFUSE_ADC2_AVE_INITCODE_ATTEN2_S)
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_V 0x0000000FU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_S 28
/** EFUSE_RD_SYS_PART1_DATA6_REG register
* Represents rd_sys_part1_data6
*/
#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74)
/** EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0;
* Represents the zeroth 32-bit of first part of system data.
/** EFUSE_ADC2_AVE_INITCODE_ATTEN2_1 : R; bitpos: [5:0]; default: 0;
* Average initcode of ADC2 atten2
*/
#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S)
#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_6_S 0
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1 0x0000003FU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_M (EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_V << EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_S)
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_V 0x0000003FU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN2_1_S 0
/** EFUSE_ADC2_AVE_INITCODE_ATTEN3 : R; bitpos: [15:6]; default: 0;
* Average initcode of ADC2 atten3
*/
#define EFUSE_ADC2_AVE_INITCODE_ATTEN3 0x000003FFU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_M (EFUSE_ADC2_AVE_INITCODE_ATTEN3_V << EFUSE_ADC2_AVE_INITCODE_ATTEN3_S)
#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_V 0x000003FFU
#define EFUSE_ADC2_AVE_INITCODE_ATTEN3_S 6
/** EFUSE_ADC1_HI_DOUT_ATTEN0 : R; bitpos: [25:16]; default: 0;
* HI_DOUT of ADC1 atten0
*/
#define EFUSE_ADC1_HI_DOUT_ATTEN0 0x000003FFU
#define EFUSE_ADC1_HI_DOUT_ATTEN0_M (EFUSE_ADC1_HI_DOUT_ATTEN0_V << EFUSE_ADC1_HI_DOUT_ATTEN0_S)
#define EFUSE_ADC1_HI_DOUT_ATTEN0_V 0x000003FFU
#define EFUSE_ADC1_HI_DOUT_ATTEN0_S 16
/** EFUSE_ADC1_HI_DOUT_ATTEN1 : R; bitpos: [31:26]; default: 0;
* HI_DOUT of ADC1 atten1
*/
#define EFUSE_ADC1_HI_DOUT_ATTEN1 0x0000003FU
#define EFUSE_ADC1_HI_DOUT_ATTEN1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_S)
#define EFUSE_ADC1_HI_DOUT_ATTEN1_V 0x0000003FU
#define EFUSE_ADC1_HI_DOUT_ATTEN1_S 26
/** EFUSE_RD_SYS_PART1_DATA7_REG register
* Represents rd_sys_part1_data7
*/
#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78)
/** EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0;
* Represents the zeroth 32-bit of first part of system data.
/** EFUSE_ADC1_HI_DOUT_ATTEN1_1 : R; bitpos: [3:0]; default: 0;
* HI_DOUT of ADC1 atten1
*/
#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S)
#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART1_7_S 0
#define EFUSE_ADC1_HI_DOUT_ATTEN1_1 0x0000000FU
#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_M (EFUSE_ADC1_HI_DOUT_ATTEN1_1_V << EFUSE_ADC1_HI_DOUT_ATTEN1_1_S)
#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_V 0x0000000FU
#define EFUSE_ADC1_HI_DOUT_ATTEN1_1_S 0
/** EFUSE_ADC1_HI_DOUT_ATTEN2 : R; bitpos: [13:4]; default: 0;
* HI_DOUT of ADC1 atten2
*/
#define EFUSE_ADC1_HI_DOUT_ATTEN2 0x000003FFU
#define EFUSE_ADC1_HI_DOUT_ATTEN2_M (EFUSE_ADC1_HI_DOUT_ATTEN2_V << EFUSE_ADC1_HI_DOUT_ATTEN2_S)
#define EFUSE_ADC1_HI_DOUT_ATTEN2_V 0x000003FFU
#define EFUSE_ADC1_HI_DOUT_ATTEN2_S 4
/** EFUSE_ADC1_HI_DOUT_ATTEN3 : R; bitpos: [23:14]; default: 0;
* HI_DOUT of ADC1 atten3
*/
#define EFUSE_ADC1_HI_DOUT_ATTEN3 0x000003FFU
#define EFUSE_ADC1_HI_DOUT_ATTEN3_M (EFUSE_ADC1_HI_DOUT_ATTEN3_V << EFUSE_ADC1_HI_DOUT_ATTEN3_S)
#define EFUSE_ADC1_HI_DOUT_ATTEN3_V 0x000003FFU
#define EFUSE_ADC1_HI_DOUT_ATTEN3_S 14
/** EFUSE_RESERVED_2_248 : R; bitpos: [31:24]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_2_248 0x000000FFU
#define EFUSE_RESERVED_2_248_M (EFUSE_RESERVED_2_248_V << EFUSE_RESERVED_2_248_S)
#define EFUSE_RESERVED_2_248_V 0x000000FFU
#define EFUSE_RESERVED_2_248_S 24
/** EFUSE_RD_USR_DATA0_REG register
* Represents rd_usr_data0
@@ -1730,49 +1940,168 @@ extern "C" {
* Represents rd_sys_part2_data
*/
#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c)
/** EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0;
* Represents the first 32-bit of second part of system data.
/** EFUSE_ADC2_HI_DOUT_ATTEN0 : R; bitpos: [9:0]; default: 0;
* HI_DOUT of ADC2 atten0
*/
#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S)
#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_0_S 0
#define EFUSE_ADC2_HI_DOUT_ATTEN0 0x000003FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN0_M (EFUSE_ADC2_HI_DOUT_ATTEN0_V << EFUSE_ADC2_HI_DOUT_ATTEN0_S)
#define EFUSE_ADC2_HI_DOUT_ATTEN0_V 0x000003FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN0_S 0
/** EFUSE_ADC2_HI_DOUT_ATTEN1 : R; bitpos: [19:10]; default: 0;
* HI_DOUT of ADC2 atten1
*/
#define EFUSE_ADC2_HI_DOUT_ATTEN1 0x000003FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN1_M (EFUSE_ADC2_HI_DOUT_ATTEN1_V << EFUSE_ADC2_HI_DOUT_ATTEN1_S)
#define EFUSE_ADC2_HI_DOUT_ATTEN1_V 0x000003FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN1_S 10
/** EFUSE_ADC2_HI_DOUT_ATTEN2 : R; bitpos: [29:20]; default: 0;
* HI_DOUT of ADC2 atten2
*/
#define EFUSE_ADC2_HI_DOUT_ATTEN2 0x000003FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN2_M (EFUSE_ADC2_HI_DOUT_ATTEN2_V << EFUSE_ADC2_HI_DOUT_ATTEN2_S)
#define EFUSE_ADC2_HI_DOUT_ATTEN2_V 0x000003FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN2_S 20
/** EFUSE_ADC2_HI_DOUT_ATTEN3 : R; bitpos: [31:30]; default: 0;
* HI_DOUT of ADC2 atten3
*/
#define EFUSE_ADC2_HI_DOUT_ATTEN3 0x00000003U
#define EFUSE_ADC2_HI_DOUT_ATTEN3_M (EFUSE_ADC2_HI_DOUT_ATTEN3_V << EFUSE_ADC2_HI_DOUT_ATTEN3_S)
#define EFUSE_ADC2_HI_DOUT_ATTEN3_V 0x00000003U
#define EFUSE_ADC2_HI_DOUT_ATTEN3_S 30
/** EFUSE_RD_SYS_PART2_DATA1_REG register
* Represents rd_sys_part2_data
*/
#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160)
/** EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0;
* Represents the first 32-bit of second part of system data.
/** EFUSE_ADC2_HI_DOUT_ATTEN3_1 : R; bitpos: [7:0]; default: 0;
* HI_DOUT of ADC2 atten3
*/
#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S)
#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_1_S 0
#define EFUSE_ADC2_HI_DOUT_ATTEN3_1 0x000000FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_M (EFUSE_ADC2_HI_DOUT_ATTEN3_1_V << EFUSE_ADC2_HI_DOUT_ATTEN3_1_S)
#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_V 0x000000FFU
#define EFUSE_ADC2_HI_DOUT_ATTEN3_1_S 0
/** EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [11:8]; default: 0;
* Gap between ADC1_ch0 and average initcode
*/
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF_S 8
/** EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [15:12]; default: 0;
* Gap between ADC1_ch1 and average initcode
*/
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF_S 12
/** EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [19:16]; default: 0;
* Gap between ADC1_ch2 and average initcode
*/
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF_S 16
/** EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [23:20]; default: 0;
* Gap between ADC1_ch3 and average initcode
*/
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF_S 20
/** EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [27:24]; default: 0;
* Gap between ADC1_ch4 and average initcode
*/
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF_S 24
/** EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [31:28]; default: 0;
* Gap between ADC1_ch5 and average initcode
*/
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH5_ATTEN0_INITCODE_DIFF_S 28
/** EFUSE_RD_SYS_PART2_DATA2_REG register
* Represents rd_sys_part2_data
*/
#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164)
/** EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0;
* Represents the second 32-bit of second part of system data.
/** EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF : R; bitpos: [3:0]; default: 0;
* Gap between ADC1_ch6 and average initcode
*/
#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S)
#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_2_S 0
#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH6_ATTEN0_INITCODE_DIFF_S 0
/** EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF : R; bitpos: [7:4]; default: 0;
* Gap between ADC1_ch7 and average initcode
*/
#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC1_CH7_ATTEN0_INITCODE_DIFF_S 4
/** EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF : R; bitpos: [11:8]; default: 0;
* Gap between ADC2_ch0 and average initcode
*/
#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC2_CH0_ATTEN0_INITCODE_DIFF_S 8
/** EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF : R; bitpos: [15:12]; default: 0;
* Gap between ADC2_ch1 and average initcode
*/
#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC2_CH1_ATTEN0_INITCODE_DIFF_S 12
/** EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF : R; bitpos: [19:16]; default: 0;
* Gap between ADC2_ch2 and average initcode
*/
#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC2_CH2_ATTEN0_INITCODE_DIFF_S 16
/** EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF : R; bitpos: [23:20]; default: 0;
* Gap between ADC2_ch3 and average initcode
*/
#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC2_CH3_ATTEN0_INITCODE_DIFF_S 20
/** EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF : R; bitpos: [27:24]; default: 0;
* Gap between ADC2_ch4 and average initcode
*/
#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC2_CH4_ATTEN0_INITCODE_DIFF_S 24
/** EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF : R; bitpos: [31:28]; default: 0;
* Gap between ADC2_ch5 and average initcode
*/
#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF 0x0000000FU
#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_M (EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_V << EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_S)
#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_V 0x0000000FU
#define EFUSE_ADC2_CH5_ATTEN0_INITCODE_DIFF_S 28
/** EFUSE_RD_SYS_PART2_DATA3_REG register
* Represents rd_sys_part2_data
*/
#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168)
/** EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0;
* Represents the third 32-bit of second part of system data.
/** EFUSE_TEMPERATURE_SENSOR : R; bitpos: [9:0]; default: 0;
* Temperature calibration data
*/
#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S)
#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFFU
#define EFUSE_SYS_DATA_PART2_3_S 0
#define EFUSE_TEMPERATURE_SENSOR 0x000003FFU
#define EFUSE_TEMPERATURE_SENSOR_M (EFUSE_TEMPERATURE_SENSOR_V << EFUSE_TEMPERATURE_SENSOR_S)
#define EFUSE_TEMPERATURE_SENSOR_V 0x000003FFU
#define EFUSE_TEMPERATURE_SENSOR_S 0
/** EFUSE_RESERVED_10_106 : R; bitpos: [31:10]; default: 0;
* reserved
*/
#define EFUSE_RESERVED_10_106 0x003FFFFFU
#define EFUSE_RESERVED_10_106_M (EFUSE_RESERVED_10_106_V << EFUSE_RESERVED_10_106_S)
#define EFUSE_RESERVED_10_106_V 0x003FFFFFU
#define EFUSE_RESERVED_10_106_S 10
/** EFUSE_RD_SYS_PART2_DATA4_REG register
* Represents rd_sys_part2_data
components/soc/esp32p4/register/hw_ver3/soc/efuse_struct.h
+227 -39
View File
@@ -549,10 +549,14 @@ typedef union {
* Major chip version (MSB)
*/
uint32_t wafer_version_major_hi:1;
/** reserved_1_88 : R; bitpos: [31:24]; default: 0;
* reserved
/** ldo_vo1_dref : R; bitpos: [27:24]; default: 0;
* Output VO1 parameter
*/
uint32_t reserved_1_88:8;
uint32_t ldo_vo1_dref:4;
/** ldo_vo2_dref : R; bitpos: [31:28]; default: 0;
* Output VO2 parameter
*/
uint32_t ldo_vo2_dref:4;
};
uint32_t val;
} efuse_rd_mac_sys2_reg_t;
@@ -562,14 +566,30 @@ typedef union {
*/
typedef union {
struct {
/** mac_reserved_2 : RO; bitpos: [17:0]; default: 0;
* Reserved.
/** ldo_vo1_mul : R; bitpos: [2:0]; default: 0;
* Output VO1 parameter
*/
uint32_t mac_reserved_2:18;
/** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
* Represents the first 14-bit of zeroth part of system data.
uint32_t ldo_vo1_mul:3;
/** ldo_vo2_mul : R; bitpos: [5:3]; default: 0;
* Output VO2 parameter
*/
uint32_t sys_data_part0_0:14;
uint32_t ldo_vo2_mul:3;
/** ldo_vo3_k : R; bitpos: [13:6]; default: 0;
* Output VO3 calibration parameter
*/
uint32_t ldo_vo3_k:8;
/** ldo_vo3_vos : R; bitpos: [19:14]; default: 0;
* Output VO3 calibration parameter
*/
uint32_t ldo_vo3_vos:6;
/** ldo_vo3_c : R; bitpos: [25:20]; default: 0;
* Output VO3 calibration parameter
*/
uint32_t ldo_vo3_c:6;
/** ldo_vo4_k : R; bitpos: [31:26]; default: 0;
* Output VO4 calibration parameter
*/
uint32_t ldo_vo4_k:6;
};
uint32_t val;
} efuse_rd_mac_sys3_reg_t;
@@ -579,10 +599,38 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
* Represents the second 32-bit of zeroth part of system data.
/** ldo_vo4_k_1 : R; bitpos: [1:0]; default: 0;
* Output VO4 calibration parameter
*/
uint32_t sys_data_part0_1:32;
uint32_t ldo_vo4_k_1:2;
/** ldo_vo4_vos : R; bitpos: [7:2]; default: 0;
* Output VO4 calibration parameter
*/
uint32_t ldo_vo4_vos:6;
/** ldo_vo4_c : R; bitpos: [13:8]; default: 0;
* Output VO4 calibration parameter
*/
uint32_t ldo_vo4_c:6;
/** reserved_1_142 : R; bitpos: [15:14]; default: 0;
* reserved
*/
uint32_t reserved_1_142:2;
/** active_hp_dbias : R; bitpos: [19:16]; default: 0;
* Active HP DBIAS of fixed voltage
*/
uint32_t active_hp_dbias:4;
/** active_lp_dbias : R; bitpos: [23:20]; default: 0;
* Active LP DBIAS of fixed voltage
*/
uint32_t active_lp_dbias:4;
/** reserved_1_152 : R; bitpos: [27:24]; default: 0;
* reserved
*/
uint32_t reserved_1_152:4;
/** dslp_dbg : R; bitpos: [31:28]; default: 0;
* DSLP BDG of fixed voltage
*/
uint32_t dslp_dbg:4;
};
uint32_t val;
} efuse_rd_mac_sys4_reg_t;
@@ -592,10 +640,34 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
* Represents the third 32-bit of zeroth part of system data.
/** dslp_lp_dbias : R; bitpos: [4:0]; default: 0;
* DSLP LP DBIAS of fixed voltage
*/
uint32_t sys_data_part0_2:32;
uint32_t dslp_lp_dbias:5;
/** lp_dcdc_dbias_vol_gap : R; bitpos: [9:5]; default: 0;
* DBIAS gap between LP and DCDC
*/
uint32_t lp_dcdc_dbias_vol_gap:5;
/** reserved_1_170 : R; bitpos: [10]; default: 0;
* reserved
*/
uint32_t reserved_1_170:1;
/** pvt_400m_bias : R; bitpos: [15:11]; default: 0;
* PVT_DCM_VSET when the CPU is at 400M
*/
uint32_t pvt_400m_bias:5;
/** pvt_40m_bias : R; bitpos: [20:16]; default: 0;
* PVT_DCM_VSET corresponding to about 0.9V fixed voltage when the CPU is at 40M
*/
uint32_t pvt_40m_bias:5;
/** pvt_100m_bias : R; bitpos: [25:21]; default: 0;
* PVT_DCM_VSET corresponding to about 1.0V fixed voltage when the CPU is at 100M
*/
uint32_t pvt_100m_bias:5;
/** reserved_1_186 : R; bitpos: [31:26]; default: 0;
* reserved
*/
uint32_t reserved_1_186:6;
};
uint32_t val;
} efuse_rd_mac_sys5_reg_t;
@@ -659,10 +731,22 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_4 : RO; bitpos: [31:0]; default: 0;
* Represents the zeroth 32-bit of first part of system data.
/** adc1_ave_initcode_atten0 : R; bitpos: [9:0]; default: 0;
* Average initcode of ADC1 atten0
*/
uint32_t sys_data_part1_4:32;
uint32_t adc1_ave_initcode_atten0:10;
/** adc1_ave_initcode_atten1 : R; bitpos: [19:10]; default: 0;
* Average initcode of ADC1 atten1
*/
uint32_t adc1_ave_initcode_atten1:10;
/** adc1_ave_initcode_atten2 : R; bitpos: [29:20]; default: 0;
* Average initcode of ADC1 atten2
*/
uint32_t adc1_ave_initcode_atten2:10;
/** adc1_ave_initcode_atten3 : R; bitpos: [31:30]; default: 0;
* Average initcode of ADC1 atten3
*/
uint32_t adc1_ave_initcode_atten3:2;
};
uint32_t val;
} efuse_rd_sys_part1_data4_reg_t;
@@ -672,10 +756,22 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_5 : RO; bitpos: [31:0]; default: 0;
* Represents the zeroth 32-bit of first part of system data.
/** adc1_ave_initcode_atten3_1 : R; bitpos: [7:0]; default: 0;
* Average initcode of ADC1 atten3
*/
uint32_t sys_data_part1_5:32;
uint32_t adc1_ave_initcode_atten3_1:8;
/** adc2_ave_initcode_atten0 : R; bitpos: [17:8]; default: 0;
* Average initcode of ADC2 atten0
*/
uint32_t adc2_ave_initcode_atten0:10;
/** adc2_ave_initcode_atten1 : R; bitpos: [27:18]; default: 0;
* Average initcode of ADC2 atten1
*/
uint32_t adc2_ave_initcode_atten1:10;
/** adc2_ave_initcode_atten2 : R; bitpos: [31:28]; default: 0;
* Average initcode of ADC2 atten2
*/
uint32_t adc2_ave_initcode_atten2:4;
};
uint32_t val;
} efuse_rd_sys_part1_data5_reg_t;
@@ -685,10 +781,22 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_6 : RO; bitpos: [31:0]; default: 0;
* Represents the zeroth 32-bit of first part of system data.
/** adc2_ave_initcode_atten2_1 : R; bitpos: [5:0]; default: 0;
* Average initcode of ADC2 atten2
*/
uint32_t sys_data_part1_6:32;
uint32_t adc2_ave_initcode_atten2_1:6;
/** adc2_ave_initcode_atten3 : R; bitpos: [15:6]; default: 0;
* Average initcode of ADC2 atten3
*/
uint32_t adc2_ave_initcode_atten3:10;
/** adc1_hi_dout_atten0 : R; bitpos: [25:16]; default: 0;
* HI_DOUT of ADC1 atten0
*/
uint32_t adc1_hi_dout_atten0:10;
/** adc1_hi_dout_atten1 : R; bitpos: [31:26]; default: 0;
* HI_DOUT of ADC1 atten1
*/
uint32_t adc1_hi_dout_atten1:6;
};
uint32_t val;
} efuse_rd_sys_part1_data6_reg_t;
@@ -698,10 +806,22 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part1_7 : RO; bitpos: [31:0]; default: 0;
* Represents the zeroth 32-bit of first part of system data.
/** adc1_hi_dout_atten1_1 : R; bitpos: [3:0]; default: 0;
* HI_DOUT of ADC1 atten1
*/
uint32_t sys_data_part1_7:32;
uint32_t adc1_hi_dout_atten1_1:4;
/** adc1_hi_dout_atten2 : R; bitpos: [13:4]; default: 0;
* HI_DOUT of ADC1 atten2
*/
uint32_t adc1_hi_dout_atten2:10;
/** adc1_hi_dout_atten3 : R; bitpos: [23:14]; default: 0;
* HI_DOUT of ADC1 atten3
*/
uint32_t adc1_hi_dout_atten3:10;
/** reserved_2_248 : R; bitpos: [31:24]; default: 0;
* reserved
*/
uint32_t reserved_2_248:8;
};
uint32_t val;
} efuse_rd_sys_part1_data7_reg_t;
@@ -917,10 +1037,22 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part2_0 : RO; bitpos: [31:0]; default: 0;
* Represents the first 32-bit of second part of system data.
/** adc2_hi_dout_atten0 : R; bitpos: [9:0]; default: 0;
* HI_DOUT of ADC2 atten0
*/
uint32_t sys_data_part2_0:32;
uint32_t adc2_hi_dout_atten0:10;
/** adc2_hi_dout_atten1 : R; bitpos: [19:10]; default: 0;
* HI_DOUT of ADC2 atten1
*/
uint32_t adc2_hi_dout_atten1:10;
/** adc2_hi_dout_atten2 : R; bitpos: [29:20]; default: 0;
* HI_DOUT of ADC2 atten2
*/
uint32_t adc2_hi_dout_atten2:10;
/** adc2_hi_dout_atten3 : R; bitpos: [31:30]; default: 0;
* HI_DOUT of ADC2 atten3
*/
uint32_t adc2_hi_dout_atten3:2;
};
uint32_t val;
} efuse_rd_sys_part2_data0_reg_t;
@@ -930,10 +1062,34 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part2_1 : RO; bitpos: [31:0]; default: 0;
* Represents the first 32-bit of second part of system data.
/** adc2_hi_dout_atten3_1 : R; bitpos: [7:0]; default: 0;
* HI_DOUT of ADC2 atten3
*/
uint32_t sys_data_part2_1:32;
uint32_t adc2_hi_dout_atten3_1:8;
/** adc1_ch0_atten0_initcode_diff : R; bitpos: [11:8]; default: 0;
* Gap between ADC1_ch0 and average initcode
*/
uint32_t adc1_ch0_atten0_initcode_diff:4;
/** adc1_ch1_atten0_initcode_diff : R; bitpos: [15:12]; default: 0;
* Gap between ADC1_ch1 and average initcode
*/
uint32_t adc1_ch1_atten0_initcode_diff:4;
/** adc1_ch2_atten0_initcode_diff : R; bitpos: [19:16]; default: 0;
* Gap between ADC1_ch2 and average initcode
*/
uint32_t adc1_ch2_atten0_initcode_diff:4;
/** adc1_ch3_atten0_initcode_diff : R; bitpos: [23:20]; default: 0;
* Gap between ADC1_ch3 and average initcode
*/
uint32_t adc1_ch3_atten0_initcode_diff:4;
/** adc1_ch4_atten0_initcode_diff : R; bitpos: [27:24]; default: 0;
* Gap between ADC1_ch4 and average initcode
*/
uint32_t adc1_ch4_atten0_initcode_diff:4;
/** adc1_ch5_atten0_initcode_diff : R; bitpos: [31:28]; default: 0;
* Gap between ADC1_ch5 and average initcode
*/
uint32_t adc1_ch5_atten0_initcode_diff:4;
};
uint32_t val;
} efuse_rd_sys_part2_data1_reg_t;
@@ -943,10 +1099,38 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part2_2 : RO; bitpos: [31:0]; default: 0;
* Represents the second 32-bit of second part of system data.
/** adc1_ch6_atten0_initcode_diff : R; bitpos: [3:0]; default: 0;
* Gap between ADC1_ch6 and average initcode
*/
uint32_t sys_data_part2_2:32;
uint32_t adc1_ch6_atten0_initcode_diff:4;
/** adc1_ch7_atten0_initcode_diff : R; bitpos: [7:4]; default: 0;
* Gap between ADC1_ch7 and average initcode
*/
uint32_t adc1_ch7_atten0_initcode_diff:4;
/** adc2_ch0_atten0_initcode_diff : R; bitpos: [11:8]; default: 0;
* Gap between ADC2_ch0 and average initcode
*/
uint32_t adc2_ch0_atten0_initcode_diff:4;
/** adc2_ch1_atten0_initcode_diff : R; bitpos: [15:12]; default: 0;
* Gap between ADC2_ch1 and average initcode
*/
uint32_t adc2_ch1_atten0_initcode_diff:4;
/** adc2_ch2_atten0_initcode_diff : R; bitpos: [19:16]; default: 0;
* Gap between ADC2_ch2 and average initcode
*/
uint32_t adc2_ch2_atten0_initcode_diff:4;
/** adc2_ch3_atten0_initcode_diff : R; bitpos: [23:20]; default: 0;
* Gap between ADC2_ch3 and average initcode
*/
uint32_t adc2_ch3_atten0_initcode_diff:4;
/** adc2_ch4_atten0_initcode_diff : R; bitpos: [27:24]; default: 0;
* Gap between ADC2_ch4 and average initcode
*/
uint32_t adc2_ch4_atten0_initcode_diff:4;
/** adc2_ch5_atten0_initcode_diff : R; bitpos: [31:28]; default: 0;
* Gap between ADC2_ch5 and average initcode
*/
uint32_t adc2_ch5_atten0_initcode_diff:4;
};
uint32_t val;
} efuse_rd_sys_part2_data2_reg_t;
@@ -956,10 +1140,14 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part2_3 : RO; bitpos: [31:0]; default: 0;
* Represents the third 32-bit of second part of system data.
/** temperature_sensor : R; bitpos: [9:0]; default: 0;
* Temperature calibration data
*/
uint32_t sys_data_part2_3:32;
uint32_t temperature_sensor:10;
/** reserved_10_106 : R; bitpos: [31:10]; default: 0;
* reserved
*/
uint32_t reserved_10_106:22;
};
uint32_t val;
} efuse_rd_sys_part2_data3_reg_t;