feat(esp_hw_support): add rtc wdt runnning during sleep test case

This commit is contained in:
hebinglin
2025-12-31 17:22:05 +08:00
parent b763ce7974
commit 6fa4a504f9
3 changed files with 68 additions and 0 deletions
@@ -17,6 +17,7 @@
#include "esp_system.h"
#include "esp_intr_alloc.h"
#include "esp_private/rtc_ctrl.h"
#include "esp_private/esp_sleep_internal.h"
/* As the RTC slow clock used by RWDT is derived using RC oscillator by default,
* the timing accuracy is not very precise, and may vary from chip to chip.
@@ -178,6 +179,50 @@ static void rtc_wdt_setup_then_reset_RTC(void)
}
}
#if SOC_LIGHT_SLEEP_SUPPORTED && CONFIG_ESP_SLEEP_ENABLE_RTC_WDT_IN_SLEEP
/* MULTI test case for light sleep prepare timeout then RTC WDT resets RTC */
static void rtc_wdt_light_sleep_prepare_timeout(void)
{
uint32_t stage_timeout_ticks = (uint32_t)(1000 * rtc_clk_slow_freq_get_hz() / 1000ULL); /* 1000ms for interrupt */
esp_sleep_enable_timer_wakeup(3000000);
/* Setup RTC WDT */
// Here enable RTC_WDT then the setup in sleep flow will be skipped
wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, true);
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
wdt_hal_enable(&rtc_wdt_ctx);
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
TEST_ASSERT_TRUE(wdt_hal_is_enabled(&rtc_wdt_ctx));
printf("RTC WDT setup stage-0 RESET (1000ms)\n");
esp_light_sleep_start();
/* Wait for RTC WDT to reset the main system and RTC */
esp_restart();
}
#endif
#if SOC_DEEP_SLEEP_SUPPORTED && CONFIG_ESP_SLEEP_ENABLE_RTC_WDT_IN_DEEP_SLEEP
/* MULTI test case for deep sleep prepare timeout then RTC WDT resets RTC */
static void rtc_wdt_deep_sleep_prepare_timeout(void)
{
uint32_t stage_timeout_ticks = (uint32_t)(1000 * rtc_clk_slow_freq_get_hz() / 1000ULL); /* 1000ms for interrupt */
esp_sleep_enable_timer_wakeup(3000000);
/* Setup RTC WDT */
// Here enable RTC_WDT then the setup in sleep flow will be skipped
wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, true);
wdt_hal_write_protect_disable(&rtc_wdt_ctx);
wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
wdt_hal_enable(&rtc_wdt_ctx);
wdt_hal_write_protect_enable(&rtc_wdt_ctx);
TEST_ASSERT_TRUE(wdt_hal_is_enabled(&rtc_wdt_ctx));
printf("RTC WDT setup stage-0 RESET (1000ms)\n");
esp_deep_sleep_start();
}
#endif
static void rtc_wdt_verify_SYSTEM_reset(void)
{
printf("Confirming if reset reason matches 0x9 (main system reset)\n");
@@ -211,3 +256,21 @@ TEST_CASE_MULTIPLE_STAGES(
rtc_wdt_setup_then_reset_RTC,
rtc_wdt_verify_RTC_reset
)
#if SOC_LIGHT_SLEEP_SUPPORTED && CONFIG_ESP_SLEEP_ENABLE_RTC_WDT_IN_SLEEP
TEST_CASE_MULTIPLE_STAGES(
"Light sleep prepare timeout then RTC WDT resets RTC",
"[rtc_wdt][lightsleep][reset]",
rtc_wdt_light_sleep_prepare_timeout,
rtc_wdt_verify_RTC_reset
)
#endif
#if SOC_DEEP_SLEEP_SUPPORTED && CONFIG_ESP_SLEEP_ENABLE_RTC_WDT_IN_DEEP_SLEEP
TEST_CASE_MULTIPLE_STAGES(
"Deep sleep prepare timeout then RTC WDT resets RTC",
"[rtc_wdt][deepsleep][reset]",
rtc_wdt_deep_sleep_prepare_timeout,
rtc_wdt_verify_RTC_reset
)
#endif
@@ -13,6 +13,7 @@ from pytest_embedded_idf.utils import soc_filtered_targets
('single_core_esp32', 'esp32'),
*(('default', target) for target in soc_filtered_targets('IDF_TARGET not in ["esp32c5"]')),
*(('release', target) for target in soc_filtered_targets('IDF_TARGET not in ["esp32c5"]')),
*(('rwdt_monitor', target) for target in soc_filtered_targets('IDF_TARGET not in ["esp32c5"]')),
],
indirect=['config', 'target'],
)
@@ -0,0 +1,4 @@
# enable RTC WDT during sleep period
CONFIG_ESP_SLEEP_ENABLE_RTC_WDT_IN_SLEEP=y
CONFIG_ESP_SLEEP_ENABLE_RTC_WDT_IN_DEEP_SLEEP=y
CONFIG_IDF_EXPERIMENTAL_FEATURES=y