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https://github.com/espressif/esp-idf.git
synced 2026-04-27 19:13:21 +00:00
feat(esp_hw_support): add rtc wdt runnning during sleep test case
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@@ -17,6 +17,7 @@
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#include "esp_system.h"
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#include "esp_intr_alloc.h"
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#include "esp_private/rtc_ctrl.h"
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#include "esp_private/esp_sleep_internal.h"
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/* As the RTC slow clock used by RWDT is derived using RC oscillator by default,
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* the timing accuracy is not very precise, and may vary from chip to chip.
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@@ -178,6 +179,50 @@ static void rtc_wdt_setup_then_reset_RTC(void)
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}
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}
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#if SOC_LIGHT_SLEEP_SUPPORTED && CONFIG_ESP_SLEEP_ENABLE_RTC_WDT_IN_SLEEP
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/* MULTI test case for light sleep prepare timeout then RTC WDT resets RTC */
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static void rtc_wdt_light_sleep_prepare_timeout(void)
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{
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uint32_t stage_timeout_ticks = (uint32_t)(1000 * rtc_clk_slow_freq_get_hz() / 1000ULL); /* 1000ms for interrupt */
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esp_sleep_enable_timer_wakeup(3000000);
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/* Setup RTC WDT */
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// Here enable RTC_WDT then the setup in sleep flow will be skipped
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wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, true);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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wdt_hal_enable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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TEST_ASSERT_TRUE(wdt_hal_is_enabled(&rtc_wdt_ctx));
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printf("RTC WDT setup stage-0 RESET (1000ms)\n");
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esp_light_sleep_start();
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/* Wait for RTC WDT to reset the main system and RTC */
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esp_restart();
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}
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#endif
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#if SOC_DEEP_SLEEP_SUPPORTED && CONFIG_ESP_SLEEP_ENABLE_RTC_WDT_IN_DEEP_SLEEP
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/* MULTI test case for deep sleep prepare timeout then RTC WDT resets RTC */
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static void rtc_wdt_deep_sleep_prepare_timeout(void)
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{
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uint32_t stage_timeout_ticks = (uint32_t)(1000 * rtc_clk_slow_freq_get_hz() / 1000ULL); /* 1000ms for interrupt */
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esp_sleep_enable_timer_wakeup(3000000);
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/* Setup RTC WDT */
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// Here enable RTC_WDT then the setup in sleep flow will be skipped
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wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, true);
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wdt_hal_write_protect_disable(&rtc_wdt_ctx);
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wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
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wdt_hal_enable(&rtc_wdt_ctx);
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wdt_hal_write_protect_enable(&rtc_wdt_ctx);
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TEST_ASSERT_TRUE(wdt_hal_is_enabled(&rtc_wdt_ctx));
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printf("RTC WDT setup stage-0 RESET (1000ms)\n");
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esp_deep_sleep_start();
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}
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#endif
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static void rtc_wdt_verify_SYSTEM_reset(void)
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{
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printf("Confirming if reset reason matches 0x9 (main system reset)\n");
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@@ -211,3 +256,21 @@ TEST_CASE_MULTIPLE_STAGES(
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rtc_wdt_setup_then_reset_RTC,
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rtc_wdt_verify_RTC_reset
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)
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#if SOC_LIGHT_SLEEP_SUPPORTED && CONFIG_ESP_SLEEP_ENABLE_RTC_WDT_IN_SLEEP
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TEST_CASE_MULTIPLE_STAGES(
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"Light sleep prepare timeout then RTC WDT resets RTC",
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"[rtc_wdt][lightsleep][reset]",
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rtc_wdt_light_sleep_prepare_timeout,
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rtc_wdt_verify_RTC_reset
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)
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#endif
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#if SOC_DEEP_SLEEP_SUPPORTED && CONFIG_ESP_SLEEP_ENABLE_RTC_WDT_IN_DEEP_SLEEP
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TEST_CASE_MULTIPLE_STAGES(
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"Deep sleep prepare timeout then RTC WDT resets RTC",
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"[rtc_wdt][deepsleep][reset]",
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rtc_wdt_deep_sleep_prepare_timeout,
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rtc_wdt_verify_RTC_reset
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)
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#endif
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+1
@@ -13,6 +13,7 @@ from pytest_embedded_idf.utils import soc_filtered_targets
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('single_core_esp32', 'esp32'),
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*(('default', target) for target in soc_filtered_targets('IDF_TARGET not in ["esp32c5"]')),
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*(('release', target) for target in soc_filtered_targets('IDF_TARGET not in ["esp32c5"]')),
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*(('rwdt_monitor', target) for target in soc_filtered_targets('IDF_TARGET not in ["esp32c5"]')),
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],
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indirect=['config', 'target'],
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)
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+4
@@ -0,0 +1,4 @@
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# enable RTC WDT during sleep period
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CONFIG_ESP_SLEEP_ENABLE_RTC_WDT_IN_SLEEP=y
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CONFIG_ESP_SLEEP_ENABLE_RTC_WDT_IN_DEEP_SLEEP=y
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CONFIG_IDF_EXPERIMENTAL_FEATURES=y
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