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refactor(uart): split UART HAL into separate component

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This commit is contained in:
Song Ruo Jing
2025-12-12 19:39:54 +08:00
parent 59fa9f7430
commit 74aeb3f41f
82 changed files with 963 additions and 883 deletions
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components/app_trace/port/port_uart.c
+1 -1
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@@ -15,7 +15,7 @@
#include "hal/uart_hal.h"
#include "hal/gpio_hal.h"
#include "driver/uart.h"
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
#include "esp_clk_tree.h"
#include "esp_private/esp_clk_tree_common.h"
#include "soc/gpio_periph.h"
components/bootloader_support/CMakeLists.txt
+2 -2
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@@ -74,7 +74,7 @@ if(BOOTLOADER_BUILD OR CONFIG_APP_BUILD_TYPE_RAM)
"private_include")
set(priv_requires micro-ecc spi_flash efuse esp_bootloader_format esp_app_format esptool_py)
# `esp_hal_ana_conv` is required by bootloader_random_esp32xx.c
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_ana_conv)
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_uart esp_hal_ana_conv)
list(APPEND srcs
"src/bootloader_init.c"
"src/bootloader_clock_loader.c"
@@ -92,7 +92,7 @@ else()
# heap is required for `heap_memory_layout.h` header
set(priv_requires spi_flash mbedtls efuse heap esp_bootloader_format esp_app_format esptool_py)
# `esp_hal_ana_conv` is required by bootloader_random_esp32xx.c
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_ana_conv)
list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_uart esp_hal_ana_conv)
endif()
if(BOOTLOADER_BUILD)
components/bootloader_support/src/bootloader_console.c
+1 -1
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@@ -7,7 +7,7 @@
#include "sdkconfig.h"
#include "bootloader_console.h"
#include "soc/soc_caps.h"
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
#include "soc/uart_pins.h"
#include "soc/io_mux_reg.h"
#include "soc/gpio_sig_map.h"
components/driver/test_apps/legacy_i2c_driver/main/CMakeLists.txt
+1 -1
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@@ -3,5 +3,5 @@ set(srcs "test_app_main.c"
)
idf_component_register(SRCS ${srcs}
PRIV_REQUIRES unity test_utils driver esp_driver_gpio
PRIV_REQUIRES unity test_utils driver esp_driver_gpio esp_hal_uart
WHOLE_ARCHIVE)
components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c
+1 -1
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@@ -20,7 +20,7 @@
#include "hal/gpio_types.h"
#include "hal/uart_ll.h"
#include "hal/i2c_types.h"
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
#include "test_utils.h"
#include "esp_private/gpio.h"
#include "driver/gpio.h"
components/esp_driver_gpio/test_apps/.build-test-rules.yml
+1
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@@ -10,6 +10,7 @@ components/esp_driver_gpio/test_apps/gpio:
- if: IDF_TARGET in ["esp32s31"]
temporary: true
reason: not support yet # TODO: [ESP32S31] IDF-14780
components/esp_driver_gpio/test_apps/gpio_extensions:
enable:
- if: SOC_DEDICATED_GPIO_SUPPORTED == 1
components/esp_driver_gpio/test_apps/gpio/CMakeLists.txt
+2 -2
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@@ -14,11 +14,11 @@ if(CONFIG_COMPILER_DUMP_RTL_FILES)
${CMAKE_BINARY_DIR}/esp-idf/esp_hal_gpio
${CMAKE_BINARY_DIR}/esp-idf/hal
)
string(JOIN "," RTL_DIRS_STRING ${GPIO_RTL_DIRS})
string(JOIN "," GPIO_RTL_DIRS_JOINED ${GPIO_RTL_DIRS})
add_custom_target(
check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${RTL_DIRS_STRING}
--rtl-dirs ${GPIO_RTL_DIRS_JOINED}
--elf-file ${CMAKE_BINARY_DIR}/gpio_test.elf
find-refs
--from-sections=.iram0.text
components/esp_driver_uart/CMakeLists.txt
+1 -1
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@@ -9,7 +9,6 @@ if(CONFIG_SOC_UART_SUPPORTED)
endif()
endif()
if(${target} STREQUAL "linux")
set(priv_requires esp_ringbuf)
else()
@@ -19,6 +18,7 @@ endif()
idf_component_register(
SRCS ${srcs}
INCLUDE_DIRS ${public_include}
REQUIRES esp_hal_uart
PRIV_REQUIRES "${priv_requires}"
LDFRAGMENTS "linker.lf"
)
components/esp_driver_uart/linker.lf
+1 -1
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@@ -5,7 +5,7 @@ entries:
uart_vfs: select_notif_callback_isr (noflash)
[mapping:uart_hal]
archive: libhal.a
archive: libesp_hal_uart.a
entries:
if UART_ISR_IN_IRAM = y:
uart_hal_iram (noflash)
components/esp_driver_uart/src/uart.c
+1 -1
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@@ -18,7 +18,7 @@
#include "freertos/idf_additions.h"
#include "esp_private/critical_section.h"
#include "hal/uart_hal.h"
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
#include "soc/soc_caps.h"
#include "driver/uart.h"
#include "driver/gpio.h"
components/esp_driver_uart/src/uhci.c
+1 -1
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@@ -22,7 +22,7 @@
#include "driver/uart.h"
#include "driver/uhci.h"
#include "driver/uhci_types.h"
#include "soc/uhci_periph.h"
#include "hal/uhci_periph.h"
#include "soc/soc_caps.h"
#include "hal/uhci_hal.h"
#include "hal/uhci_ll.h"
components/esp_driver_uart/test_apps/.build-test-rules.yml
+5
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@@ -12,6 +12,7 @@ components/esp_driver_uart/test_apps/rs485:
reason: lack of runners
depends_components:
- esp_driver_uart
- esp_hal_uart
- esp_driver_gpio
components/esp_driver_uart/test_apps/uart:
@@ -22,11 +23,13 @@ components/esp_driver_uart/test_apps/uart:
reason: not support yet # TODO: [ESP32S31] IDF-14789
depends_components:
- esp_driver_uart
- esp_hal_uart
- esp_driver_gpio
components/esp_driver_uart/test_apps/uart_vfs:
depends_components:
- esp_driver_uart
- esp_hal_uart
- vfs
components/esp_driver_uart/test_apps/uhci:
@@ -34,3 +37,5 @@ components/esp_driver_uart/test_apps/uhci:
- if: SOC_UHCI_SUPPORTED != 1
depends_components:
- esp_driver_uart
- esp_hal_uart
- esp_driver_gpio
components/esp_driver_uart/test_apps/uart/CMakeLists.txt
+7 -1
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@@ -11,9 +11,15 @@ project(uart_test)
idf_build_get_property(elf EXECUTABLE)
if(CONFIG_COMPILER_DUMP_RTL_FILES)
set(UART_RTL_DIRS
${CMAKE_BINARY_DIR}/esp-idf/esp_driver_uart
${CMAKE_BINARY_DIR}/esp-idf/esp_hal_uart
${CMAKE_BINARY_DIR}/esp-idf/hal
)
string(JOIN "," UART_RTL_DIRS_JOINED ${UART_RTL_DIRS})
add_custom_target(check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_uart/,${CMAKE_BINARY_DIR}/esp-idf/hal/
--rtl-dirs ${UART_RTL_DIRS_JOINED}
--elf-file ${CMAKE_BINARY_DIR}/uart_test.elf
find-refs
--from-sections=.iram0.text
components/esp_driver_uart/test_apps/uart/main/test_uart.c
+1 -1
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@@ -16,7 +16,7 @@
#include "driver/rtc_io.h"
#include "hal/rtc_io_ll.h"
#endif
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
#include "soc/uart_pins.h"
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
components/esp_driver_uart/test_apps/uhci/CMakeLists.txt
+7 -1
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@@ -11,9 +11,15 @@ project(uhci_test)
idf_build_get_property(elf EXECUTABLE)
if(CONFIG_COMPILER_DUMP_RTL_FILES)
set(UHCI_RTL_DIRS
${CMAKE_BINARY_DIR}/esp-idf/esp_driver_uart
${CMAKE_BINARY_DIR}/esp-idf/esp_hal_uart
${CMAKE_BINARY_DIR}/esp-idf/hal
)
string(JOIN "," UHCI_RTL_DIRS_JOINED ${UHCI_RTL_DIRS})
add_custom_target(check_test_app_sections ALL
COMMAND ${PYTHON} $ENV{IDF_PATH}/tools/ci/check_callgraph.py
--rtl-dirs ${CMAKE_BINARY_DIR}/esp-idf/esp_driver_uart/,${CMAKE_BINARY_DIR}/esp-idf/hal/
--rtl-dirs ${UHCI_RTL_DIRS_JOINED}
--elf-file ${CMAKE_BINARY_DIR}/uhci_test.elf
find-refs
--from-sections=.iram0.text
components/esp_gdbstub/CMakeLists.txt
+1 -1
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@@ -28,4 +28,4 @@ idf_component_register(SRCS ${srcs}
PRIV_INCLUDE_DIRS ${priv_includes}
LDFRAGMENTS "linker.lf"
REQUIRES "freertos"
PRIV_REQUIRES esp_hal_wdt)
PRIV_REQUIRES esp_hal_wdt esp_hal_uart)
components/esp_hal_gpio/Kconfig.hal_gpio
+9
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@@ -0,0 +1,9 @@
config HAL_GPIO_USE_ROM_IMPL
bool "Use ROM implementation of GPIO HAL driver"
default y
help
Enable this flag to use HAL functions from ROM when applicable instead of ESP-IDF.
If keeping this as "n" in your project, you will have less free IRAM.
When compiling an application for a CPU that cannot access to the ROM memory,
this option should be disabled.
components/esp_hal_gpio/README.md
+32 -5
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@@ -1,9 +1,36 @@
# `esp_hal_gpio`
# ESP Hardware Abstraction Layer for GPIO Peripheral
⚠️ This HAL component is still under heavy development at the moment, so we don't guarantee the stability and backward-compatibility among versions.
> [!NOTE]
> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
The `esp_hal_gpio` component provides a **Hardware Abstraction Layer** of GPIO for all targets supported by ESP-IDF.
## Overview
In a broad sense, the HAL layer consists of two sub-layers: HAL (upper) and Low-Level(bottom). The HAL layer defines the steps and data that is required to operate a peripheral (e.g. initialization, start and stop). The low-level is a translation layer above the register files under the `soc` component, it only covers general conceptions to register configurations.
The `esp_hal_gpio` component provides a **Hardware Abstraction Layer** for General-Purpose Input/Output (GPIO) across all ESP-IDF supported targets.
The functions in this file mainly provide hardware abstraction for IDF peripheral drivers. For advanced developers, the HAL layer functions can also be directly used to assist in implementing their own drivers. However, it needs to be mentioned again that the interfaces here do not guarantee stability.
## Architecture
The GPIO HAL is structured in two main sub-layers:
1. **HAL Layer (Upper)**: Defines the operational steps and data structures required to configure and control GPIO pins (e.g., direction, level, pull mode, interrupt enable/disable).
2. **Low-Level Layer (Bottom)**: Serves as a translation layer between the HAL and the register files defined in the `soc` component, handling target-specific register configurations.
## Features
- Configure pin direction (input/output)
- Set and get logic levels
- Internal pull-up/pull-down configuration (on supported chips)
- Open-drain/output mode selection (on supported chips)
- Interrupt configuration (edge/level) and handling
- Drive strength configuration (on supported chips)
- Deep sleep and light sleep helpers for pin retention (on supported chips)
## Usage
The HAL functions primarily serve ESP-IDF peripheral drivers and system components that need efficient and portable GPIO control.
Advanced developers can use these interfaces directly when implementing custom drivers, with the understanding that API stability is not guaranteed.
## Dependencies
- `soc`: Provides chip-specific register definitions
- `hal`: Core hardware abstraction utilities and macros
components/esp_hal_uart/CMakeLists.txt
+22
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@@ -0,0 +1,22 @@
idf_build_get_property(target IDF_TARGET)
set(srcs)
set(includes "include")
# Add target-specific include directory if it exists
if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/include")
list(APPEND includes "${target}/include")
endif()
if(CONFIG_SOC_UART_SUPPORTED)
list(APPEND srcs "uart_hal.c" "uart_hal_iram.c" "${target}/uart_periph.c")
endif()
# UHCI HAL source
if(CONFIG_SOC_UHCI_SUPPORTED)
list(APPEND srcs "uhci_hal.c")
endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${includes}
REQUIRES soc hal)
components/esp_hal_uart/README.md
+41
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@@ -0,0 +1,41 @@
# ESP Hardware Abstraction Layer for UART Peripheral
> [!NOTE]
> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
## Overview
The `esp_hal_uart` component provides a **Hardware Abstraction Layer** for Universal Asynchronous Receiver/Transmitter (UART) peripherals across all ESP-IDF supported targets. It also includes support for UHCI (Universal Host Controller Interface) on chips where it is available and enabled.
## Architecture
The UART HAL is structured in two main sub-layers:
1. **HAL Layer (Upper)**: Defines the operational steps and data structures required to control UART/UHCI peripherals (e.g., initialization, configuration, data movement, power-management hooks).
2. **Low-Level Layer (Bottom)**: Serves as a translation layer between the HAL and the register files defined in the `soc` component, handling target-specific register configurations.
## Supported Controllers
- **UART**: Standard UART controller available on all supported ESP chips
- **UHCI**: Available on selected chips; built when `CONFIG_SOC_UHCI_SUPPORTED` is enabled
## Features
- Configurable baud rate, data bits, parity, and stop bits
- Hardware and software flow control (on supported chips)
- RX/TX FIFO management
- Interrupt-driven operations
- DMA support on capable chips
- Clock source selection (on supported chips)
- Light-sleep and wakeup helpers (on supported chips)
## Usage
The HAL functions primarily serve ESP-IDF peripheral drivers such as `esp_driver_uart`.
Advanced developers can use these interfaces directly when implementing custom drivers, with the understanding that API stability is not guaranteed.
## Dependencies
- `soc`: Provides chip-specific register definitions
- `hal`: Core hardware abstraction utilities and macros
components/hal/esp32/include/hal/uart_ll.h → components/esp_hal_uart/esp32/include/hal/uart_ll.h
+73 -74
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@@ -7,7 +7,6 @@
// The LL layer for UART register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdlib.h>
@@ -18,10 +17,6 @@
#include "soc/dport_reg.h"
#include "hal/uart_types.h"
#ifdef __cplusplus
extern "C" {
#endif
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
@@ -37,27 +32,31 @@ extern "C" {
#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask
#ifdef __cplusplus
extern "C" {
#endif
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1<<0),
UART_INTR_TXFIFO_EMPTY = (0x1<<1),
UART_INTR_PARITY_ERR = (0x1<<2),
UART_INTR_FRAM_ERR = (0x1<<3),
UART_INTR_RXFIFO_OVF = (0x1<<4),
UART_INTR_DSR_CHG = (0x1<<5),
UART_INTR_CTS_CHG = (0x1<<6),
UART_INTR_BRK_DET = (0x1<<7),
UART_INTR_RXFIFO_TOUT = (0x1<<8),
UART_INTR_SW_XON = (0x1<<9),
UART_INTR_SW_XOFF = (0x1<<10),
UART_INTR_GLITCH_DET = (0x1<<11),
UART_INTR_TX_BRK_DONE = (0x1<<12),
UART_INTR_TX_BRK_IDLE = (0x1<<13),
UART_INTR_TX_DONE = (0x1<<14),
UART_INTR_RS485_PARITY_ERR = (0x1<<15),
UART_INTR_RS485_FRM_ERR = (0x1<<16),
UART_INTR_RS485_CLASH = (0x1<<17),
UART_INTR_CMD_CHAR_DET = (0x1<<18),
UART_INTR_RXFIFO_FULL = (0x1 << 0),
UART_INTR_TXFIFO_EMPTY = (0x1 << 1),
UART_INTR_PARITY_ERR = (0x1 << 2),
UART_INTR_FRAM_ERR = (0x1 << 3),
UART_INTR_RXFIFO_OVF = (0x1 << 4),
UART_INTR_DSR_CHG = (0x1 << 5),
UART_INTR_CTS_CHG = (0x1 << 6),
UART_INTR_BRK_DET = (0x1 << 7),
UART_INTR_RXFIFO_TOUT = (0x1 << 8),
UART_INTR_SW_XON = (0x1 << 9),
UART_INTR_SW_XOFF = (0x1 << 10),
UART_INTR_GLITCH_DET = (0x1 << 11),
UART_INTR_TX_BRK_DONE = (0x1 << 12),
UART_INTR_TX_BRK_IDLE = (0x1 << 13),
UART_INTR_TX_DONE = (0x1 << 14),
UART_INTR_RS485_PARITY_ERR = (0x1 << 15),
UART_INTR_RS485_FRM_ERR = (0x1 << 16),
UART_INTR_RS485_CLASH = (0x1 << 17),
UART_INTR_CMD_CHAR_DET = (0x1 << 18),
} uart_intr_t;
/**
@@ -70,13 +69,13 @@ typedef enum {
FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
{
uint32_t uart_rst_bit = ((uart_num == 0) ? DPORT_UART_RST :
(uart_num == 1) ? DPORT_UART1_RST :
(uart_num == 2) ? DPORT_UART2_RST : 0);
(uart_num == 1) ? DPORT_UART1_RST :
(uart_num == 2) ? DPORT_UART2_RST : 0);
uint32_t uart_en_bit = ((uart_num == 0) ? DPORT_UART_CLK_EN :
(uart_num == 1) ? DPORT_UART1_CLK_EN :
(uart_num == 2) ? DPORT_UART2_CLK_EN : 0);
(uart_num == 1) ? DPORT_UART1_CLK_EN :
(uart_num == 2) ? DPORT_UART2_CLK_EN : 0);
return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN_REG, uart_rst_bit) == 0 &&
DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
}
/**
@@ -173,15 +172,15 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
switch (source_clk) {
case UART_SCLK_REF_TICK:
hw->conf0.tick_ref_always_on = 0;
break;
case UART_SCLK_APB:
hw->conf0.tick_ref_always_on = 1;
break;
default:
// Invalid UART clock source
abort();
case UART_SCLK_REF_TICK:
hw->conf0.tick_ref_always_on = 0;
break;
case UART_SCLK_APB:
hw->conf0.tick_ref_always_on = 1;
break;
default:
// Invalid UART clock source
abort();
}
}
@@ -196,13 +195,13 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
switch (hw->conf0.tick_ref_always_on) {
default:
case 0:
*source_clk = (soc_module_clk_t)UART_SCLK_REF_TICK;
break;
case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_APB;
break;
default:
case 0:
*source_clk = (soc_module_clk_t)UART_SCLK_REF_TICK;
break;
case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_APB;
break;
}
}
@@ -364,7 +363,7 @@ FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf,
{
//Get the UART AHB fifo addr, Write fifo, we use AHB address
uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_AHB_REG(0) : (hw == &UART1) ? UART_FIFO_AHB_REG(1) : UART_FIFO_AHB_REG(2);
for(uint32_t i = 0; i < wr_len; i++) {
for (uint32_t i = 0; i < wr_len; i++) {
WRITE_PERI_REG(fifo_addr, buf[i]);
}
}
@@ -386,12 +385,12 @@ FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw)
do {
fifo_cnt = HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt);
rxmem_sta.val = hw->mem_rx_status.val;
if(fifo_cnt != 0 || (rxmem_sta.rd_addr != rxmem_sta.wr_addr)) {
if (fifo_cnt != 0 || (rxmem_sta.rd_addr != rxmem_sta.wr_addr)) {
READ_PERI_REG(fifo_addr);
} else {
break;
}
} while(1);
} while (1);
}
/**
@@ -463,7 +462,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
{
//workaround for hardware issue, when UART stop bit set as 2-bit mode.
if(stop_bit == UART_STOP_BITS_2) {
if (stop_bit == UART_STOP_BITS_2) {
hw->rs485_conf.dl1_en = 1;
hw->conf0.stop_bit_num = 0x1;
} else {
@@ -483,7 +482,7 @@ FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t st
FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
{
//workaround for hardware issue, when UART stop bit set as 2-bit mode.
if(hw->rs485_conf.dl1_en == 1 && hw->conf0.stop_bit_num == 0x1) {
if (hw->rs485_conf.dl1_en == 1 && hw->conf0.stop_bit_num == 0x1) {
*stop_bit = (uart_stop_bits_t)UART_STOP_BITS_2;
} else {
*stop_bit = (uart_stop_bits_t)hw->conf0.stop_bit_num;
@@ -500,7 +499,7 @@ FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *s
*/
FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
{
if(parity_mode != UART_PARITY_DISABLE) {
if (parity_mode != UART_PARITY_DISABLE) {
hw->conf0.parity = parity_mode & 0x1;
}
hw->conf0.parity_en = (parity_mode >> 1) & 0x1;
@@ -516,7 +515,7 @@ FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_m
*/
FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
{
if(hw->conf0.parity_en) {
if (hw->conf0.parity_en) {
*parity_mode = (uart_parity_t)(0x2 | hw->conf0.parity);
} else {
*parity_mode = UART_PARITY_DISABLE;
@@ -588,7 +587,7 @@ FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num
*/
FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
{
if(break_num > 0) {
if (break_num > 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->idle_conf, tx_brk_num, break_num);
hw->conf0.txd_brk = 1;
} else {
@@ -608,13 +607,13 @@ FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
{
//only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
if(flow_ctrl & UART_HW_FLOWCTRL_RTS) {
if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
hw->conf1.rx_flow_thrhd = rx_thrs;
hw->conf1.rx_flow_en = 1;
} else {
hw->conf1.rx_flow_en = 0;
}
if(flow_ctrl & UART_HW_FLOWCTRL_CTS) {
if (flow_ctrl & UART_HW_FLOWCTRL_CTS) {
hw->conf0.tx_flow_en = 1;
} else {
hw->conf0.tx_flow_en = 0;
@@ -632,10 +631,10 @@ FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcont
FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
{
*flow_ctrl = UART_HW_FLOWCTRL_DISABLE;
if(hw->conf1.rx_flow_en) {
if (hw->conf1.rx_flow_en) {
*flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_RTS);
}
if(hw->conf0.tx_flow_en) {
if (hw->conf0.tx_flow_en) {
*flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_CTS);
}
}
@@ -651,7 +650,7 @@ FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcont
*/
FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
{
if(sw_flow_ctrl_en) {
if (sw_flow_ctrl_en) {
hw->flow_conf.xonoff_del = 1;
hw->flow_conf.sw_flow_con_en = 1;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xon_threshold, flow_ctrl->xon_thrd);
@@ -859,22 +858,22 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
{
switch (mode) {
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
uart_ll_set_mode_irda(hw);
break;
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
uart_ll_set_mode_irda(hw);
break;
}
}
components/hal/esp32/include/hal/uhci_ll.h → components/esp_hal_uart/esp32/include/hal/uhci_ll.h
View File
components/soc/esp32/uart_periph.c → components/esp_hal_uart/esp32/uart_periph.c
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
/*
Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
components/hal/esp32c2/include/hal/uart_ll.h → components/esp_hal_uart/esp32c2/include/hal/uart_ll.h
+49 -50
View File
@@ -20,10 +20,6 @@
#include "soc/dport_access.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
@@ -39,6 +35,10 @@ extern "C" {
#define UART_LL_FSM_IDLE (0x0)
#define UART_LL_FSM_TX_WAIT_SEND (0xf)
#ifdef __cplusplus
extern "C" {
#endif
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1 << 0),
@@ -73,11 +73,11 @@ typedef enum {
FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
{
uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
(uart_num == 1) ? SYSTEM_UART1_RST : 0);
(uart_num == 1) ? SYSTEM_UART1_RST : 0);
uint32_t uart_en_bit = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
(uart_num == 1) ? SYSTEM_UART1_CLK_EN : 0);
(uart_num == 1) ? SYSTEM_UART1_CLK_EN : 0);
return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
}
/**
@@ -159,7 +159,6 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
hw->clk_conf.tx_sclk_en = 0;
}
/**
* @brief Set the UART source clock.
*
@@ -172,18 +171,18 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
switch (source_clk) {
case UART_SCLK_PLL_F40M:
hw->clk_conf.sclk_sel = 1;
break;
case UART_SCLK_RTC:
hw->clk_conf.sclk_sel = 2;
break;
case UART_SCLK_XTAL:
hw->clk_conf.sclk_sel = 3;
break;
default:
// Invalid UART clock source
abort();
case UART_SCLK_PLL_F40M:
hw->clk_conf.sclk_sel = 1;
break;
case UART_SCLK_RTC:
hw->clk_conf.sclk_sel = 2;
break;
case UART_SCLK_XTAL:
hw->clk_conf.sclk_sel = 3;
break;
default:
// Invalid UART clock source
abort();
}
}
@@ -198,16 +197,16 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
switch (hw->clk_conf.sclk_sel) {
default:
case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_PLL_F40M;
break;
case 2:
*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
break;
case 3:
*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
break;
default:
case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_PLL_F40M;
break;
case 2:
*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
break;
case 3:
*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
break;
}
}
@@ -257,7 +256,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
typeof(hw->clk_div) div_reg;
div_reg.val = hw->clk_div.val;
return ((sclk_freq << 4)) /
(((div_reg.div_int << 4) | div_reg.div_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1));
(((div_reg.div_int << 4) | div_reg.div_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1));
}
/**
@@ -826,22 +825,22 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
{
switch (mode) {
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
uart_ll_set_mode_irda(hw);
break;
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
uart_ll_set_mode_irda(hw);
break;
}
}
@@ -937,7 +936,7 @@ FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
{
hw->flow_conf.force_xon = 1;
if(!always_on) {
if (!always_on) {
hw->flow_conf.force_xon = 0;
}
}
@@ -977,7 +976,7 @@ FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
{
uint16_t tout_val = tout_thrd;
if(tout_thrd > 0) {
if (tout_thrd > 0) {
hw->mem_conf.rx_tout_thrhd = tout_val;
hw->conf1.rx_tout_en = 1;
} else {
@@ -995,7 +994,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
{
uint16_t tout_thrd = 0;
if(hw->conf1.rx_tout_en > 0) {
if (hw->conf1.rx_tout_en > 0) {
tout_thrd = hw->mem_conf.rx_tout_thrhd;
}
return tout_thrd;
components/soc/esp32c3/uart_periph.c → components/esp_hal_uart/esp32c2/uart_periph.c
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
/*
Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
components/hal/esp32c3/include/hal/uart_ll.h → components/esp_hal_uart/esp32c3/include/hal/uart_ll.h
+48 -49
View File
@@ -7,7 +7,6 @@
// The LL layer for UART register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdlib.h>
@@ -20,10 +19,6 @@
#include "soc/dport_access.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
@@ -39,6 +34,10 @@ extern "C" {
#define UART_LL_FSM_IDLE (0x0)
#define UART_LL_FSM_TX_WAIT_SEND (0xf)
#ifdef __cplusplus
extern "C" {
#endif
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1 << 0),
@@ -73,11 +72,11 @@ typedef enum {
FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
{
uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
(uart_num == 1) ? SYSTEM_UART1_RST : 0);
(uart_num == 1) ? SYSTEM_UART1_RST : 0);
uint32_t uart_en_bit = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
(uart_num == 1) ? SYSTEM_UART1_CLK_EN : 0);
(uart_num == 1) ? SYSTEM_UART1_CLK_EN : 0);
return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
}
/**
@@ -178,18 +177,18 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
switch (source_clk) {
case UART_SCLK_APB:
hw->clk_conf.sclk_sel = 1;
break;
case UART_SCLK_RTC:
hw->clk_conf.sclk_sel = 2;
break;
case UART_SCLK_XTAL:
hw->clk_conf.sclk_sel = 3;
break;
default:
// Invalid UART clock source
abort();
case UART_SCLK_APB:
hw->clk_conf.sclk_sel = 1;
break;
case UART_SCLK_RTC:
hw->clk_conf.sclk_sel = 2;
break;
case UART_SCLK_XTAL:
hw->clk_conf.sclk_sel = 3;
break;
default:
// Invalid UART clock source
abort();
}
}
@@ -204,16 +203,16 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
switch (hw->clk_conf.sclk_sel) {
default:
case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_APB;
break;
case 2:
*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
break;
case 3:
*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
break;
default:
case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_APB;
break;
case 2:
*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
break;
case 3:
*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
break;
}
}
@@ -831,22 +830,22 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
{
switch (mode) {
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
uart_ll_set_mode_irda(hw);
break;
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
uart_ll_set_mode_irda(hw);
break;
}
}
@@ -942,7 +941,7 @@ FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
{
hw->flow_conf.force_xon = 1;
if(!always_on) {
if (!always_on) {
hw->flow_conf.force_xon = 0;
}
}
@@ -982,7 +981,7 @@ FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
{
uint16_t tout_val = tout_thrd;
if(tout_thrd > 0) {
if (tout_thrd > 0) {
hw->mem_conf.rx_tout_thrhd = tout_val;
hw->conf1.rx_tout_en = 1;
} else {
@@ -1000,7 +999,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
{
uint16_t tout_thrd = 0;
if(hw->conf1.rx_tout_en > 0) {
if (hw->conf1.rx_tout_en > 0) {
tout_thrd = hw->mem_conf.rx_tout_thrhd;
}
return tout_thrd;
components/hal/esp32c3/include/hal/uhci_ll.h → components/esp_hal_uart/esp32c3/include/hal/uhci_ll.h
+3 -3
View File
@@ -14,13 +14,13 @@
#include "soc/system_struct.h"
#include "hal/misc.h"
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
#ifdef __cplusplus
extern "C" {
#endif
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
typedef enum {
UHCI_RX_BREAK_CHR_EOF = 0x1,
UHCI_RX_IDLE_EOF = 0x2,
components/soc/esp32c2/uart_periph.c → components/esp_hal_uart/esp32c3/uart_periph.c
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
/*
Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
components/hal/esp32c5/include/hal/uart_ll.h → components/esp_hal_uart/esp32c5/include/hal/uart_ll.h
+58 -59
View File
@@ -21,10 +21,6 @@
#include "soc/lpperi_struct.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
#define LP_UART_LL_FIFO_DEF_LEN (SOC_LP_UART_FIFO_LEN)
@@ -68,6 +64,10 @@ extern "C" {
#define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix) \
(((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##field_suffix)
#ifdef __cplusplus
extern "C" {
#endif
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1 << 0),
@@ -944,7 +944,6 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_edge_thrd(uart_dev_t *hw, uint32_t wak
hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_WAKEUP_EDGE_THRED_MIN;
}
/**
* @brief Set the number of received data bytes for the RX FIFO threshold wake-up mode.
*
@@ -969,22 +968,22 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_fifo_thrd(uart_dev_t *hw, uint32_t wak
*/
FORCE_INLINE_ATTR void uart_ll_set_wakeup_mode(uart_dev_t *hw, uart_wakeup_mode_t mode)
{
switch(mode){
case UART_WK_MODE_ACTIVE_THRESH:
hw->sleep_conf2.wk_mode_sel = 0;
break;
case UART_WK_MODE_FIFO_THRESH:
hw->sleep_conf2.wk_mode_sel = 1;
break;
case UART_WK_MODE_START_BIT:
hw->sleep_conf2.wk_mode_sel = 2;
break;
case UART_WK_MODE_CHAR_SEQ:
hw->sleep_conf2.wk_mode_sel = 3;
break;
default:
abort();
break;
switch (mode) {
case UART_WK_MODE_ACTIVE_THRESH:
hw->sleep_conf2.wk_mode_sel = 0;
break;
case UART_WK_MODE_FIFO_THRESH:
hw->sleep_conf2.wk_mode_sel = 1;
break;
case UART_WK_MODE_START_BIT:
hw->sleep_conf2.wk_mode_sel = 2;
break;
case UART_WK_MODE_CHAR_SEQ:
hw->sleep_conf2.wk_mode_sel = 3;
break;
default:
abort();
break;
}
}
@@ -1026,24 +1025,24 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_char_seq_char_num(uart_dev_t *hw, uint
FORCE_INLINE_ATTR void uart_ll_set_char_seq_wk_char(uart_dev_t *hw, uint32_t char_position, char value)
{
switch (char_position) {
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
case 4:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char4, value);
break;
default:
abort();
break;
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
case 4:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char4, value);
break;
default:
abort();
break;
}
}
@@ -1187,26 +1186,26 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
{
switch (mode) {
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
// Only HP_UART support this mode
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
// Only HP_UART support this mode
uart_ll_set_mode_irda(hw);
break;
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
// Only HP_UART support this mode
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
// Only HP_UART support this mode
uart_ll_set_mode_irda(hw);
break;
}
}
components/hal/esp32c5/include/hal/uhci_ll.h → components/esp_hal_uart/esp32c5/include/hal/uhci_ll.h
+3 -3
View File
@@ -14,13 +14,13 @@
#include "soc/pcr_struct.h"
#include "hal/misc.h"
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
#ifdef __cplusplus
extern "C" {
#endif
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
typedef enum {
UHCI_RX_BREAK_CHR_EOF = 0x1,
UHCI_RX_IDLE_EOF = 0x2,
components/soc/esp32c5/uart_periph.c → components/esp_hal_uart/esp32c5/uart_periph.c
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
/*
Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
components/hal/esp32c6/include/hal/uart_ll.h → components/esp_hal_uart/esp32c6/include/hal/uart_ll.h
+58 -59
View File
@@ -21,10 +21,6 @@
#include "soc/lpperi_struct.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
#define LP_UART_LL_FIFO_DEF_LEN (SOC_LP_UART_FIFO_LEN)
@@ -68,6 +64,10 @@ extern "C" {
#define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix) \
(((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##field_suffix)
#ifdef __cplusplus
extern "C" {
#endif
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1 << 0),
@@ -925,7 +925,6 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_edge_thrd(uart_dev_t *hw, uint32_t wak
hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_WAKEUP_EDGE_THRED_MIN;
}
/**
* @brief Set the number of received data bytes for the RX FIFO threshold wake-up mode.
*
@@ -950,22 +949,22 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_fifo_thrd(uart_dev_t *hw, uint32_t wak
*/
FORCE_INLINE_ATTR void uart_ll_set_wakeup_mode(uart_dev_t *hw, uart_wakeup_mode_t mode)
{
switch(mode){
case UART_WK_MODE_ACTIVE_THRESH:
hw->sleep_conf2.wk_mode_sel = 0;
break;
case UART_WK_MODE_FIFO_THRESH:
hw->sleep_conf2.wk_mode_sel = 1;
break;
case UART_WK_MODE_START_BIT:
hw->sleep_conf2.wk_mode_sel = 2;
break;
case UART_WK_MODE_CHAR_SEQ:
hw->sleep_conf2.wk_mode_sel = 3;
break;
default:
abort();
break;
switch (mode) {
case UART_WK_MODE_ACTIVE_THRESH:
hw->sleep_conf2.wk_mode_sel = 0;
break;
case UART_WK_MODE_FIFO_THRESH:
hw->sleep_conf2.wk_mode_sel = 1;
break;
case UART_WK_MODE_START_BIT:
hw->sleep_conf2.wk_mode_sel = 2;
break;
case UART_WK_MODE_CHAR_SEQ:
hw->sleep_conf2.wk_mode_sel = 3;
break;
default:
abort();
break;
}
}
@@ -1007,24 +1006,24 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_char_seq_char_num(uart_dev_t *hw, uint
FORCE_INLINE_ATTR void uart_ll_set_char_seq_wk_char(uart_dev_t *hw, uint32_t char_position, char value)
{
switch (char_position) {
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
case 4:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char4, value);
break;
default:
abort();
break;
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
case 4:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char4, value);
break;
default:
abort();
break;
}
}
@@ -1168,26 +1167,26 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
{
switch (mode) {
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
// Only HP_UART support this mode
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
// Only HP_UART support this mode
uart_ll_set_mode_irda(hw);
break;
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
// Only HP_UART support this mode
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
// Only HP_UART support this mode
uart_ll_set_mode_irda(hw);
break;
}
}
components/hal/esp32c6/include/hal/uhci_ll.h → components/esp_hal_uart/esp32c6/include/hal/uhci_ll.h
+3 -3
View File
@@ -14,13 +14,13 @@
#include "soc/pcr_struct.h"
#include "hal/misc.h"
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
#ifdef __cplusplus
extern "C" {
#endif
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
typedef enum {
UHCI_RX_BREAK_CHR_EOF = 0x1,
UHCI_RX_IDLE_EOF = 0x2,
components/soc/esp32c6/uart_periph.c → components/esp_hal_uart/esp32c6/uart_periph.c
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
#include "soc/uart_reg.h"
/*
components/hal/esp32c61/include/hal/uart_ll.h → components/esp_hal_uart/esp32c61/include/hal/uart_ll.h
+79 -80
View File
@@ -7,7 +7,6 @@
// The LL layer for UART register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdlib.h>
@@ -21,10 +20,6 @@
#include "esp_attr.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
@@ -71,6 +66,10 @@ extern "C" {
((hw) == &UART1) ? PCR.uart1_##reg_suffix.uart1_##field_suffix : \
PCR.uart2_##reg_suffix.uart2_##field_suffix)
#ifdef __cplusplus
extern "C" {
#endif
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1 << 0),
@@ -216,18 +215,18 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_
{
uint32_t sel_value = 0;
switch (source_clk) {
case UART_SCLK_XTAL:
sel_value = 0;
break;
case UART_SCLK_RTC:
sel_value = 1;
break;
case UART_SCLK_PLL_F80M:
sel_value = 2;
break;
default:
// Invalid UART clock source
abort();
case UART_SCLK_XTAL:
sel_value = 0;
break;
case UART_SCLK_RTC:
sel_value = 1;
break;
case UART_SCLK_PLL_F80M:
sel_value = 2;
break;
default:
// Invalid UART clock source
abort();
}
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, sel_value);
}
@@ -243,16 +242,16 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
default:
case 0:
*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
break;
case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
break;
case 2:
*source_clk = (soc_module_clk_t)UART_SCLK_PLL_F80M;
break;
default:
case 0:
*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
break;
case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
break;
case 2:
*source_clk = (soc_module_clk_t)UART_SCLK_PLL_F80M;
break;
}
}
@@ -784,22 +783,22 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_fifo_thrd(uart_dev_t *hw, uint32_t wak
*/
FORCE_INLINE_ATTR void uart_ll_set_wakeup_mode(uart_dev_t *hw, uart_wakeup_mode_t mode)
{
switch(mode){
case UART_WK_MODE_ACTIVE_THRESH:
hw->sleep_conf2.wk_mode_sel = 0;
break;
case UART_WK_MODE_FIFO_THRESH:
hw->sleep_conf2.wk_mode_sel = 1;
break;
case UART_WK_MODE_START_BIT:
hw->sleep_conf2.wk_mode_sel = 2;
break;
case UART_WK_MODE_CHAR_SEQ:
hw->sleep_conf2.wk_mode_sel = 3;
break;
default:
abort();
break;
switch (mode) {
case UART_WK_MODE_ACTIVE_THRESH:
hw->sleep_conf2.wk_mode_sel = 0;
break;
case UART_WK_MODE_FIFO_THRESH:
hw->sleep_conf2.wk_mode_sel = 1;
break;
case UART_WK_MODE_START_BIT:
hw->sleep_conf2.wk_mode_sel = 2;
break;
case UART_WK_MODE_CHAR_SEQ:
hw->sleep_conf2.wk_mode_sel = 3;
break;
default:
abort();
break;
}
}
@@ -841,24 +840,24 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_char_seq_char_num(uart_dev_t *hw, uint
FORCE_INLINE_ATTR void uart_ll_set_char_seq_wk_char(uart_dev_t *hw, uint32_t char_position, char value)
{
switch (char_position) {
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
case 4:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char4, value);
break;
default:
abort();
break;
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
case 4:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char4, value);
break;
default:
abort();
break;
}
}
@@ -982,22 +981,22 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
{
switch (mode) {
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
uart_ll_set_mode_irda(hw);
break;
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
uart_ll_set_mode_irda(hw);
break;
}
}
@@ -1095,7 +1094,7 @@ FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
{
hw->swfc_conf0_sync.force_xon = 1;
uart_ll_update(hw);
if(!always_on) {
if (!always_on) {
hw->swfc_conf0_sync.force_xon = 0;
uart_ll_update(hw);
}
@@ -1141,7 +1140,7 @@ FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
{
uint16_t tout_val = tout_thrd;
if(tout_thrd > 0) {
if (tout_thrd > 0) {
hw->tout_conf_sync.rx_tout_thrhd = tout_val;
hw->tout_conf_sync.rx_tout_en = 1;
} else {
@@ -1160,7 +1159,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
{
uint16_t tout_thrd = 0;
if(hw->tout_conf_sync.rx_tout_en > 0) {
if (hw->tout_conf_sync.rx_tout_en > 0) {
tout_thrd = hw->tout_conf_sync.rx_tout_thrhd;
}
return tout_thrd;
components/soc/esp32c61/uart_periph.c → components/esp_hal_uart/esp32c61/uart_periph.c
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
#include "soc/uart_reg.h"
/*
components/hal/esp32h2/include/hal/uart_ll.h → components/esp_hal_uart/esp32h2/include/hal/uart_ll.h
+38 -40
View File
@@ -7,7 +7,6 @@
// The LL layer for UART register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdlib.h>
@@ -20,10 +19,6 @@
#include "soc/pcr_reg.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
@@ -64,6 +59,10 @@ extern "C" {
#define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix) \
(((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##field_suffix)
#ifdef __cplusplus
extern "C" {
#endif
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1 << 0),
@@ -764,22 +763,22 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_fifo_thrd(uart_dev_t *hw, uint32_t wak
*/
FORCE_INLINE_ATTR void uart_ll_set_wakeup_mode(uart_dev_t *hw, uart_wakeup_mode_t mode)
{
switch(mode){
case UART_WK_MODE_ACTIVE_THRESH:
hw->sleep_conf2.wk_mode_sel = 0;
break;
case UART_WK_MODE_FIFO_THRESH:
hw->sleep_conf2.wk_mode_sel = 1;
break;
case UART_WK_MODE_START_BIT:
hw->sleep_conf2.wk_mode_sel = 2;
break;
case UART_WK_MODE_CHAR_SEQ:
hw->sleep_conf2.wk_mode_sel = 3;
break;
default:
abort();
break;
switch (mode) {
case UART_WK_MODE_ACTIVE_THRESH:
hw->sleep_conf2.wk_mode_sel = 0;
break;
case UART_WK_MODE_FIFO_THRESH:
hw->sleep_conf2.wk_mode_sel = 1;
break;
case UART_WK_MODE_START_BIT:
hw->sleep_conf2.wk_mode_sel = 2;
break;
case UART_WK_MODE_CHAR_SEQ:
hw->sleep_conf2.wk_mode_sel = 3;
break;
default:
abort();
break;
}
}
@@ -821,29 +820,28 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_char_seq_char_num(uart_dev_t *hw, uint
FORCE_INLINE_ATTR void uart_ll_set_char_seq_wk_char(uart_dev_t *hw, uint32_t char_position, char value)
{
switch (char_position) {
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
case 4:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char4, value);
break;
default:
abort();
break;
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
case 4:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char4, value);
break;
default:
abort();
break;
}
}
/**
* @brief Enable/disable the UART pad clock in sleep_state
*
components/hal/esp32h2/include/hal/uhci_ll.h → components/esp_hal_uart/esp32h2/include/hal/uhci_ll.h
+3 -3
View File
@@ -11,13 +11,13 @@
#include "soc/pcr_struct.h"
#include "hal/misc.h"
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
#ifdef __cplusplus
extern "C" {
#endif
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
typedef enum {
UHCI_RX_BREAK_CHR_EOF = 0x1,
UHCI_RX_IDLE_EOF = 0x2,
components/soc/esp32h2/uart_periph.c → components/esp_hal_uart/esp32h2/uart_periph.c
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
#include "soc/uart_reg.h"
/*
components/hal/esp32h21/include/hal/uart_ll.h → components/esp_hal_uart/esp32h21/include/hal/uart_ll.h
+75 -78
View File
@@ -7,7 +7,6 @@
// The LL layer for UART register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdlib.h>
@@ -20,10 +19,6 @@
#include "soc/pcr_reg.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
@@ -64,6 +59,9 @@ extern "C" {
#define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix) \
(((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##field_suffix)
#ifdef __cplusplus
extern "C" {
#endif
// Define UART interrupts
typedef enum {
@@ -198,18 +196,18 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
switch (source_clk) {
case UART_SCLK_PLL_F48M:
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1);
break;
case UART_SCLK_RTC:
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 2);
break;
case UART_SCLK_XTAL:
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 3);
break;
default:
// Invalid UART clock source
abort();
case UART_SCLK_PLL_F48M:
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 1);
break;
case UART_SCLK_RTC:
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 2);
break;
case UART_SCLK_XTAL:
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_sel, 3);
break;
default:
// Invalid UART clock source
abort();
}
}
@@ -224,16 +222,16 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
default:
case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_PLL_F48M;
break;
case 2:
*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
break;
case 3:
*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
break;
default:
case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_PLL_F48M;
break;
case 2:
*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
break;
case 3:
*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
break;
}
}
@@ -765,22 +763,22 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_fifo_thrd(uart_dev_t *hw, uint32_t wak
*/
FORCE_INLINE_ATTR void uart_ll_set_wakeup_mode(uart_dev_t *hw, uart_wakeup_mode_t mode)
{
switch(mode){
case UART_WK_MODE_ACTIVE_THRESH:
hw->sleep_conf2.wk_mode_sel = 0;
break;
case UART_WK_MODE_FIFO_THRESH:
hw->sleep_conf2.wk_mode_sel = 1;
break;
case UART_WK_MODE_START_BIT:
hw->sleep_conf2.wk_mode_sel = 2;
break;
case UART_WK_MODE_CHAR_SEQ:
hw->sleep_conf2.wk_mode_sel = 3;
break;
default:
abort();
break;
switch (mode) {
case UART_WK_MODE_ACTIVE_THRESH:
hw->sleep_conf2.wk_mode_sel = 0;
break;
case UART_WK_MODE_FIFO_THRESH:
hw->sleep_conf2.wk_mode_sel = 1;
break;
case UART_WK_MODE_START_BIT:
hw->sleep_conf2.wk_mode_sel = 2;
break;
case UART_WK_MODE_CHAR_SEQ:
hw->sleep_conf2.wk_mode_sel = 3;
break;
default:
abort();
break;
}
}
@@ -822,29 +820,28 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_char_seq_char_num(uart_dev_t *hw, uint
FORCE_INLINE_ATTR void uart_ll_set_char_seq_wk_char(uart_dev_t *hw, uint32_t char_position, char value)
{
switch (char_position) {
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
case 4:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char4, value);
break;
default:
abort();
break;
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
case 4:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char4, value);
break;
default:
abort();
break;
}
}
/**
* @brief Enable/disable the UART pad clock in sleep_state
*
@@ -964,22 +961,22 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
{
switch (mode) {
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
uart_ll_set_mode_irda(hw);
break;
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
uart_ll_set_mode_irda(hw);
break;
}
}
components/soc/esp32h21/uart_periph.c → components/esp_hal_uart/esp32h21/uart_periph.c
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
#include "soc/uart_reg.h"
/*
components/hal/esp32h4/include/hal/uart_ll.h → components/esp_hal_uart/esp32h4/include/hal/uart_ll.h
+58 -58
View File
@@ -18,10 +18,6 @@
#include "soc/pcr_reg.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
@@ -60,6 +56,10 @@ extern "C" {
#define UART_LL_PCR_REG_GET(hw, reg_suffix, field_suffix) \
(((hw) == &UART0) ? PCR.uart0_##reg_suffix.uart0_##field_suffix : PCR.uart1_##reg_suffix.uart1_##field_suffix)
#ifdef __cplusplus
extern "C" {
#endif
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1 << 0),
@@ -780,22 +780,22 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_fifo_thrd(uart_dev_t *hw, uint32_t wak
*/
FORCE_INLINE_ATTR void uart_ll_set_wakeup_mode(uart_dev_t *hw, uart_wakeup_mode_t mode)
{
switch(mode){
case UART_WK_MODE_ACTIVE_THRESH:
hw->sleep_conf2.wk_mode_sel = 0;
break;
// case UART_WK_MODE_FIFO_THRESH: // TODO: [ESP32H4] PM-457
// hw->sleep_conf2.wk_mode_sel = 1;
// break;
// case UART_WK_MODE_START_BIT:
// hw->sleep_conf2.wk_mode_sel = 2;
// break;
// case UART_WK_MODE_CHAR_SEQ:
// hw->sleep_conf2.wk_mode_sel = 3;
// break;
default:
abort();
break;
switch (mode) {
case UART_WK_MODE_ACTIVE_THRESH:
hw->sleep_conf2.wk_mode_sel = 0;
break;
// case UART_WK_MODE_FIFO_THRESH: // TODO: [ESP32H4] PM-457
// hw->sleep_conf2.wk_mode_sel = 1;
// break;
// case UART_WK_MODE_START_BIT:
// hw->sleep_conf2.wk_mode_sel = 2;
// break;
// case UART_WK_MODE_CHAR_SEQ:
// hw->sleep_conf2.wk_mode_sel = 3;
// break;
default:
abort();
break;
}
}
@@ -837,24 +837,24 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_char_seq_char_num(uart_dev_t *hw, uint
FORCE_INLINE_ATTR void uart_ll_set_char_seq_wk_char(uart_dev_t *hw, uint32_t char_position, char value)
{
switch (char_position) {
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
case 4:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char4, value);
break;
default:
abort();
break;
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
case 4:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char4, value);
break;
default:
abort();
break;
}
}
@@ -978,26 +978,26 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
{
switch (mode) {
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
// Only HP_UART support this mode
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
// Only HP_UART support this mode
uart_ll_set_mode_irda(hw);
break;
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
// Only HP_UART support this mode
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
// Only HP_UART support this mode
uart_ll_set_mode_irda(hw);
break;
}
}
components/soc/esp32h4/uart_periph.c → components/esp_hal_uart/esp32h4/uart_periph.c
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
#include "soc/uart_reg.h"
/*
components/hal/esp32p4/include/hal/uart_ll.h → components/esp_hal_uart/esp32p4/include/hal/uart_ll.h
+65 -67
View File
@@ -7,7 +7,6 @@
// The LL layer for UART register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdint.h>
@@ -23,10 +22,6 @@
#include "soc/lp_clkrst_struct.h"
#include "soc/lpperi_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
#define LP_UART_LL_FIFO_DEF_LEN (SOC_LP_UART_FIFO_LEN)
@@ -52,6 +47,10 @@ extern "C" {
#define UART_LL_FSM_IDLE (0x0)
#define UART_LL_FSM_TX_WAIT_SEND (0xf)
#ifdef __cplusplus
extern "C" {
#endif
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1 << 0),
@@ -107,10 +106,10 @@ FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *sou
case 1:
*source_clk = (soc_module_clk_t)LP_UART_SCLK_XTAL_D2;
break;
// TODO: IDF-9581
// case 2:
// *source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_PLL;
// break;
// TODO: IDF-9581
// case 2:
// *source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_PLL;
// break;
}
}
@@ -1066,7 +1065,6 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_edge_thrd(uart_dev_t *hw, uint32_t wak
hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_WAKEUP_EDGE_THRED_MIN;
}
/**
* @brief Set the number of received data bytes for the RX FIFO threshold wake-up mode.
*
@@ -1091,22 +1089,22 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_fifo_thrd(uart_dev_t *hw, uint32_t wak
*/
FORCE_INLINE_ATTR void uart_ll_set_wakeup_mode(uart_dev_t *hw, uart_wakeup_mode_t mode)
{
switch(mode){
case UART_WK_MODE_ACTIVE_THRESH:
hw->sleep_conf2.wk_mode_sel = 0;
break;
case UART_WK_MODE_FIFO_THRESH:
hw->sleep_conf2.wk_mode_sel = 1;
break;
case UART_WK_MODE_START_BIT:
hw->sleep_conf2.wk_mode_sel = 2;
break;
case UART_WK_MODE_CHAR_SEQ:
hw->sleep_conf2.wk_mode_sel = 3;
break;
default:
abort();
break;
switch (mode) {
case UART_WK_MODE_ACTIVE_THRESH:
hw->sleep_conf2.wk_mode_sel = 0;
break;
case UART_WK_MODE_FIFO_THRESH:
hw->sleep_conf2.wk_mode_sel = 1;
break;
case UART_WK_MODE_START_BIT:
hw->sleep_conf2.wk_mode_sel = 2;
break;
case UART_WK_MODE_CHAR_SEQ:
hw->sleep_conf2.wk_mode_sel = 3;
break;
default:
abort();
break;
}
}
@@ -1148,24 +1146,24 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_char_seq_char_num(uart_dev_t *hw, uint
FORCE_INLINE_ATTR void uart_ll_set_char_seq_wk_char(uart_dev_t *hw, uint32_t char_position, char value)
{
switch (char_position) {
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
case 4:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char4, value);
break;
default:
abort();
break;
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
case 4:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char4, value);
break;
default:
abort();
break;
}
}
@@ -1325,26 +1323,26 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
{
switch (mode) {
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
// Only HP_UART support this mode
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
// Only HP_UART support this mode
uart_ll_set_mode_irda(hw);
break;
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
// Only HP_UART support this mode
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
// Only HP_UART support this mode
uart_ll_set_mode_irda(hw);
break;
}
}
@@ -1442,7 +1440,7 @@ FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
{
hw->swfc_conf0_sync.force_xon = 1;
uart_ll_update(hw);
if(!always_on) {
if (!always_on) {
hw->swfc_conf0_sync.force_xon = 0;
uart_ll_update(hw);
}
@@ -1491,7 +1489,7 @@ FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
{
uint16_t tout_val = tout_thrd;
if(tout_thrd > 0) {
if (tout_thrd > 0) {
hw->tout_conf_sync.rx_tout_thrhd = tout_val;
hw->tout_conf_sync.rx_tout_en = 1;
} else {
@@ -1510,7 +1508,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
{
uint16_t tout_thrd = 0;
if(hw->tout_conf_sync.rx_tout_en > 0) {
if (hw->tout_conf_sync.rx_tout_en > 0) {
tout_thrd = hw->tout_conf_sync.rx_tout_thrhd;
}
return tout_thrd;
components/hal/esp32p4/include/hal/uhci_ll.h → components/esp_hal_uart/esp32p4/include/hal/uhci_ll.h
+3 -3
View File
@@ -14,13 +14,13 @@
#include "soc/hp_sys_clkrst_struct.h"
#include "hal/misc.h"
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
#ifdef __cplusplus
extern "C" {
#endif
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
typedef enum {
UHCI_RX_BREAK_CHR_EOF = 0x1,
UHCI_RX_IDLE_EOF = 0x2,
components/soc/esp32p4/uart_periph.c → components/esp_hal_uart/esp32p4/uart_periph.c
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
#include "soc/lp_gpio_sig_map.h"
#include "soc/uart_reg.h"
components/hal/esp32s2/include/hal/uart_ll.h → components/esp_hal_uart/esp32s2/include/hal/uart_ll.h
+70 -71
View File
@@ -7,7 +7,6 @@
// The LL layer for UART register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdlib.h>
@@ -19,10 +18,6 @@
#include "soc/dport_reg.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
@@ -35,27 +30,31 @@ extern "C" {
#define UART_LL_INTR_MASK (0x7ffff) //All interrupt mask
#ifdef __cplusplus
extern "C" {
#endif
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1<<0),
UART_INTR_TXFIFO_EMPTY = (0x1<<1),
UART_INTR_PARITY_ERR = (0x1<<2),
UART_INTR_FRAM_ERR = (0x1<<3),
UART_INTR_RXFIFO_OVF = (0x1<<4),
UART_INTR_DSR_CHG = (0x1<<5),
UART_INTR_CTS_CHG = (0x1<<6),
UART_INTR_BRK_DET = (0x1<<7),
UART_INTR_RXFIFO_TOUT = (0x1<<8),
UART_INTR_SW_XON = (0x1<<9),
UART_INTR_SW_XOFF = (0x1<<10),
UART_INTR_GLITCH_DET = (0x1<<11),
UART_INTR_TX_BRK_DONE = (0x1<<12),
UART_INTR_TX_BRK_IDLE = (0x1<<13),
UART_INTR_TX_DONE = (0x1<<14),
UART_INTR_RS485_PARITY_ERR = (0x1<<15),
UART_INTR_RS485_FRM_ERR = (0x1<<16),
UART_INTR_RS485_CLASH = (0x1<<17),
UART_INTR_CMD_CHAR_DET = (0x1<<18),
UART_INTR_RXFIFO_FULL = (0x1 << 0),
UART_INTR_TXFIFO_EMPTY = (0x1 << 1),
UART_INTR_PARITY_ERR = (0x1 << 2),
UART_INTR_FRAM_ERR = (0x1 << 3),
UART_INTR_RXFIFO_OVF = (0x1 << 4),
UART_INTR_DSR_CHG = (0x1 << 5),
UART_INTR_CTS_CHG = (0x1 << 6),
UART_INTR_BRK_DET = (0x1 << 7),
UART_INTR_RXFIFO_TOUT = (0x1 << 8),
UART_INTR_SW_XON = (0x1 << 9),
UART_INTR_SW_XOFF = (0x1 << 10),
UART_INTR_GLITCH_DET = (0x1 << 11),
UART_INTR_TX_BRK_DONE = (0x1 << 12),
UART_INTR_TX_BRK_IDLE = (0x1 << 13),
UART_INTR_TX_DONE = (0x1 << 14),
UART_INTR_RS485_PARITY_ERR = (0x1 << 15),
UART_INTR_RS485_FRM_ERR = (0x1 << 16),
UART_INTR_RS485_CLASH = (0x1 << 17),
UART_INTR_CMD_CHAR_DET = (0x1 << 18),
UART_INTR_WAKEUP = (0x1 << 19),
} uart_intr_t;
@@ -69,11 +68,11 @@ typedef enum {
FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
{
uint32_t uart_rst_bit = ((uart_num == 0) ? DPORT_UART_RST :
(uart_num == 1) ? DPORT_UART1_RST : 0);
(uart_num == 1) ? DPORT_UART1_RST : 0);
uint32_t uart_en_bit = ((uart_num == 0) ? DPORT_UART_CLK_EN :
(uart_num == 1) ? DPORT_UART1_CLK_EN : 0);
(uart_num == 1) ? DPORT_UART1_CLK_EN : 0);
return DPORT_REG_GET_BIT(DPORT_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
DPORT_REG_GET_BIT(DPORT_PERIP_CLK_EN_REG, uart_en_bit) != 0;
}
/**
@@ -162,15 +161,15 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
switch (source_clk) {
case UART_SCLK_REF_TICK:
hw->conf0.tick_ref_always_on = 0;
break;
case UART_SCLK_APB:
hw->conf0.tick_ref_always_on = 1;
break;
default:
// Invalid UART clock source
abort();
case UART_SCLK_REF_TICK:
hw->conf0.tick_ref_always_on = 0;
break;
case UART_SCLK_APB:
hw->conf0.tick_ref_always_on = 1;
break;
default:
// Invalid UART clock source
abort();
}
}
@@ -185,13 +184,13 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
switch (hw->conf0.tick_ref_always_on) {
default:
case 0:
*source_clk = (soc_module_clk_t)UART_SCLK_REF_TICK;
break;
case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_APB;
break;
default:
case 0:
*source_clk = (soc_module_clk_t)UART_SCLK_REF_TICK;
break;
case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_APB;
break;
}
}
@@ -331,7 +330,7 @@ FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_
{
//Get the UART fifo addr, ESP32-S2 have 2 UART
uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_AHB_REG(0) : UART_FIFO_AHB_REG(1);
for(uint32_t i = 0; i < rd_len; i++) {
for (uint32_t i = 0; i < rd_len; i++) {
buf[i] = READ_PERI_REG(fifo_addr);
}
}
@@ -349,7 +348,7 @@ FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf,
{
//Get the UART fifo addr, ESP32-S2 have 2 UART
uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_AHB_REG(0) : UART_FIFO_AHB_REG(1);
for(uint32_t i = 0; i < wr_len; i++) {
for (uint32_t i = 0; i < wr_len; i++) {
WRITE_PERI_REG(fifo_addr, buf[i]);
}
}
@@ -440,7 +439,7 @@ FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *s
*/
FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
{
if(parity_mode != UART_PARITY_DISABLE) {
if (parity_mode != UART_PARITY_DISABLE) {
hw->conf0.parity = parity_mode & 0x1;
}
hw->conf0.parity_en = (parity_mode >> 1) & 0x1;
@@ -456,7 +455,7 @@ FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_m
*/
FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
{
if(hw->conf0.parity_en) {
if (hw->conf0.parity_en) {
*parity_mode = (uart_parity_t)(0x2 | hw->conf0.parity);
} else {
*parity_mode = UART_PARITY_DISABLE;
@@ -528,7 +527,7 @@ FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num
*/
FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
{
if(break_num > 0) {
if (break_num > 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->idle_conf, tx_brk_num, break_num);
hw->conf0.txd_brk = 1;
} else {
@@ -548,13 +547,13 @@ FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
{
//only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
if(flow_ctrl & UART_HW_FLOWCTRL_RTS) {
if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
hw->mem_conf.rx_flow_thrhd = rx_thrs;
hw->conf1.rx_flow_en = 1;
} else {
hw->conf1.rx_flow_en = 0;
}
if(flow_ctrl & UART_HW_FLOWCTRL_CTS) {
if (flow_ctrl & UART_HW_FLOWCTRL_CTS) {
hw->conf0.tx_flow_en = 1;
} else {
hw->conf0.tx_flow_en = 0;
@@ -572,10 +571,10 @@ FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcont
FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
{
*flow_ctrl = UART_HW_FLOWCTRL_DISABLE;
if(hw->conf1.rx_flow_en) {
if (hw->conf1.rx_flow_en) {
*flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_RTS);
}
if(hw->conf0.tx_flow_en) {
if (hw->conf0.tx_flow_en) {
*flow_ctrl = (uart_hw_flowcontrol_t)((unsigned int)(*flow_ctrl) | (unsigned int)UART_HW_FLOWCTRL_CTS);
}
}
@@ -591,7 +590,7 @@ FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcont
*/
FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
{
if(sw_flow_ctrl_en) {
if (sw_flow_ctrl_en) {
hw->flow_conf.xonoff_del = 1;
hw->flow_conf.sw_flow_con_en = 1;
hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd;
@@ -798,22 +797,22 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
{
switch (mode) {
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
uart_ll_set_mode_irda(hw);
break;
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
uart_ll_set_mode_irda(hw);
break;
}
}
@@ -941,7 +940,7 @@ FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
{
uint16_t tout_val = tout_thrd;
if(tout_thrd > 0) {
if (tout_thrd > 0) {
hw->mem_conf.rx_tout_thrhd = tout_val;
hw->conf1.rx_tout_en = 1;
} else {
@@ -959,7 +958,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
{
uint16_t tout_thrd = 0;
if(hw->conf1.rx_tout_en > 0) {
if (hw->conf1.rx_tout_en > 0) {
tout_thrd = hw->mem_conf.rx_tout_thrhd;
}
return tout_thrd;
components/soc/esp32s2/uart_periph.c → components/esp_hal_uart/esp32s2/uart_periph.c
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
/*
Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
components/hal/esp32s3/include/hal/uart_ll.h → components/esp_hal_uart/esp32s3/include/hal/uart_ll.h
+36 -37
View File
@@ -7,7 +7,6 @@
// The LL layer for UART register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include <stdlib.h>
@@ -20,10 +19,6 @@
#include "soc/dport_access.h"
#include "esp_attr.h"
#ifdef __cplusplus
extern "C" {
#endif
// The default fifo depth
#define UART_LL_FIFO_DEF_LEN (SOC_UART_FIFO_LEN)
// Get UART hardware instance with giving uart num
@@ -39,6 +34,10 @@ extern "C" {
#define UART_LL_FSM_IDLE (0x0)
#define UART_LL_FSM_TX_WAIT_SEND (0xf)
#ifdef __cplusplus
extern "C" {
#endif
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1 << 0),
@@ -73,13 +72,13 @@ typedef enum {
FORCE_INLINE_ATTR bool uart_ll_is_enabled(uint32_t uart_num)
{
uint32_t uart_rst_bit = ((uart_num == 0) ? SYSTEM_UART_RST :
(uart_num == 1) ? SYSTEM_UART1_RST :
(uart_num == 2) ? SYSTEM_UART2_RST : 0);
(uart_num == 1) ? SYSTEM_UART1_RST :
(uart_num == 2) ? SYSTEM_UART2_RST : 0);
uint32_t uart_en_bit = ((uart_num == 0) ? SYSTEM_UART_CLK_EN :
(uart_num == 1) ? SYSTEM_UART1_CLK_EN :
(uart_num == 2) ? SYSTEM_UART2_CLK_EN : 0);
(uart_num == 1) ? SYSTEM_UART1_CLK_EN :
(uart_num == 2) ? SYSTEM_UART2_CLK_EN : 0);
return DPORT_REG_GET_BIT(SYSTEM_PERIP_RST_EN0_REG, uart_rst_bit) == 0 &&
DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
DPORT_REG_GET_BIT(SYSTEM_PERIP_CLK_EN0_REG, uart_en_bit) != 0;
}
/**
@@ -182,18 +181,18 @@ FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
switch (source_clk) {
case UART_SCLK_APB:
hw->clk_conf.sclk_sel = 1;
break;
case UART_SCLK_RTC:
hw->clk_conf.sclk_sel = 2;
break;
case UART_SCLK_XTAL:
hw->clk_conf.sclk_sel = 3;
break;
default:
// Invalid UART clock source
abort();
case UART_SCLK_APB:
hw->clk_conf.sclk_sel = 1;
break;
case UART_SCLK_RTC:
hw->clk_conf.sclk_sel = 2;
break;
case UART_SCLK_XTAL:
hw->clk_conf.sclk_sel = 3;
break;
default:
// Invalid UART clock source
abort();
}
}
@@ -208,16 +207,16 @@ FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
switch (hw->clk_conf.sclk_sel) {
default:
case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_APB;
break;
case 2:
*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
break;
case 3:
*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
break;
default:
case 1:
*source_clk = (soc_module_clk_t)UART_SCLK_APB;
break;
case 2:
*source_clk = (soc_module_clk_t)UART_SCLK_RTC;
break;
case 3:
*source_clk = (soc_module_clk_t)UART_SCLK_XTAL;
break;
}
}
@@ -267,7 +266,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
uart_clkdiv_reg_t div_reg;
div_reg.val = hw->clkdiv.val;
return ((sclk_freq << 4)) /
(((div_reg.clkdiv << 4) | div_reg.clkdiv_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1));
(((div_reg.clkdiv << 4) | div_reg.clkdiv_frag) * (HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1));
}
/**
@@ -742,7 +741,7 @@ FORCE_INLINE_ATTR void _uart_ll_enable_pad_sleep_clock(uart_dev_t *hw, bool enab
FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw)
{
hw->rs485_conf.rs485_en = 0;
hw->rs485_conf.rs485tx_rx_en= 0;
hw->rs485_conf.rs485tx_rx_en = 0;
hw->rs485_conf.rs485rxby_tx_en = 0;
hw->conf0.irda_en = 0;
}
@@ -780,7 +779,7 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
// This is to void collision
hw->rs485_conf.rs485rxby_tx_en = 1;
hw->conf0.irda_en = 0;
hw->rs485_conf.rs485_en= 1;
hw->rs485_conf.rs485_en = 1;
}
/**
@@ -971,7 +970,7 @@ FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
{
uint16_t tout_val = tout_thrd;
if(tout_thrd > 0) {
if (tout_thrd > 0) {
hw->mem_conf.rx_tout_thrhd = tout_val;
hw->conf1.rx_tout_en = 1;
} else {
@@ -989,7 +988,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
{
uint16_t tout_thrd = 0;
if(hw->conf1.rx_tout_en > 0) {
if (hw->conf1.rx_tout_en > 0) {
tout_thrd = hw->mem_conf.rx_tout_thrhd;
}
return tout_thrd;
components/hal/esp32s3/include/hal/uhci_ll.h → components/esp_hal_uart/esp32s3/include/hal/uhci_ll.h
+3 -3
View File
@@ -14,13 +14,13 @@
#include "soc/system_struct.h"
#include "hal/misc.h"
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
#ifdef __cplusplus
extern "C" {
#endif
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
typedef enum {
UHCI_RX_BREAK_CHR_EOF = 0x1,
UHCI_RX_IDLE_EOF = 0x2,
components/soc/esp32s3/uart_periph.c → components/esp_hal_uart/esp32s3/uart_periph.c
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
/*
Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc
components/hal/esp32s31/include/hal/uart_ll.h → components/esp_hal_uart/esp32s31/include/hal/uart_ll.h
+42 -46
View File
@@ -7,7 +7,6 @@
// The LL layer for UART register operations.
// Note that most of the register operations in this layer are non-atomic operations.
#pragma once
#include "esp_attr.h"
@@ -24,10 +23,6 @@
#include "soc/lp_system_struct.h"
#include "soc/hp_alive_sys_struct.h"
#ifdef __cplusplus
extern "C" {
#endif
// TODO: [ESP32S31] IDF-14789
// The default fifo depth
@@ -54,6 +49,10 @@ extern "C" {
#define UART_LL_FSM_IDLE (0x0)
#define UART_LL_FSM_TX_WAIT_SEND (0xf)
#ifdef __cplusplus
extern "C" {
#endif
// Define UART interrupts
typedef enum {
UART_INTR_RXFIFO_FULL = (0x1 << 0),
@@ -103,7 +102,6 @@ FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *sou
// TODO: [ESP32S31] IDF-14789
}
/**
* @brief Configure the lp uart baud-rate.
*
@@ -458,7 +456,6 @@ FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint3
#define _uart_ll_set_baudrate(...) uart_ll_set_baudrate(__VA_ARGS__)
/**
* @brief Get the current baud-rate.
*
@@ -950,7 +947,6 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_edge_thrd(uart_dev_t *hw, uint32_t wak
hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_WAKEUP_EDGE_THRED_MIN;
}
/**
* @brief Set the number of received data bytes for the RX FIFO threshold wake-up mode.
*
@@ -1016,21 +1012,21 @@ FORCE_INLINE_ATTR void uart_ll_set_wakeup_char_seq_char_num(uart_dev_t *hw, uint
FORCE_INLINE_ATTR void uart_ll_set_char_seq_wk_char(uart_dev_t *hw, uint32_t char_position, char value)
{
switch (char_position) {
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
default:
abort();
break;
case 0:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf1, wk_char0, value);
break;
case 1:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char1, value);
break;
case 2:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char2, value);
break;
case 3:
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->sleep_conf0, wk_char3, value);
break;
default:
abort();
break;
}
}
@@ -1182,26 +1178,26 @@ FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
{
switch (mode) {
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
// Only HP_UART support this mode
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
// Only HP_UART support this mode
uart_ll_set_mode_irda(hw);
break;
default:
case UART_MODE_UART:
uart_ll_set_mode_normal(hw);
break;
case UART_MODE_RS485_COLLISION_DETECT:
// Only HP_UART support this mode
uart_ll_set_mode_collision_detect(hw);
break;
case UART_MODE_RS485_APP_CTRL:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_app_ctrl(hw);
break;
case UART_MODE_RS485_HALF_DUPLEX:
// Only HP_UART support this mode
uart_ll_set_mode_rs485_half_duplex(hw);
break;
case UART_MODE_IRDA:
// Only HP_UART support this mode
uart_ll_set_mode_irda(hw);
break;
}
}
@@ -1299,7 +1295,7 @@ FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
{
hw->swfc_conf0_sync.force_xon = 1;
uart_ll_update(hw);
if(!always_on) {
if (!always_on) {
hw->swfc_conf0_sync.force_xon = 0;
uart_ll_update(hw);
}
@@ -1348,7 +1344,7 @@ FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
{
uint16_t tout_val = tout_thrd;
if(tout_thrd > 0) {
if (tout_thrd > 0) {
hw->tout_conf_sync.rx_tout_thrhd = tout_val;
hw->tout_conf_sync.rx_tout_en = 1;
} else {
@@ -1367,7 +1363,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
{
uint16_t tout_thrd = 0;
if(hw->tout_conf_sync.rx_tout_en > 0) {
if (hw->tout_conf_sync.rx_tout_en > 0) {
tout_thrd = hw->tout_conf_sync.rx_tout_thrhd;
}
return tout_thrd;
components/soc/esp32s31/uart_periph.c → components/esp_hal_uart/esp32s31/uart_periph.c
+2 -2
View File
@@ -1,10 +1,10 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
#include "soc/lp_gpio_sig_map.h"
#include "soc/uart_reg.h"
components/hal/include/hal/uart_hal.h → components/esp_hal_uart/include/hal/uart_hal.h
+3 -4
View File
@@ -15,13 +15,13 @@
#pragma once
#include "hal/uart_ll.h"
#include "hal/uart_types.h"
#ifdef __cplusplus
extern "C" {
#endif
#include "hal/uart_ll.h"
#include "hal/uart_types.h"
/**
* Context that should be maintained by both the driver and the HAL
*/
@@ -115,7 +115,6 @@ typedef struct {
*/
#define uart_hal_get_intr_status_reg(hal) uart_ll_get_intr_status_reg((hal)->dev)
/**
* @brief Get the UART pattern char configuration
*
components/soc/include/soc/uart_periph.h → components/esp_hal_uart/include/hal/uart_periph.h
+2 -2
View File
@@ -1,7 +1,7 @@
/*
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
@@ -53,7 +53,7 @@ typedef struct {
typedef struct {
const uart_periph_sig_t pins[SOC_UART_PERIPH_SIGNAL_MAX];
const uint8_t irq;
const int irq;
} uart_signal_conn_t;
extern const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM];
components/hal/include/hal/uart_types.h → components/esp_hal_uart/include/hal/uart_types.h
+4 -4
View File
@@ -6,16 +6,16 @@
#pragma once
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#include <stdbool.h>
#include "soc/soc_caps.h"
#include "soc/clk_tree_defs.h"
#include "esp_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief UART port number, can be UART_NUM_0 ~ (UART_NUM_MAX -1).
*/
components/hal/include/hal/uhci_hal.h → components/esp_hal_uart/include/hal/uhci_hal.h
View File
components/soc/include/soc/uhci_periph.h → components/esp_hal_uart/include/hal/uhci_periph.h
+1 -1
View File
@@ -1,7 +1,7 @@
/*
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
components/hal/include/hal/uhci_types.h → components/esp_hal_uart/include/hal/uhci_types.h
View File
components/hal/linux/include/hal/uart_ll.h → components/esp_hal_uart/linux/include/hal/uart_ll.h
View File
components/hal/uart_hal.c → components/esp_hal_uart/uart_hal.c
+1 -2
View File
@@ -6,7 +6,6 @@
// The HAL layer for UART (common part)
#include "hal/uart_hal.h"
#include "soc/soc_caps.h"
void uart_hal_get_sclk(uart_hal_context_t *hal, soc_module_clk_t *sclk)
{
@@ -95,7 +94,7 @@ void uart_hal_set_wakeup_edge_thrd(uart_hal_context_t *hal, uint32_t wakeup_thrd
void uart_hal_get_wakeup_edge_thrd(uart_hal_context_t *hal, uint32_t *wakeup_thrd)
{
*wakeup_thrd = uart_ll_get_wakeup_edge_thrd(hal->dev);
*wakeup_thrd = uart_ll_get_wakeup_edge_thrd(hal->dev);
}
void uart_hal_set_mode(uart_hal_context_t *hal, uart_mode_t mode)
components/hal/uart_hal_iram.c → components/esp_hal_uart/uart_hal_iram.c
View File
components/hal/uhci_hal.c → components/esp_hal_uart/uhci_hal.c
View File
components/esp_hw_support/CMakeLists.txt
+1
View File
@@ -80,6 +80,7 @@ if(NOT non_os_build)
list(APPEND priv_requires esp_mm
esp_hal_mspi
esp_hal_uart
)
if(CONFIG_IDF_TARGET_ESP32 OR CONFIG_IDF_TARGET_ESP32S2)
components/esp_hw_support/sleep_system_peripheral.c
+1 -1
View File
@@ -10,7 +10,7 @@
#include "sdkconfig.h"
#include "soc/soc_caps.h"
#include "soc/system_periph_retention.h"
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
#include "hal/timer_ll.h"
#if SOC_HAS(I2S)
#include "hal/i2s_ll.h"
components/esp_pm/CMakeLists.txt
+1 -1
View File
@@ -1,5 +1,5 @@
idf_build_get_property(target IDF_TARGET)
set(priv_requires esp_system esp_driver_gpio esp_timer)
set(priv_requires esp_system esp_driver_gpio esp_timer esp_hal_uart)
if(${target} STREQUAL "linux")
return() # This component is not supported by the POSIX/Linux simulator
components/esp_rom/CMakeLists.txt
+1 -1
View File
@@ -44,7 +44,7 @@ else()
list(APPEND sources "patches/esp_rom_multi_heap.c")
endif()
list(APPEND private_required_comp soc hal)
list(APPEND private_required_comp soc hal esp_hal_uart)
endif()
if(CONFIG_IDF_TARGET_ARCH_XTENSA)
components/esp_rom/esp32/include/esp32/rom/uart.h
-1
View File
@@ -9,7 +9,6 @@
#include "esp_attr.h"
#include "ets_sys.h"
#include "soc/soc.h"
#include "soc/uart_periph.h"
#include "soc/uart_reg.h"
#ifdef __cplusplus
components/esp_system/CMakeLists.txt
+1 -1
View File
@@ -75,7 +75,7 @@ else()
idf_component_register(SRCS "${srcs}"
INCLUDE_DIRS include
PRIV_REQUIRES spi_flash esp_timer esp_mm esp_hal_mspi esp_hal_wdt
PRIV_REQUIRES spi_flash esp_timer esp_mm esp_hal_mspi esp_hal_wdt esp_hal_uart
# [refactor-todo] requirements due to init code,
# should be removable once using component init functions
# link-time registration is used.
components/esp_system/linker.lf
+1 -1
View File
@@ -38,7 +38,7 @@ entries:
image_process (noflash)
[mapping:esp_system_hal]
archive: libhal.a
archive: libesp_hal_uart.a
entries:
if ESP_PANIC_HANDLER_IRAM = y:
uart_hal_iram (noflash)
components/hal/CMakeLists.txt
-8
View File
@@ -80,18 +80,10 @@ elseif(NOT BOOTLOADER_BUILD)
list(APPEND srcs "systimer_hal.c")
endif()
if(CONFIG_SOC_UART_SUPPORTED)
list(APPEND srcs "uart_hal.c" "uart_hal_iram.c")
endif()
if(CONFIG_SOC_I3C_MASTER_SUPPORTED)
list(APPEND srcs "i3c_master_hal.c")
endif()
if(CONFIG_SOC_UHCI_SUPPORTED)
list(APPEND srcs "uhci_hal.c")
endif()
if(CONFIG_SOC_SDMMC_HOST_SUPPORTED)
list(APPEND srcs "sdmmc_hal.c")
endif()
components/hal/Kconfig
+1 -9
View File
@@ -80,15 +80,7 @@ menu "Hardware Abstraction Layer (HAL) and Low Level (LL)"
orsource "../esp_hal_wdt/Kconfig.hal_wdt"
config HAL_GPIO_USE_ROM_IMPL
bool "Use ROM implementation of GPIO HAL driver"
default y
help
Enable this flag to use HAL functions from ROM when applicable instead of ESP-IDF.
If keeping this as "n" in your project, you will have less free IRAM.
When compiling an application for a CPU that cannot access to the ROM memory,
this option should be disabled.
orsource "../esp_hal_gpio/Kconfig.hal_gpio"
config HAL_ECDSA_GEN_SIG_CM
bool "Enable countermeasure for ECDSA signature generation"
components/mbedtls/test_apps/main/test_aes_sha_rsa.c
-1
View File
@@ -17,7 +17,6 @@
#include "unity.h"
#include "test_utils.h"
#include "esp32/rom/sha.h"
#include "soc/uart_periph.h"
#include "soc/dport_reg.h"
#include "soc/rtc.h"
#include "esp_log.h"
components/soc/CMakeLists.txt
+2 -4
View File
@@ -8,14 +8,12 @@ if(NOT ${target} STREQUAL "linux")
set(srcs "lldesc.c"
"dport_access_common.c"
"${target_folder}/interrupts_beta5.c"
"${target_folder}/gpio_periph.c"
"${target_folder}/uart_periph.c")
"${target_folder}/gpio_periph.c")
else()
set(srcs "lldesc.c"
"dport_access_common.c"
"${target_folder}/interrupts.c"
"${target_folder}/gpio_periph.c"
"${target_folder}/uart_periph.c")
"${target_folder}/gpio_periph.c")
endif()
endif()
components/ulp/cmake/IDFULPProject.cmake
+2 -2
View File
@@ -119,8 +119,8 @@ function(ulp_apply_default_sources ulp_app_name)
"${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_startup.c"
"${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_utils.c"
"${IDF_PATH}/components/hal/uart_hal_iram.c"
"${IDF_PATH}/components/hal/uart_hal.c"
"${IDF_PATH}/components/esp_hal_uart/uart_hal_iram.c"
"${IDF_PATH}/components/esp_hal_uart/uart_hal.c"
"${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_uart.c"
"${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_print.c"
"${IDF_PATH}/components/ulp/lp_core/lp_core/lp_core_panic.c"
components/ulp/lp_core/lp_core_uart.c
+1 -1
View File
@@ -10,7 +10,7 @@
#include "lp_core_uart.h"
#include "driver/rtc_io.h"
#include "driver/lp_io.h"
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
#include "soc/lp_uart_struct.h"
#include "hal/uart_hal.h"
#include "hal/rtc_io_hal.h"
docs/doxygen/Doxyfile
+3 -3
View File
@@ -149,6 +149,7 @@ INPUT = \
$(PROJECT_PATH)/components/esp_driver_tsens/include/driver/temperature_sensor.h \
$(PROJECT_PATH)/components/esp_driver_tsens/include/driver/temperature_sensor_etm.h \
$(PROJECT_PATH)/components/esp_driver_uart/include/driver/uart.h \
$(PROJECT_PATH)/components/esp_driver_uart/include/driver/uart_wakeup.h \
$(PROJECT_PATH)/components/esp_driver_uart/include/driver/uart_vfs.h \
$(PROJECT_PATH)/components/esp_driver_uart/include/driver/uhci.h \
$(PROJECT_PATH)/components/esp_driver_uart/include/driver/uhci_types.h \
@@ -182,6 +183,8 @@ INPUT = \
$(PROJECT_PATH)/components/esp_hal_pcnt/include/hal/pcnt_types.h \
$(PROJECT_PATH)/components/esp_hal_rmt/include/hal/rmt_types.h \
$(PROJECT_PATH)/components/esp_hal_twai/include/hal/twai_types.h \
$(PROJECT_PATH)/components/esp_hal_uart/include/hal/uart_types.h \
$(PROJECT_PATH)/components/esp_hal_uart/include/hal/uhci_types.h \
$(PROJECT_PATH)/components/esp_http_client/include/esp_http_client.h \
$(PROJECT_PATH)/components/esp_http_server/include/esp_http_server.h \
$(PROJECT_PATH)/components/esp_https_ota/include/esp_https_ota.h \
@@ -269,12 +272,10 @@ INPUT = \
$(PROJECT_PATH)/components/hal/include/hal/color_types.h \
$(PROJECT_PATH)/components/hal/include/hal/mcpwm_types.h \
$(PROJECT_PATH)/components/hal/include/hal/sdio_slave_types.h \
$(PROJECT_PATH)/components/hal/include/hal/uart_types.h \
$(PROJECT_PATH)/components/hal/include/hal/efuse_hal.h \
$(PROJECT_PATH)/components/hal/include/hal/eth_types.h \
$(PROJECT_PATH)/components/hal/include/hal/lp_core_types.h \
$(PROJECT_PATH)/components/hal/include/hal/sd_types.h \
$(PROJECT_PATH)/components/hal/include/hal/uhci_types.h \
$(PROJECT_PATH)/components/heap/include/esp_heap_caps_init.h \
$(PROJECT_PATH)/components/heap/include/esp_heap_caps.h \
$(PROJECT_PATH)/components/heap/include/esp_heap_task_info.h \
@@ -335,7 +336,6 @@ INPUT = \
$(PROJECT_PATH)/components/wear_levelling/include/wear_levelling.h \
$(PROJECT_PATH)/components/wpa_supplicant/esp_supplicant/include/esp_dpp.h \
$(PROJECT_PATH)/components/wpa_supplicant/esp_supplicant/include/esp_supplicant_utils.h \
$(PROJECT_PATH)/components/esp_driver_uart/include/driver/uart_wakeup.h \
## Target specific headers are in separate Doxyfile files
@INCLUDE = $(PROJECT_PATH)/docs/doxygen/Doxyfile_$(IDF_TARGET)
docs/en/api-reference/peripherals/uhci.rst
+1 -1
View File
@@ -293,7 +293,7 @@ API Reference
.. include-build-file:: inc/uhci.inc
.. include-build-file:: inc/components/esp_driver_uart/include/driver/uhci_types.inc
.. include-build-file:: inc/components/hal/include/hal/uhci_types.inc
.. include-build-file:: inc/components/esp_hal_uart/include/hal/uhci_types.inc
.. [1]
The callback function, e.g., :cpp:member:`uhci_event_callbacks_t::on_tx_trans_done`, :cpp:member:`uhci_event_callbacks_t::on_rx_trans_event` and the functions invoked by itself should also reside in IRAM, users need to take care of this by themselves.
docs/zh_CN/api-reference/peripherals/uhci.rst
+1 -1
View File
@@ -293,7 +293,7 @@ API 参考
.. include-build-file:: inc/uhci.inc
.. include-build-file:: inc/components/esp_driver_uart/include/driver/uhci_types.inc
.. include-build-file:: inc/components/hal/include/hal/uhci_types.inc
.. include-build-file:: inc/components/esp_hal_uart/include/hal/uhci_types.inc
.. [1]
回调函数（例如 :cpp:member:`uhci_event_callbacks_t::on_tx_trans_done` 、:cpp:member:`uhci_event_callbacks_t::on_rx_trans_event`）及其调用的函数也应驻留在 IRAM 中，用户需要自行注意这一点。
examples/peripherals/.build-test-rules.yml
+2
View File
@@ -79,6 +79,7 @@ examples/peripherals/dac/dac_cosine_wave:
examples/peripherals/gpio:
depends_components:
- esp_driver_gpio
- esp_hal_gpio
examples/peripherals/gpio/matrix_keyboard:
enable:
@@ -442,6 +443,7 @@ examples/peripherals/sigma_delta:
- if: SOC_SDM_SUPPORTED != 1
depends_components:
- esp_driver_sdm
- esp_hal_gpio
examples/peripherals/spi_master/hd_eeprom:
disable:
examples/peripherals/uart/uart_repl/main/uart_repl_example_main.c
+1 -1
View File
@@ -10,7 +10,7 @@
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "driver/uart.h"
#include "soc/uart_periph.h"
#include "hal/uart_periph.h"
#include "esp_rom_gpio.h"
#include "driver/gpio.h"
#include "hal/gpio_hal.h"
tools/test_apps/system/g1_components/CMakeLists.txt
+1
View File
@@ -18,6 +18,7 @@ set(esp_hal_components
esp_hal_gpspi
esp_hal_timg
esp_hal_touch_sens
esp_hal_uart
esp_hal_usb
esp_hal_wdt
esp_hal_pmu