Merge branch 'feat/add_retention_test_back' into 'master'

feat: add sleep retention UT test back

Closes IDFCI-8836

See merge request espressif/esp-idf!46621

components/esp_hw_support/sleep_modes.c

@@ -723,6 +723,7 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool
         sar_periph_ctrl_power_disable();
     }
 #endif
+    suspend_timers(sleep_flags);
 }
 
 /**
@@ -730,6 +731,7 @@ static SLEEP_FN_ATTR void misc_modules_sleep_prepare(uint32_t sleep_flags, bool
  */
 static SLEEP_FN_ATTR void misc_modules_wake_prepare(uint32_t sleep_flags)
 {
+    resume_timers(sleep_flags);
 #if CONFIG_ESP_ENABLE_PVT && SOC_PVT_EN_WITH_SLEEP
     pvt_func_enable(true);
 #endif
@@ -906,7 +908,6 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint
         result = rtc_deep_sleep_start(s_config.wakeup_triggers, reject_triggers);
 #endif
     } else {
-        suspend_timers(sleep_flags);
         /* Cache Suspend 1: will wait cache idle in cache suspend */
         suspend_cache();
         if (!(sleep_flags & RTC_SLEEP_PD_VDDSDIO)) {
@@ -992,7 +993,12 @@ static esp_err_t FORCE_IRAM_ATTR esp_sleep_start_safe(uint32_t sleep_flags, uint
 #endif
         /* Cache Resume 1: Resume cache for continue running*/
         resume_cache();
-        resume_timers(sleep_flags);
+#if CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED && CONFIG_SPIRAM_XIP_FROM_PSRAM
+        // Code outside of esp_sleep_start_safe may be linked to FLASH, and if CONFIG_SPIRAM_XIP_FROM_PSRAM
+        // is enabled, code in Flash will be copied to PSRAM for execution. We need to wait here until
+        // PSRAM exits half-sleep before returning.
+        esp_psram_impl_resume_from_halfsleep_mode(s_config.rtc_clk_cal_period);
+#endif
     }
     return result;
 }
@@ -1395,10 +1401,6 @@ static SLEEP_FN_ATTR esp_err_t esp_light_sleep_inner(uint32_t sleep_flags, uint3
 #endif
     }
 
-#if CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED
-    esp_psram_impl_resume_from_halfsleep_mode(s_config.rtc_clk_cal_period);
-#endif
-
 #if CONFIG_ESP_SLEEP_CACHE_SAFE_ASSERTION
     if (sleep_flags & RTC_SLEEP_PD_VDDSDIO) {
         /* Cache Resume 2: flash is ready now, we can resume the cache and access flash safely after */
@@ -1683,6 +1685,14 @@ esp_err_t esp_light_sleep_start(void)
     }
 #endif
 
+#if CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED && !CONFIG_SPIRAM_XIP_FROM_PSRAM
+    // If CONFIG_SPIRAM_XIP_FROM_PSRAM is not enabled, the sleep-wake process
+    // prior to this point does not access the PSRAM, so we can postpone waiting
+    // for the PSRAM to resume until here, in order to reuse the time overhead
+    // of the wake-up process as much as possible.
+    esp_psram_impl_resume_from_halfsleep_mode(s_config.rtc_clk_cal_period);
+#endif
+
 #if !CONFIG_FREERTOS_UNICORE
     esp_ipc_isr_stall_resume();
 #if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && SOC_PM_CPU_RETENTION_BY_SW

components/esp_hw_support/test_apps/sleep_retention/pytest_retention.py

@@ -0,0 +1,20 @@
+# SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+import pytest
+from pytest_embedded import Dut
+from pytest_embedded_idf.utils import idf_parametrize
+from pytest_embedded_idf.utils import soc_filtered_targets
+
+
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'default',
+        'xip_psram',
+    ],
+    indirect=True,
+)
+@idf_parametrize('target', soc_filtered_targets('SOC_PAU_SUPPORTED == 1'), indirect=['target'])
+def test_sleep_retention(dut: Dut) -> None:
+    dut.run_all_single_board_cases()