Merge branch 'feat/p4_eco5_real_chip_v5.4' into 'release/v5.4'

p4: p4 eco5 real chip (v5.4) See merge request espressif/esp-idf!42063
2026-04-27 19:13:21 +00:00 · 2025-10-26 22:38:34 +08:00
parent 2de7923716 a70a29b7a6
commit 80971b25da
42 changed files with 2097 additions and 84 deletions
@@ -5,6 +5,11 @@ set(target_folder "${target}")

 idf_build_get_property(target IDF_TARGET)
 set(scripts "ld/${target_folder}/bootloader.ld")
+if(CONFIG_ESP32P4_REV_MIN_300)
+    set(scripts "ld/${target_folder}/bootloader.rev3.ld")
+else()
+    set(scripts "ld/${target_folder}/bootloader.ld")
+endif()

 list(APPEND scripts "ld/${target_folder}/bootloader.rom.ld")
 target_linker_script(${COMPONENT_LIB} INTERFACE "${scripts}")
@@ -0,0 +1,324 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/**
+ * Simplified memory map for the bootloader.
+ *  Make sure the bootloader can load into main memory without overwriting itself.
+ *
+ *  ESP32-P4 ROM static data usage is as follows:
+ *  - 0x4ff296b8 - 0x4ff3afc0: Shared buffers, used in UART/USB/SPI download mode only
+ *  - 0x4ff3afc0 - 0x4ff3fba4: CPU1 stack, can be reclaimed as heap after RTOS startup
+ *  - 0x4ff3fba4 - 0x4ff40000: ROM .bss and .data (not easily reclaimable)
+ *
+ *  The 2nd stage bootloader can take space up to the end of ROM shared
+ *  buffers area (0x4087c610).
+ */
+
+/* We consider 0x4087c610 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
+ * and work out iram_seg and iram_loader_seg addresses from there, backwards.
+ */
+
+/* These lengths can be adjusted, if necessary: */
+bootloader_usable_dram_end = 0x4ffbcfc0;
+bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
+bootloader_dram_seg_len = 0x5000;
+bootloader_iram_loader_seg_len = 0x7000;
+bootloader_iram_seg_len = 0x2D00;
+
+/* Start of the lower region is determined by region size and the end of the higher region */
+bootloader_dram_seg_end = bootloader_usable_dram_end - bootloader_stack_overhead;
+bootloader_dram_seg_start = bootloader_dram_seg_end - bootloader_dram_seg_len;
+bootloader_iram_loader_seg_start = bootloader_dram_seg_start - bootloader_iram_loader_seg_len;
+bootloader_iram_seg_start = bootloader_iram_loader_seg_start - bootloader_iram_seg_len;
+
+MEMORY
+{
+  iram_seg (RWX) :                  org = bootloader_iram_seg_start, len = bootloader_iram_seg_len
+  iram_loader_seg (RWX) :           org = bootloader_iram_loader_seg_start, len = bootloader_iram_loader_seg_len
+  dram_seg (RW) :                   org = bootloader_dram_seg_start, len = bootloader_dram_seg_len
+}
+
+/* The app may use RAM for static allocations up to the start of iram_loader_seg.
+ * If you have changed something above and this assert fails:
+ * 1. Check what the new value of bootloader_iram_loader_seg start is.
+ * 2. Update the value in this assert.
+ * 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32p4/memory.ld.in to the same value.
+ */
+ASSERT(bootloader_iram_loader_seg_start == 0x4FFAEFC0, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
+
+/* Default entry point: */
+ENTRY(call_start_cpu0);
+
+SECTIONS
+{
+
+  .iram_loader.text :
+  {
+    . = ALIGN (16);
+    _loader_text_start = ABSOLUTE(.);
+    *(.stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram1 .iram1.*) /* catch stray IRAM_ATTR */
+    *liblog.a:(.literal .text .literal.* .text.*)
+    *libgcc.a:(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_clock_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_common_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_flash.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_disable .text.bootloader_random_disable)
+    *libbootloader_support.a:bootloader_random*.*(.literal.bootloader_random_enable .text.bootloader_random_enable)
+    *libbootloader_support.a:bootloader_efuse.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_utility.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_sha.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_console_loader.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_panic.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:bootloader_soc.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:esp_image_format.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encrypt.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_encryption_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:flash_partitions.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_secure_features.*(.literal .text .literal.* .text.*)
+    *libbootloader_support.a:secure_boot_signatures_bootloader.*(.literal .text .literal.* .text.*)
+    *libmicro-ecc.a:*.*(.literal .text .literal.* .text.*)
+    *libspi_flash.a:*.*(.literal .text .literal.* .text.*)
+    *libhal.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
+    *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
+    *libhal.a:key_mgr_hal.*(.literal.key_mgr_hal_set_key_usage .text.key_mgr_hal_set_key_usage)
+    *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:rtc_time.*(.literal .text .literal.* .text.*)
+    *libesp_hw_support.a:regi2c_ctrl.*(.literal .text .literal.* .text.*)
+    *libefuse.a:*.*(.literal .text .literal.* .text.*)
+    *libriscv.a:rv_utils.*(.literal .text .literal.* .text.*)
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+    _loader_text_end = ABSOLUTE(.);
+  } > iram_loader_seg
+
+  .iram.text :
+  {
+    . = ALIGN (16);
+    *(.entry.text)
+    *(.init.literal)
+    *(.init)
+  } > iram_seg
+
+
+  /* Shared RAM */
+  .dram0.bss (NOLOAD) :
+  {
+    . = ALIGN (8);
+    _dram_start = ABSOLUTE(.);
+    _bss_start = ABSOLUTE(.);
+    *(.dynsbss)
+    *(.sbss)
+    *(.sbss.*)
+    *(.gnu.linkonce.sb.*)
+    *(.scommon)
+    *(.sbss2)
+    *(.sbss2.*)
+    *(.gnu.linkonce.sb2.*)
+    *(.dynbss)
+    *(.bss)
+    *(.bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    _bss_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.bootdesc : ALIGN(0x10)
+  {
+    _data_start = ABSOLUTE(.);
+    *(.data_bootloader_desc .data_bootloader_desc.*)               /* Should be the first.  Bootloader version info.        DO NOT PUT ANYTHING BEFORE IT! */
+  } > dram_seg
+
+  .dram0.data :
+  {
+    *(.dram1 .dram1.*) /* catch stray DRAM_ATTR */
+    *(.data)
+    *(.data.*)
+    *(.gnu.linkonce.d.*)
+    *(.data1)
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.gnu.linkonce.s2.*)
+    *(.jcr)
+    _data_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .dram0.rodata :
+  {
+    _rodata_start = ABSOLUTE(.);
+    *(.rodata)
+    *(.rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    *(.sdata2 .sdata2.* .srodata .srodata.*)
+    __XT_EXCEPTION_TABLE_ = ABSOLUTE(.);
+    *(.xt_except_table)
+    *(.gcc_except_table)
+    *(.gnu.linkonce.e.*)
+    *(.gnu.version_r)
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+    . = (. + 3) & ~ 3;
+    /* C++ constructor and destructor tables, properly ordered: */
+    __init_array_start = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    __init_array_end = ABSOLUTE(.);
+    KEEP (*crtbegin.*(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.*) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    /*  C++ exception handlers table:  */
+    __XT_EXCEPTION_DESCS_ = ABSOLUTE(.);
+    *(.xt_except_desc)
+    *(.gnu.linkonce.h.*)
+    __XT_EXCEPTION_DESCS_END__ = ABSOLUTE(.);
+    *(.xt_except_desc_end)
+    *(.dynamic)
+    *(.gnu.version_d)
+    _rodata_end = ABSOLUTE(.);
+    /* Literals are also RO data. */
+    _lit4_start = ABSOLUTE(.);
+    *(*.lit4)
+    *(.lit4.*)
+    *(.gnu.linkonce.lit4.*)
+    _lit4_end = ABSOLUTE(.);
+    . = ALIGN(4);
+    _dram_end = ABSOLUTE(.);
+  } > dram_seg
+
+  .iram.text :
+  {
+    _stext = .;
+    _text_start = ABSOLUTE(.);
+    *(.literal .text .literal.* .text.* .stub .gnu.warning .gnu.linkonce.literal.* .gnu.linkonce.t.*.literal .gnu.linkonce.t.*)
+    *(.iram .iram.*) /* catch stray IRAM_ATTR */
+    *(.fini.literal)
+    *(.fini)
+    *(.gnu.version)
+
+    /** CPU will try to prefetch up to 16 bytes of
+      * of instructions. This means that any configuration (e.g. MMU, PMS) must allow
+      * safe access to up to 16 bytes after the last real instruction, add
+      * dummy bytes to ensure this
+      */
+    . += 16;
+
+    _text_end = ABSOLUTE(.);
+    _etext = .;
+  } > iram_seg
+
+  .riscv.attributes 0: { *(.riscv.attributes) }
+
+  /* DWARF 1 */
+  .debug              0 : { *(.debug) }
+  .line               0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo      0 : { *(.debug_srcinfo) }
+  .debug_sfnames      0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges      0 : { *(.debug_aranges) }
+  .debug_pubnames     0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev       0 : { *(.debug_abbrev) }
+  .debug_line         0 : { *(.debug_line) }
+  .debug_frame        0 : { *(.debug_frame) }
+  .debug_str          0 : { *(.debug_str) }
+  .debug_loc          0 : { *(.debug_loc) }
+  .debug_macinfo      0 : { *(.debug_macinfo) }
+  .debug_pubtypes     0 : { *(.debug_pubtypes) }
+  /* DWARF 3 */
+  .debug_ranges       0 : { *(.debug_ranges) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames    0 : { *(.debug_weaknames) }
+  .debug_funcnames    0 : { *(.debug_funcnames) }
+  .debug_typenames    0 : { *(.debug_typenames) }
+  .debug_varnames     0 : { *(.debug_varnames) }
+  /* GNU DWARF 2 extensions */
+  .debug_gnu_pubnames 0 : { *(.debug_gnu_pubnames) }
+  .debug_gnu_pubtypes 0 : { *(.debug_gnu_pubtypes) }
+  /* DWARF 4 */
+  .debug_types        0 : { *(.debug_types) }
+  /* DWARF 5 */
+  .debug_addr         0 : { *(.debug_addr) }
+  .debug_line_str     0 : { *(.debug_line_str) }
+  .debug_loclists     0 : { *(.debug_loclists) }
+  .debug_macro        0 : { *(.debug_macro) }
+  .debug_names        0 : { *(.debug_names) }
+  .debug_rnglists     0 : { *(.debug_rnglists) }
+  .debug_str_offsets  0 : { *(.debug_str_offsets) }
+
+  .comment 0 : { *(.comment) }
+  .note.GNU-stack 0: { *(.note.GNU-stack) }
+
+  /**
+   * Discarding .rela.* sections results in the following mapping:
+   * .rela.text.* -> .text.*
+   * .rela.data.* -> .data.*
+   * And so forth...
+   */
+  /DISCARD/ : { *(.rela.*) }
+
+  /**
+   * This section is not included in the binary image; it is only present in the ELF file.
+   * It is used to keep certain symbols in the ELF file.
+   */
+  .noload 0 (INFO) :
+  {
+    _noload_keep_in_elf_start = ABSOLUTE(.);
+    KEEP(*(.noload_keep_in_elf .noload_keep_in_elf.*))
+    _noload_keep_in_elf_end = ABSOLUTE(.);
+  }
+}
+
+
+/**
+ *  Appendix: Memory Usage of ROM bootloader
+ *
+ *  0x4ffa96b8 ------------------> _dram0_0_start
+ *          |               |
+ *          |               |
+ *          |               |   1. Large buffers that are only used in certain boot modes, see shared_buffers.h
+ *          |               |
+ *          |               |
+ * 0x4ffbafc0 ------------------> __stack_sentry
+ *          |               |
+ *          |               |   2. Startup pro cpu stack (freed when IDF app is running)
+ *          |               |
+ * 0x4ffbcfc0 ------------------> __stack (pro cpu)
+ *          |               |
+ *          |               |      Startup app cpu stack
+ *          |               |
+ * 0x4ffbefc0 ------------------> __stack_app (app cpu)
+ *          |               |
+ *          |               |
+ *          |               |   3. Shared memory only used in startup code or nonos/early boot*
+ *          |               |      (can be freed when IDF runs)
+ *          |               |
+ *          |               |
+ * 0x4ffbfbb0 ------------------> _dram0_rtos_reserved_start
+ *          |               |
+ *          |               |
+ *          |               |   4. Shared memory used in startup code and when IDF runs
+ *          |               |
+ *          |               |
+ * 0x4ffbffa4 ------------------> _dram0_rtos_reserved_end
+ *          |               |
+ * 0x4ffbffc8 ------------------> _data_start_interface
+ *          |               |
+ *          |               |   5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
+ *          |               |
+ * 0x4ffc0000 ------------------> _data_end_interface
+ */
@@ -224,6 +224,7 @@ static void bootloader_spi_flash_resume(void)

 esp_err_t bootloader_init_spi_flash(void)
 {
+    bootloader_init_mspi_clock();
    bootloader_init_flash_configure();
    bootloader_spi_flash_resume();
    bootloader_flash_unlock();
@@ -34,7 +34,11 @@ __attribute__((weak)) void bootloader_clock_configure(void)
    esp_rom_output_tx_wait_idle(0);

    /* Set CPU to a higher certain frequency. Keep other clocks unmodified. */
+#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
+    int cpu_freq_mhz = 100;
+#else
    int cpu_freq_mhz = CPU_CLK_FREQ_MHZ_BTLD;
+#endif

 #if CONFIG_IDF_TARGET_ESP32
    /* On ESP32 rev 0, switching to 80/160 MHz if clock was previously set to
@@ -352,6 +352,11 @@ err:
 }

 #ifdef BOOTLOADER_BUILD
+#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
+#define ROM_STACK_START         (SOC_ROM_STACK_START_REV2)
+#else
+#define ROM_STACK_START         (SOC_ROM_STACK_START)
+#endif
 /* Check the region load_addr - load_end doesn't overlap any memory used by the bootloader, registers, or other invalid memory
 */
 static bool verify_load_addresses(int segment_index, intptr_t load_addr, intptr_t load_end, bool print_error, bool no_recurse)
@@ -371,7 +376,7 @@ static bool verify_load_addresses(int segment_index, intptr_t load_addr, intptr_
    if (esp_ptr_in_dram(load_addr_p) && esp_ptr_in_dram(load_inclusive_end_p)) { /* Writing to DRAM */
        /* Check if we're clobbering the stack */
        intptr_t sp = (intptr_t)esp_cpu_get_sp();
-        if (bootloader_util_regions_overlap(sp - STACK_LOAD_HEADROOM, SOC_ROM_STACK_START,
+        if (bootloader_util_regions_overlap(sp - STACK_LOAD_HEADROOM, ROM_STACK_START,
                                           load_addr, load_end)) {
            reason = "overlaps bootloader stack";
            goto invalid;
@@ -1,3 +1,15 @@
+comment "NOTE! Support of ESP32-P4 rev. <3.0 and >=3.0 is mutually exclusive"
+comment "Read the help text of the option below for explanation"
+
+config ESP32P4_SELECTS_REV_LESS_V3
+    bool "Select ESP32-P4 revisions <3.0 (No >=3.x Support)"
+    default y
+    help
+        Select this option to support ESP32-P4 revisions 0.x and 1.x.
+        Revisions higher than 3.0 (included) and revisions less than 3.0
+        have huge hardware difference.
+        Revisions higher than 3.0 (included) is not compatible with 0.x and 1.x.
+
 choice ESP32P4_REV_MIN
    prompt "Minimum Supported ESP32-P4 Revision"
    default ESP32P4_REV_MIN_1
@@ -10,11 +22,18 @@ choice ESP32P4_REV_MIN
        this will also help to reduce binary size.

    config ESP32P4_REV_MIN_0
+        depends on ESP32P4_SELECTS_REV_LESS_V3
        bool "Rev v0.0"
    config ESP32P4_REV_MIN_1
+        depends on ESP32P4_SELECTS_REV_LESS_V3
        bool "Rev v0.1"
    config ESP32P4_REV_MIN_100
+        depends on ESP32P4_SELECTS_REV_LESS_V3
        bool "Rev v1.0"
+    config ESP32P4_REV_MIN_300
+        bool "Rev v3.0"
+        depends on !ESP32P4_SELECTS_REV_LESS_V3
+        select ESPTOOLPY_NO_STUB # TODO: IDF-13911
 endchoice

 config ESP32P4_REV_MIN_FULL
@@ -22,6 +41,7 @@ config ESP32P4_REV_MIN_FULL
    default 0 if ESP32P4_REV_MIN_0
    default 1 if ESP32P4_REV_MIN_1
    default 100 if ESP32P4_REV_MIN_100
+    default 300 if ESP32P4_REV_MIN_300

 config ESP_REV_MIN_FULL
    int
@@ -32,6 +52,9 @@ config ESP_REV_MIN_FULL
    #

    comment "Maximum Supported ESP32-P4 Revision (Rev v1.99)"
+    depends on ESP32P4_SELECTS_REV_LESS_V3
+    comment "Maximum Supported ESP32-P4 Revision (Rev v3.99)"
+    depends on !ESP32P4_SELECTS_REV_LESS_V3
    # Maximum revision that IDF supports.
    # It can not be changed by user.
    # Only Espressif can change it when a new version will be supported in IDF.
@@ -39,7 +62,8 @@ config ESP_REV_MIN_FULL

 config ESP32P4_REV_MAX_FULL
    int
-    default 199
+    default 399 if !ESP32P4_SELECTS_REV_LESS_V3
+    default 199 if ESP32P4_SELECTS_REV_LESS_V3
    # keep in sync the "Maximum Supported Revision" description with this value

 config ESP_REV_MAX_FULL
@@ -59,6 +83,6 @@ config ESP_EFUSE_BLOCK_REV_MIN_FULL

 config ESP_EFUSE_BLOCK_REV_MAX_FULL
    int
-    default 99
+    default 199
    comment "Maximum Supported ESP32-P4 eFuse Block Revision (eFuse Block Rev v0.99)"
    # The revision in the comment must correspond to the default value of ESP_EFUSE_BLOCK_REV_MAX_FULL
@@ -8,6 +8,7 @@
 #include <stdbool.h>
 #include <stddef.h>
 #include <stdint.h>
+#include "sdkconfig.h"
 #include "soc/soc.h"
 #include "soc/clk_tree_defs.h"
 #include "hal/hal_utils.h"
@@ -189,6 +190,7 @@ typedef struct {
 /**
 * Default initializer for rtc_clk_config_t
 */
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 #define RTC_CLK_CONFIG_DEFAULT() { \
    .xtal_freq = CONFIG_XTAL_FREQ, \
    .cpu_freq_mhz = 90, \
@@ -200,6 +202,19 @@ typedef struct {
    .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
    .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \
 }
+#else
+#define RTC_CLK_CONFIG_DEFAULT() { \
+    .xtal_freq = CONFIG_XTAL_FREQ, \
+    .cpu_freq_mhz = 100, \
+    .fast_clk_src = SOC_RTC_FAST_CLK_SRC_RC_FAST, \
+    .slow_clk_src = SOC_RTC_SLOW_CLK_SRC_RC_SLOW, \
+    .clk_rtc_clk_div = 0, \
+    .clk_8m_clk_div = 0, \
+    .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
+    .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
+    .rc32k_dfreq = RTC_CNTL_RC32K_DFREQ_DEFAULT, \
+}
+#endif

 /**
 * Initialize clocks and set CPU frequency
@@ -343,7 +343,7 @@ uint32_t get_act_hp_dbias(void)
    uint32_t hp_cali_dbias = HP_CALI_ACTIVE_DBIAS_DEFAULT;
    uint32_t blk_version = efuse_hal_blk_version();
    uint32_t hp_cali_dbias_efuse = 0;
-    if (blk_version >= 2) {
+    if (blk_version >= 2 && blk_version < 100) {
        hp_cali_dbias_efuse = efuse_ll_get_active_hp_dbias();
    }
    if (hp_cali_dbias_efuse > 0) {
@@ -364,7 +364,7 @@ uint32_t get_act_lp_dbias(void)
    uint32_t lp_cali_dbias = LP_CALI_ACTIVE_DBIAS_DEFAULT;
    uint32_t blk_version = efuse_hal_blk_version();
    uint32_t lp_cali_dbias_efuse = 0;
-    if (blk_version >= 2) {
+    if (blk_version >= 2 && blk_version < 100) {
        lp_cali_dbias_efuse = efuse_ll_get_active_lp_dbias();
    }
    if (lp_cali_dbias_efuse > 0) {
@@ -34,7 +34,7 @@ static uint8_t get_lp_hp_gap(void)
    int8_t lp_hp_gap = 0;
    uint32_t blk_version = efuse_hal_blk_version();
    uint8_t lp_hp_gap_efuse = 0;
-    if (blk_version >= 2) {
+    if (blk_version >= 2 && blk_version < 100) {
        lp_hp_gap_efuse = efuse_ll_get_dbias_vol_gap();
        bool gap_flag = lp_hp_gap_efuse >> 4;
        uint8_t gap_abs_value = lp_hp_gap_efuse & 0xf;
@@ -78,7 +78,7 @@ static uint32_t pvt_get_lp_dbias(void)
 void pvt_auto_dbias_init(void)
 {
    uint32_t blk_version = efuse_hal_blk_version();
-    if (blk_version >= 2) {
+    if (blk_version >= 2 && blk_version < 100) {
        SET_PERI_REG_MASK(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN);
        SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_PVT_SYS_CLK_EN);
        /*config for dbias func*/
@@ -121,7 +121,7 @@ void pvt_auto_dbias_init(void)
 void pvt_func_enable(bool enable)
 {
    uint32_t blk_version = efuse_hal_blk_version();
-    if (blk_version >= 2){
+    if (blk_version >= 2 && blk_version < 100){

        if (enable) {
            SET_PERI_REG_MASK(HP_SYS_CLKRST_REF_CLK_CTRL2_REG, HP_SYS_CLKRST_REG_REF_160M_CLK_EN);
@@ -220,6 +220,7 @@ static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t *
    uint32_t mem_divider = 1;
    uint32_t sys_divider = 1; // We are not going to change this
    uint32_t apb_divider = 1;
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
    switch (cpu_freq_mhz) {
    case 360:
        mem_divider = 2;
@@ -240,6 +241,28 @@ static void rtc_clk_cpu_freq_to_cpll_mhz(int cpu_freq_mhz, hal_utils_clk_div_t *
        // To avoid such case, we will strictly do abort here.
        abort();
    }
+#else
+    switch (cpu_freq_mhz) {
+    case 400:
+        mem_divider = 2;
+        apb_divider = 2;
+        break;
+    case 200:
+        mem_divider = 1;
+        apb_divider = 2;
+        break;
+    case 100:
+        mem_divider = 1;
+        apb_divider = 1;
+        break;
+    default:
+        // Unsupported configuration
+        // This is dangerous to modify dividers. Hardware could automatically correct the divider, and it won't be
+        // reflected to the registers. Therefore, you won't even be able to calculate out the real mem_clk, apb_clk freq.
+        // To avoid such case, we will strictly do abort here.
+        abort();
+    }
+#endif

    // If it's upscaling, the divider of MEM/SYS/APB needs to be increased, to avoid illegal intermediate states,
    // the clock divider should be updated in the order from the APB_CLK to CPU_CLK.
@@ -285,6 +308,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou

    // Keep default CPLL at 360MHz
    uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get();
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
    if (freq_mhz <= xtal_freq && freq_mhz != 0) {
        divider.integer = xtal_freq / freq_mhz;
        real_freq_mhz = (xtal_freq + divider.integer / 2) / divider.integer; /* round */
@@ -292,7 +316,6 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
            // no suitable divider
            return false;
        }
-
        source_freq_mhz = xtal_freq;
        source = SOC_CPU_CLK_SRC_XTAL;
    } else if (freq_mhz == 90) {
@@ -310,6 +333,30 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
        source = SOC_CPU_CLK_SRC_CPLL;
        source_freq_mhz = CLK_LL_PLL_360M_FREQ_MHZ;
        divider.integer = 1;
+    } else {
+        // unsupported frequency
+        return false;
+    }
+#else
+    if (freq_mhz <= xtal_freq && freq_mhz != 0) {
+        divider.integer = xtal_freq / freq_mhz;
+        real_freq_mhz = (xtal_freq + divider.integer / 2) / divider.integer; /* round */
+        if (real_freq_mhz != freq_mhz) {
+            // no suitable divider
+            return false;
+        }
+        source_freq_mhz = xtal_freq;
+        source = SOC_CPU_CLK_SRC_XTAL;
+    } else if (freq_mhz == 100) {
+        real_freq_mhz = freq_mhz;
+        source = SOC_CPU_CLK_SRC_CPLL;
+        source_freq_mhz = CLK_LL_PLL_400M_FREQ_MHZ;
+        divider.integer = 4;
+    } else if (freq_mhz == 200) {
+        real_freq_mhz = freq_mhz;
+        source = SOC_CPU_CLK_SRC_CPLL;
+        source_freq_mhz = CLK_LL_PLL_400M_FREQ_MHZ;
+        divider.integer = 2;
    } else if (freq_mhz == 400) {
        // If CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ selects 400MHz, then at app startup stage will need a CPLL calibration to raise its freq from 360MHz to 400MHz
        real_freq_mhz = freq_mhz;
@@ -320,6 +367,7 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
        // unsupported frequency
        return false;
    }
+#endif
    *out_config = (rtc_cpu_freq_config_t) {
        .source = source,
        .div = divider,
@@ -101,7 +101,12 @@ if(target STREQUAL "linux")
        target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-integer-overflow -Wno-shift-count-overflow)
    endif()
 else()
-    target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.ld")
+    # TODO: IDF-13410. Update to (CONFIG_ESP32P4_REV_MIN_FULL GREATER_EQUAL 200) when chip efuse is correct.
+    if(CONFIG_ESP32P4_REV_MIN_300)
+        target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.eco5.ld")
+    else()
+        target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.ld")
+    endif()
    rom_linker_script("api")
    if(NOT CONFIG_BT_CTRL_RUN_IN_FLASH_ONLY)
        if(target STREQUAL "esp32s3" OR target STREQUAL "esp32c3")
@@ -110,9 +115,17 @@ else()
    endif()

    if(CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB)
-        rom_linker_script("libgcc")
+        if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410
+            rom_linker_script("eco5.libgcc")
+        else()
+            rom_linker_script("libgcc")
+        endif()
    else()
-        rom_linker_script("rvfp")
+        if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410.
+            rom_linker_script("eco5.rvfp")
+        else()
+            rom_linker_script("rvfp")
+        endif()
    endif()
 endif()

@@ -151,6 +164,18 @@ if(BOOTLOADER_BUILD)
        endif()
    endif()

+    if(CONFIG_ESP_ROM_HAS_NEWLIB)
+        if(target STREQUAL "esp32" OR target STREQUAL "esp32s2")
+            rom_linker_script("newlib-funcs")
+        else()
+            if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410
+                rom_linker_script("eco5.newlib")
+            else()
+                rom_linker_script("newlib")
+            endif()
+        endif()
+    endif()
+

 else() # Regular app build
    if(target STREQUAL "esp32")
@@ -284,7 +309,11 @@ else() # Regular app build

    if(CONFIG_ESP_ROM_HAS_NEWLIB AND NOT target STREQUAL "esp32" AND NOT target STREQUAL "esp32s2")
        # ESP32 and S2 are a bit different, keep them as special cases in the target specific include section
-        rom_linker_script("newlib")
+        if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410
+            rom_linker_script("eco5.newlib")
+        else()
+            rom_linker_script("newlib")
+        endif()

        if(CONFIG_ESP_ROM_HAS_NEWLIB_NANO_FORMAT AND CONFIG_NEWLIB_NANO_FORMAT)
            if(NOT CONFIG_ESP_ROM_HAS_NEWLIB_32BIT_TIME AND NOT CONFIG_ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG)
@@ -24,5 +24,5 @@
 #define ESP_ROM_HAS_NEWLIB_NANO_FORMAT      (1) // ROM has the newlib nano version of formatting functions
 #define ESP_ROM_HAS_NEWLIB_NANO_PRINTF_FLOAT_BUG  (1) // ROM has the printf float bug with newlib nano version
 #define ESP_ROM_HAS_VERSION                 (1) // ROM has version/eco information
-#define ESP_ROM_CLIC_INT_TYPE_PATCH         (1) // ROM api esprv_intc_int_set_type configuring edge type interrupt is invalid
+#define ESP_ROM_CLIC_INT_TYPE_PATCH         (1) // ROM api esprv_intc_int_set_type configuring edge type interrupt is invalid TODO: IDF-13409
 #define ESP_ROM_HAS_OUTPUT_PUTC_FUNC        (1) // ROM has esp_rom_output_putc (or ets_write_char_uart)
@@ -0,0 +1,614 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32p4.rom.ld for esp32p4
+ *
+ *
+ * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum 56d78222be1daa0502090a078288f4d5
+ *
+ * Compatible with ROM where ECO version equal or greater to 5.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group common
+ ***************************************/
+
+/* Functions */
+rtc_get_reset_reason = 0x4fc00018;
+rtc_get_wakeup_cause = 0x4fc0001c;
+pmu_enable_unhold_pads = 0x4fc00020;
+ets_printf = 0x4fc00024;
+ets_install_putc1 = 0x4fc00028;
+ets_install_putc2 = 0x4fc0002c;
+ets_install_uart_printf = 0x4fc00030;
+ets_install_usb_printf = 0x4fc00034;
+ets_get_printf_channel = 0x4fc00038;
+ets_delay_us = 0x4fc0003c;
+ets_get_cpu_frequency = 0x4fc00040;
+ets_update_cpu_frequency = 0x4fc00044;
+ets_install_lock = 0x4fc00048;
+UartRxString = 0x4fc0004c;
+UartGetCmdLn = 0x4fc00050;
+uart_tx_one_char = 0x4fc00054;
+uart_tx_one_char2 = 0x4fc00058;
+uart_tx_one_char3 = 0x4fc0005c;
+uart_rx_one_char = 0x4fc00060;
+uart_rx_one_char_block = 0x4fc00064;
+uart_rx_intr_handler = 0x4fc00068;
+uart_rx_readbuff = 0x4fc0006c;
+uartAttach = 0x4fc00070;
+uart_tx_flush = 0x4fc00074;
+uart_tx_wait_idle = 0x4fc00078;
+uart_div_modify = 0x4fc0007c;
+ets_write_char_uart = 0x4fc00080;
+uart_tx_switch = 0x4fc00084;
+uart_buff_switch = 0x4fc00088;
+roundup2 = 0x4fc0008c;
+multofup = 0x4fc00090;
+software_reset = 0x4fc00094;
+software_reset_cpu = 0x4fc00098;
+ets_clk_assist_debug_clock_enable = 0x4fc0009c;
+clear_super_wdt_reset_flag = 0x4fc000a0;
+disable_default_watchdog = 0x4fc000a4;
+ets_set_appcpu_boot_addr = 0x4fc000a8;
+send_packet = 0x4fc000ac;
+recv_packet = 0x4fc000b0;
+GetUartDevice = 0x4fc000b4;
+UartDwnLdProc = 0x4fc000b8;
+GetSecurityInfoProc = 0x4fc000bc;
+Uart_Init = 0x4fc000c0;
+ets_set_user_start = 0x4fc000c4;
+/* Data (.data, .bss, .rodata) */
+ets_rom_layout_p = 0x4fc1fffc;
+ets_ops_table_ptr = 0x4ffbfff4;
+g_saved_pc = 0x4ffbfff8;
+
+
+/***************************************
+ Group miniz
+ ***************************************/
+
+/* Functions */
+mz_adler32 = 0x4fc000c8;
+mz_free = 0x4fc000cc;
+tdefl_compress = 0x4fc000d0;
+tdefl_compress_buffer = 0x4fc000d4;
+tdefl_compress_mem_to_heap = 0x4fc000d8;
+tdefl_compress_mem_to_mem = 0x4fc000dc;
+tdefl_compress_mem_to_output = 0x4fc000e0;
+tdefl_get_adler32 = 0x4fc000e4;
+tdefl_get_prev_return_status = 0x4fc000e8;
+tdefl_init = 0x4fc000ec;
+tdefl_write_image_to_png_file_in_memory = 0x4fc000f0;
+tdefl_write_image_to_png_file_in_memory_ex = 0x4fc000f4;
+tinfl_decompress = 0x4fc000f8;
+tinfl_decompress_mem_to_callback = 0x4fc000fc;
+tinfl_decompress_mem_to_heap = 0x4fc00100;
+tinfl_decompress_mem_to_mem = 0x4fc00104;
+
+
+/***************************************
+ Group spi_extmem_common
+ ***************************************/
+
+/* Functions */
+esp_rom_spi_cmd_config = 0x4fc00108;
+esp_rom_spi_cmd_start = 0x4fc0010c;
+esp_rom_spi_set_op_mode = 0x4fc00110;
+esp_rom_spi_set_dtr_swap_mode = 0x4fc00114;
+
+
+/***************************************
+ Group spiflash_legacy
+ ***************************************/
+
+/* Functions */
+esp_rom_spiflash_wait_idle = 0x4fc00118;
+esp_rom_spiflash_write_encrypted = 0x4fc0011c;
+esp_rom_spiflash_write_encrypted_dest = 0x4fc00120;
+esp_rom_spiflash_write_encrypted_enable = 0x4fc00124;
+esp_rom_spiflash_write_encrypted_disable = 0x4fc00128;
+esp_rom_spiflash_erase_chip = 0x4fc0012c;
+_esp_rom_spiflash_erase_sector = 0x4fc00130;
+_esp_rom_spiflash_erase_block = 0x4fc00134;
+_esp_rom_spiflash_write = 0x4fc00138;
+_esp_rom_spiflash_read = 0x4fc0013c;
+_esp_rom_spiflash_unlock = 0x4fc00140;
+_SPIEraseArea = 0x4fc00144;
+_SPI_write_enable = 0x4fc00148;
+esp_rom_spiflash_erase_sector = 0x4fc0014c;
+esp_rom_spiflash_erase_block = 0x4fc00150;
+esp_rom_spiflash_write = 0x4fc00154;
+esp_rom_spiflash_read = 0x4fc00158;
+esp_rom_spiflash_unlock = 0x4fc0015c;
+SPIEraseArea = 0x4fc00160;
+SPI_write_enable = 0x4fc00164;
+esp_rom_spiflash_config_param = 0x4fc00168;
+esp_rom_spiflash_read_user_cmd = 0x4fc0016c;
+esp_rom_spiflash_select_qio_pins = 0x4fc00170;
+esp_rom_spi_flash_auto_sus_res = 0x4fc00174;
+esp_rom_spi_flash_send_resume = 0x4fc00178;
+esp_rom_spi_flash_update_id = 0x4fc0017c;
+esp_rom_spiflash_config_clk = 0x4fc00180;
+esp_rom_spiflash_config_readmode = 0x4fc00184;
+esp_rom_spiflash_read_status = 0x4fc00188;
+esp_rom_spiflash_read_statushigh = 0x4fc0018c;
+esp_rom_spiflash_write_status = 0x4fc00190;
+esp_rom_spiflash_write_disable = 0x4fc00194;
+spi_cache_mode_switch = 0x4fc00198;
+spi_common_set_dummy_output = 0x4fc0019c;
+spi_common_set_flash_cs_timing = 0x4fc001a0;
+esp_rom_spi_set_address_bit_len = 0x4fc001a4;
+SPILock = 0x4fc001a8;
+SPIMasterReadModeCnfig = 0x4fc001ac;
+SPI_Common_Command = 0x4fc001b0;
+SPI_WakeUp = 0x4fc001b4;
+SPI_block_erase = 0x4fc001b8;
+SPI_chip_erase = 0x4fc001bc;
+SPI_init = 0x4fc001c0;
+SPI_page_program = 0x4fc001c4;
+SPI_read_data = 0x4fc001c8;
+SPI_sector_erase = 0x4fc001cc;
+SelectSpiFunction = 0x4fc001d0;
+SetSpiDrvs = 0x4fc001d4;
+Wait_SPI_Idle = 0x4fc001d8;
+spi_dummy_len_fix = 0x4fc001dc;
+Disable_QMode = 0x4fc001e0;
+Enable_QMode = 0x4fc001e4;
+spi_flash_attach = 0x4fc001e8;
+spi_flash_get_chip_size = 0x4fc001ec;
+spi_flash_guard_set = 0x4fc001f0;
+spi_flash_guard_get = 0x4fc001f4;
+spi_flash_read_encrypted = 0x4fc001f8;
+/* Data (.data, .bss, .rodata) */
+rom_spiflash_legacy_funcs = 0x4ffbffec;
+rom_spiflash_legacy_data = 0x4ffbffe8;
+g_flash_guard_ops = 0x4ffbfff0;
+
+
+/***************************************
+ Group hal_systimer
+ ***************************************/
+
+/* Functions */
+systimer_hal_init = 0x4fc00228;
+systimer_hal_deinit = 0x4fc0022c;
+systimer_hal_set_tick_rate_ops = 0x4fc00230;
+systimer_hal_get_counter_value = 0x4fc00234;
+systimer_hal_get_time = 0x4fc00238;
+systimer_hal_set_alarm_target = 0x4fc0023c;
+systimer_hal_set_alarm_period = 0x4fc00240;
+systimer_hal_get_alarm_value = 0x4fc00244;
+systimer_hal_enable_alarm_int = 0x4fc00248;
+systimer_hal_on_apb_freq_update = 0x4fc0024c;
+systimer_hal_counter_value_advance = 0x4fc00250;
+systimer_hal_enable_counter = 0x4fc00254;
+systimer_hal_select_alarm_mode = 0x4fc00258;
+systimer_hal_connect_alarm_counter = 0x4fc0025c;
+systimer_hal_counter_can_stall_by_cpu = 0x4fc00260;
+
+
+/***************************************
+ Group cache
+ ***************************************/
+
+/* Functions */
+Cache_Get_L1_ICache_Line_Size = 0x4fc003c4;
+Cache_Get_L1_DCache_Line_Size = 0x4fc003c8;
+Cache_Get_L2_Cache_Line_Size = 0x4fc003cc;
+Cache_Get_Mode = 0x4fc003d0;
+Cache_Set_L2_Cache_Mode = 0x4fc003d4;
+Cache_Address_Through_Cache = 0x4fc003d8;
+ROM_Boot_Cache_Init = 0x4fc003dc;
+Cache_Sync_Addr = 0x4fc003e0;
+Cache_Invalidate_Addr = 0x4fc003e4;
+Cache_Invalidate_Addr_Gid = 0x4fc003e8;
+Cache_Clean_Addr = 0x4fc003ec;
+Cache_Clean_Addr_Gid = 0x4fc003f0;
+Cache_WriteBack_Addr = 0x4fc003f4;
+Cache_WriteBack_Addr_Gid = 0x4fc003f8;
+Cache_WriteBack_Invalidate_Addr = 0x4fc003fc;
+Cache_WriteBack_Invalidate_Addr_Gid = 0x4fc00400;
+Cache_Invalidate_All = 0x4fc00404;
+Cache_Invalidate_All_Gid = 0x4fc00408;
+Cache_Clean_All = 0x4fc0040c;
+Cache_Clean_All_Gid = 0x4fc00410;
+Cache_WriteBack_All = 0x4fc00414;
+Cache_WriteBack_All_Gid = 0x4fc00418;
+Cache_WriteBack_Invalidate_All = 0x4fc0041c;
+Cache_WriteBack_Invalidate_All_Gid = 0x4fc00420;
+Cache_Mask_All = 0x4fc00424;
+Cache_Suspend_L1_CORE0_ICache_Autoload = 0x4fc00428;
+Cache_Resume_L1_CORE0_ICache_Autoload = 0x4fc0042c;
+Cache_Suspend_L1_CORE1_ICache_Autoload = 0x4fc00430;
+Cache_Resume_L1_CORE1_ICache_Autoload = 0x4fc00434;
+Cache_Suspend_L1_DCache_Autoload = 0x4fc00438;
+Cache_Resume_L1_DCache_Autoload = 0x4fc0043c;
+Cache_Suspend_L2_Cache_Autoload = 0x4fc00440;
+Cache_Resume_L2_Cache_Autoload = 0x4fc00444;
+Cache_Start_L1_CORE0_ICache_Preload = 0x4fc00448;
+Cache_L1_CORE0_ICache_Preload_Done = 0x4fc0044c;
+Cache_End_L1_CORE0_ICache_Preload = 0x4fc00450;
+Cache_Start_L1_CORE1_ICache_Preload = 0x4fc00454;
+Cache_L1_CORE1_ICache_Preload_Done = 0x4fc00458;
+Cache_End_L1_CORE1_ICache_Preload = 0x4fc0045c;
+Cache_Start_L1_DCache_Preload = 0x4fc00460;
+Cache_L1_DCache_Preload_Done = 0x4fc00464;
+Cache_End_L1_DCache_Preload = 0x4fc00468;
+Cache_Start_L2_Cache_Preload = 0x4fc0046c;
+Cache_L2_Cache_Preload_Done = 0x4fc00470;
+Cache_End_L2_Cache_Preload = 0x4fc00474;
+Cache_Config_L1_CORE0_ICache_Autoload = 0x4fc00478;
+Cache_Enable_L1_CORE0_ICache_Autoload = 0x4fc0047c;
+Cache_Disable_L1_CORE0_ICache_Autoload = 0x4fc00480;
+Cache_Config_L1_CORE1_ICache_Autoload = 0x4fc00484;
+Cache_Enable_L1_CORE1_ICache_Autoload = 0x4fc00488;
+Cache_Disable_L1_CORE1_ICache_Autoload = 0x4fc0048c;
+Cache_Config_L1_DCache_Autoload = 0x4fc00490;
+Cache_Enable_L1_DCache_Autoload = 0x4fc00494;
+Cache_Disable_L1_DCache_Autoload = 0x4fc00498;
+Cache_Config_L2_Cache_Autoload = 0x4fc0049c;
+Cache_Enable_L2_Cache_Autoload = 0x4fc004a0;
+Cache_Disable_L2_Cache_Autoload = 0x4fc004a4;
+Cache_Enable_L1_CORE0_ICache_PreLock = 0x4fc004a8;
+Cache_Disable_L1_CORE0_ICache_PreLock = 0x4fc004ac;
+Cache_Enable_L1_CORE1_ICache_PreLock = 0x4fc004b0;
+Cache_Disable_L1_CORE1_ICache_PreLock = 0x4fc004b4;
+Cache_Enable_L1_DCache_PreLock = 0x4fc004b8;
+Cache_Disable_L1_DCache_PreLock = 0x4fc004bc;
+Cache_Enable_L2_Cache_PreLock = 0x4fc004c0;
+Cache_Disable_L2_Cache_PreLock = 0x4fc004c4;
+Cache_Lock_Addr = 0x4fc004c8;
+Cache_Unlock_Addr = 0x4fc004cc;
+Cache_Disable_L1_CORE0_ICache = 0x4fc004d0;
+Cache_Enable_L1_CORE0_ICache = 0x4fc004d4;
+Cache_Suspend_L1_CORE0_ICache = 0x4fc004d8;
+Cache_Resume_L1_CORE0_ICache = 0x4fc004dc;
+Cache_Disable_L1_CORE1_ICache = 0x4fc004e0;
+Cache_Enable_L1_CORE1_ICache = 0x4fc004e4;
+Cache_Suspend_L1_CORE1_ICache = 0x4fc004e8;
+Cache_Resume_L1_CORE1_ICache = 0x4fc004ec;
+Cache_Disable_L1_DCache = 0x4fc004f0;
+Cache_Enable_L1_DCache = 0x4fc004f4;
+Cache_Suspend_L1_DCache = 0x4fc004f8;
+Cache_Resume_L1_DCache = 0x4fc004fc;
+Cache_Disable_L2_Cache = 0x4fc00500;
+Cache_Enable_L2_Cache = 0x4fc00504;
+Cache_Suspend_L2_Cache = 0x4fc00508;
+Cache_Resume_L2_Cache = 0x4fc0050c;
+Cache_FLASH_MMU_Init = 0x4fc00510;
+Cache_PSRAM_MMU_Init = 0x4fc00514;
+Cache_FLASH_MMU_Set = 0x4fc00518;
+Cache_FLASH_MMU_Set_Secure = 0x4fc0051c;
+Cache_PSRAM_MMU_Set = 0x4fc00520;
+Cache_PSRAM_MMU_Set_Secure = 0x4fc00524;
+Cache_Count_Flash_Pages = 0x4fc00528;
+Cache_Flash_To_SPIRAM_Copy = 0x4fc0052c;
+Cache_Set_IDROM_MMU_Size = 0x4fc00530;
+flash2spiram_instruction_offset = 0x4fc00534;
+flash2spiram_rodata_offset = 0x4fc00538;
+flash_instr_rodata_start_page = 0x4fc0053c;
+flash_instr_rodata_end_page = 0x4fc00540;
+Cache_Set_IDROM_MMU_Info = 0x4fc00544;
+Cache_Get_IROM_MMU_End = 0x4fc00548;
+Cache_Get_DROM_MMU_End = 0x4fc0054c;
+/* Data (.data, .bss, .rodata) */
+rom_cache_op_cb = 0x4ffbffdc;
+rom_cache_internal_table_ptr = 0x4ffbffd8;
+
+
+/***************************************
+ Group clock
+ ***************************************/
+
+/* Functions */
+ets_clk_get_xtal_freq = 0x4fc00550;
+ets_clk_get_cpu_freq = 0x4fc00554;
+
+
+/***************************************
+ Group gpio
+ ***************************************/
+
+/* Functions */
+gpio_set_output_level = 0x4fc00558;
+gpio_get_input_level = 0x4fc0055c;
+gpio_matrix_in = 0x4fc00560;
+gpio_matrix_out = 0x4fc00564;
+gpio_bypass_matrix_in = 0x4fc00568;
+gpio_output_disable = 0x4fc0056c;
+gpio_output_enable = 0x4fc00570;
+gpio_pad_input_disable = 0x4fc00574;
+gpio_pad_input_enable = 0x4fc00578;
+gpio_pad_pulldown = 0x4fc0057c;
+gpio_pad_pullup = 0x4fc00580;
+gpio_pad_select_gpio = 0x4fc00584;
+gpio_pad_set_drv = 0x4fc00588;
+gpio_pad_unhold = 0x4fc0058c;
+gpio_pad_hold = 0x4fc00590;
+gpio_lppad_select_mux = 0x4fc00594;
+gpio_ded_pad_set_drv = 0x4fc00598;
+gpio_ded_pad_pullup = 0x4fc0059c;
+gpio_ded_pad_pulldown = 0x4fc005a0;
+gpio_ded_pad_hold = 0x4fc005a4;
+gpio_ded_pad_unhold = 0x4fc005a8;
+
+
+/***************************************
+ Group interrupts
+ ***************************************/
+
+/* Functions */
+esprv_intc_int_set_priority = 0x4fc005ac;
+esprv_intc_int_set_threshold = 0x4fc005b0;
+esprv_intc_int_enable = 0x4fc005b4;
+esprv_intc_int_disable = 0x4fc005b8;
+esprv_intc_int_set_type = 0x4fc005bc;
+PROVIDE( intr_handler_set = 0x4fc005c0 );
+intr_matrix_set = 0x4fc005c4;
+ets_intr_lock = 0x4fc005c8;
+ets_intr_unlock = 0x4fc005cc;
+ets_isr_attach = 0x4fc005d0;
+ets_isr_mask = 0x4fc005d4;
+ets_isr_unmask = 0x4fc005d8;
+
+
+/***************************************
+ Group crypto
+ ***************************************/
+
+/* Functions */
+md5_vector = 0x4fc005dc;
+MD5Init = 0x4fc005e0;
+MD5Update = 0x4fc005e4;
+MD5Final = 0x4fc005e8;
+crc32_le = 0x4fc005ec;
+crc16_le = 0x4fc005f0;
+crc8_le = 0x4fc005f4;
+crc32_be = 0x4fc005f8;
+crc16_be = 0x4fc005fc;
+crc8_be = 0x4fc00600;
+esp_crc8 = 0x4fc00604;
+ets_sha_enable = 0x4fc00608;
+ets_sha_disable = 0x4fc0060c;
+ets_sha_get_state = 0x4fc00610;
+ets_sha_init = 0x4fc00614;
+ets_sha_process = 0x4fc00618;
+ets_sha_starts = 0x4fc0061c;
+ets_sha_update = 0x4fc00620;
+ets_sha_finish = 0x4fc00624;
+ets_sha_clone = 0x4fc00628;
+ets_hmac_enable = 0x4fc0062c;
+ets_hmac_disable = 0x4fc00630;
+ets_hmac_calculate_message = 0x4fc00634;
+ets_hmac_calculate_downstream = 0x4fc00638;
+ets_hmac_invalidate_downstream = 0x4fc0063c;
+ets_jtag_enable_temporarily = 0x4fc00640;
+ets_aes_enable = 0x4fc00644;
+ets_aes_disable = 0x4fc00648;
+ets_aes_setkey = 0x4fc0064c;
+ets_aes_block = 0x4fc00650;
+ets_aes_setkey_dec = 0x4fc00654;
+ets_aes_setkey_enc = 0x4fc00658;
+ets_bigint_enable = 0x4fc0065c;
+ets_bigint_disable = 0x4fc00660;
+ets_bigint_multiply = 0x4fc00664;
+ets_bigint_modmult = 0x4fc00668;
+ets_bigint_modexp = 0x4fc0066c;
+ets_bigint_wait_finish = 0x4fc00670;
+ets_bigint_getz = 0x4fc00674;
+ets_ds_enable = 0x4fc00678;
+ets_ds_disable = 0x4fc0067c;
+ets_ds_start_sign = 0x4fc00680;
+ets_ds_is_busy = 0x4fc00684;
+ets_ds_finish_sign = 0x4fc00688;
+ets_ds_encrypt_params = 0x4fc0068c;
+ets_mgf1_sha256 = 0x4fc00690;
+/* Data (.data, .bss, .rodata) */
+crc32_le_table_ptr = 0x4fc1fff8;
+crc16_le_table_ptr = 0x4fc1fff4;
+crc8_le_table_ptr = 0x4fc1fff0;
+crc32_be_table_ptr = 0x4fc1ffec;
+crc16_be_table_ptr = 0x4fc1ffe8;
+crc8_be_table_ptr = 0x4fc1ffe4;
+
+
+/***************************************
+ Group efuse
+ ***************************************/
+
+/* Functions */
+ets_efuse_read = 0x4fc00694;
+ets_efuse_program = 0x4fc00698;
+ets_efuse_clear_program_registers = 0x4fc0069c;
+ets_efuse_write_key = 0x4fc006a0;
+ets_efuse_get_read_register_address = 0x4fc006a4;
+ets_efuse_get_key_purpose = 0x4fc006a8;
+ets_efuse_key_block_unused = 0x4fc006ac;
+ets_efuse_find_unused_key_block = 0x4fc006b0;
+ets_efuse_rs_calculate = 0x4fc006b4;
+ets_efuse_count_unused_key_blocks = 0x4fc006b8;
+ets_efuse_secure_boot_enabled = 0x4fc006bc;
+ets_efuse_secure_boot_aggressive_revoke_enabled = 0x4fc006c0;
+ets_efuse_cache_encryption_enabled = 0x4fc006c4;
+ets_efuse_download_modes_disabled = 0x4fc006c8;
+ets_efuse_find_purpose = 0x4fc006cc;
+ets_efuse_force_send_resume = 0x4fc006d0;
+ets_efuse_get_flash_delay_us = 0x4fc006d4;
+ets_efuse_get_uart_print_control = 0x4fc006d8;
+ets_efuse_direct_boot_mode_disabled = 0x4fc006dc;
+ets_efuse_security_download_modes_enabled = 0x4fc006e0;
+ets_efuse_jtag_disabled = 0x4fc006e4;
+ets_efuse_usb_print_is_disabled = 0x4fc006e8;
+ets_efuse_usb_download_mode_disabled = 0x4fc006ec;
+ets_efuse_usb_device_disabled = 0x4fc006f0;
+ets_efuse_get_km_huk_gen_state = 0x4fc006f4;
+ets_efuse_get_km_deploy_only_once = 0x4fc006f8;
+ets_efuse_get_force_use_km_key = 0x4fc006fc;
+ets_efuse_xts_key_length_256 = 0x4fc00700;
+ets_efuse_get_km_key_lock = 0x4fc00704;
+
+
+/***************************************
+ Group key_mgr
+ ***************************************/
+
+/* Functions */
+esp_rom_check_recover_key = 0x4fc00708;
+esp_rom_km_huk_conf = 0x4fc0070c;
+esp_rom_km_huk_risk = 0x4fc00710;
+
+
+/***************************************
+ Group secureboot
+ ***************************************/
+
+/* Functions */
+ets_emsa_pss_verify = 0x4fc00714;
+ets_rsa_pss_verify = 0x4fc00718;
+ets_ecdsa_verify = 0x4fc0071c;
+ets_secure_boot_verify_bootloader_with_keys = 0x4fc00720;
+ets_secure_boot_verify_signature = 0x4fc00724;
+ets_secure_boot_read_key_digests = 0x4fc00728;
+ets_secure_boot_revoke_public_key_digest = 0x4fc0072c;
+
+
+/***************************************
+ Group usb_device_uart
+ ***************************************/
+
+/* Functions */
+usb_serial_device_rx_one_char = 0x4fc008a4;
+usb_serial_device_rx_one_char_block = 0x4fc008a8;
+usb_serial_device_tx_flush = 0x4fc008ac;
+usb_serial_device_tx_one_char = 0x4fc008b0;
+
+
+/***************************************
+ Group usb_dwcotg_uart
+ ***************************************/
+
+/* Functions */
+Uart_Init_USB = 0x4fc008b4;
+usb_serial_otg_rx_one_char = 0x4fc008b8;
+usb_serial_otg_rx_one_char_block = 0x4fc008bc;
+usb_serial_otg_tx_flush = 0x4fc008c0;
+usb_serial_otg_tx_one_char = 0x4fc008c4;
+/* Data (.data, .bss, .rodata) */
+uart_acm_dev = 0x4ffbffd4;
+
+
+/***************************************
+ Group usb_dwcotg_module
+ ***************************************/
+
+/* Functions */
+cdc_acm_class_handle_req = 0x4fc008c8;
+cdc_acm_init = 0x4fc008cc;
+cdc_acm_fifo_fill = 0x4fc008d0;
+cdc_acm_rx_fifo_cnt = 0x4fc008d4;
+cdc_acm_fifo_read = 0x4fc008d8;
+cdc_acm_irq_tx_enable = 0x4fc008dc;
+cdc_acm_irq_tx_disable = 0x4fc008e0;
+cdc_acm_irq_state_enable = 0x4fc008e4;
+cdc_acm_irq_state_disable = 0x4fc008e8;
+cdc_acm_irq_tx_ready = 0x4fc008ec;
+cdc_acm_irq_rx_enable = 0x4fc008f0;
+cdc_acm_irq_rx_disable = 0x4fc008f4;
+cdc_acm_irq_rx_ready = 0x4fc008f8;
+cdc_acm_irq_is_pending = 0x4fc008fc;
+cdc_acm_irq_callback_set = 0x4fc00900;
+cdc_acm_line_ctrl_set = 0x4fc00904;
+cdc_acm_line_ctrl_get = 0x4fc00908;
+cdc_acm_poll_out = 0x4fc0090c;
+chip_usb_dw_did_persist = 0x4fc00910;
+chip_usb_dw_init = 0x4fc00914;
+chip_usb_detach = 0x4fc00918;
+chip_usb_dw_prepare_persist = 0x4fc0091c;
+chip_usb_get_persist_flags = 0x4fc00920;
+chip_usb_set_persist_flags = 0x4fc00924;
+cpio_start = 0x4fc00928;
+cpio_feed = 0x4fc0092c;
+cpio_done = 0x4fc00930;
+cpio_destroy = 0x4fc00934;
+dfu_flash_init = 0x4fc00938;
+dfu_flash_erase = 0x4fc0093c;
+dfu_flash_program = 0x4fc00940;
+dfu_flash_read = 0x4fc00944;
+dfu_flash_attach = 0x4fc00948;
+dfu_cpio_callback = 0x4fc0094c;
+dfu_updater_get_err = 0x4fc00950;
+dfu_updater_clear_err = 0x4fc00954;
+dfu_updater_enable = 0x4fc00958;
+dfu_updater_begin = 0x4fc0095c;
+dfu_updater_feed = 0x4fc00960;
+dfu_updater_end = 0x4fc00964;
+dfu_updater_set_raw_addr = 0x4fc00968;
+dfu_updater_flash_read = 0x4fc0096c;
+usb_dc_prepare_persist = 0x4fc00970;
+usb_dw_isr_handler = 0x4fc00974;
+usb_dc_attach = 0x4fc00978;
+usb_dc_detach = 0x4fc0097c;
+usb_dc_reset = 0x4fc00980;
+usb_dc_set_address = 0x4fc00984;
+usb_dc_ep_check_cap = 0x4fc00988;
+usb_dc_ep_configure = 0x4fc0098c;
+usb_dc_ep_set_stall = 0x4fc00990;
+usb_dc_ep_clear_stall = 0x4fc00994;
+usb_dc_ep_halt = 0x4fc00998;
+usb_dc_ep_is_stalled = 0x4fc0099c;
+usb_dc_ep_enable = 0x4fc009a0;
+usb_dc_ep_disable = 0x4fc009a4;
+usb_dc_ep_flush = 0x4fc009a8;
+usb_dc_ep_write_would_block = 0x4fc009ac;
+usb_dc_ep_write = 0x4fc009b0;
+usb_dc_ep_read_wait = 0x4fc009b4;
+usb_dc_ep_read_continue = 0x4fc009b8;
+usb_dc_ep_read = 0x4fc009bc;
+usb_dc_ep_set_callback = 0x4fc009c0;
+usb_dc_set_status_callback = 0x4fc009c4;
+usb_dc_ep_mps = 0x4fc009c8;
+usb_dc_check_poll_for_interrupts = 0x4fc009cc;
+mac_addr_to_serial_str_desc = 0x4fc009d0;
+usb_set_current_descriptor = 0x4fc009d4;
+usb_get_descriptor = 0x4fc009d8;
+usb_dev_resume = 0x4fc009dc;
+usb_dev_get_configuration = 0x4fc009e0;
+usb_set_config = 0x4fc009e4;
+usb_deconfig = 0x4fc009e8;
+usb_enable = 0x4fc009ec;
+usb_disable = 0x4fc009f0;
+usb_write_would_block = 0x4fc009f4;
+usb_write = 0x4fc009f8;
+usb_read = 0x4fc009fc;
+usb_ep_set_stall = 0x4fc00a00;
+usb_ep_clear_stall = 0x4fc00a04;
+usb_ep_read_wait = 0x4fc00a08;
+usb_ep_read_continue = 0x4fc00a0c;
+usb_transfer_ep_callback = 0x4fc00a10;
+usb_transfer = 0x4fc00a14;
+usb_cancel_transfer = 0x4fc00a18;
+usb_transfer_sync = 0x4fc00a1c;
+usb_dfu_set_detach_cb = 0x4fc00a20;
+dfu_class_handle_req = 0x4fc00a24;
+dfu_status_cb = 0x4fc00a28;
+dfu_custom_handle_req = 0x4fc00a2c;
+usb_dfu_init = 0x4fc00a30;
+usb_dfu_force_detach = 0x4fc00a34;
+usb_dev_deinit = 0x4fc00a38;
+usb_dw_ctrl_deinit = 0x4fc00a3c;
+/* Data (.data, .bss, .rodata) */
+s_usb_osglue = 0x4ffbffc8;
+
+
+/***************************************
+ Group recovery_bootloader
+ ***************************************/
+
+/* Functions */
+ets_get_bootloader_offset = 0x4fc00a40;
+ets_set_bootloader_offset = 0x4fc00a44;
@@ -0,0 +1,58 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+esp_rom_newlib_init_common_mutexes = 0x4fc00264;
+memset = 0x4fc00268;
+strlen = 0x4fc00288;
+strstr = 0x4fc0028c;
+bzero = 0x4fc00290;
+sbrk = 0x4fc00298;
+isalnum = 0x4fc0029c;
+isalpha = 0x4fc002a0;
+isascii = 0x4fc002a4;
+isblank = 0x4fc002a8;
+iscntrl = 0x4fc002ac;
+isdigit = 0x4fc002b0;
+islower = 0x4fc002b4;
+isgraph = 0x4fc002b8;
+isprint = 0x4fc002bc;
+ispunct = 0x4fc002c0;
+isspace = 0x4fc002c4;
+isupper = 0x4fc002c8;
+toupper = 0x4fc002cc;
+tolower = 0x4fc002d0;
+toascii = 0x4fc002d4;
+memccpy = 0x4fc002d8;
+memchr = 0x4fc002dc;
+memrchr = 0x4fc002e0;
+strcasecmp = 0x4fc002e4;
+strcasestr = 0x4fc002e8;
+strcat = 0x4fc002ec;
+strchr = 0x4fc002f4;
+strcspn = 0x4fc002f8;
+strcoll = 0x4fc002fc;
+strlcat = 0x4fc00300;
+strlcpy = 0x4fc00304;
+strlwr = 0x4fc00308;
+strncasecmp = 0x4fc0030c;
+strncat = 0x4fc00310;
+strnlen = 0x4fc00318;
+strrchr = 0x4fc0031c;
+strsep = 0x4fc00320;
+strspn = 0x4fc00324;
+strtok_r = 0x4fc00328;
+strupr = 0x4fc0032c;
+longjmp = 0x4fc00330;
+setjmp = 0x4fc00334;
+abs = 0x4fc00338;
+div = 0x4fc0033c;
+labs = 0x4fc00340;
+ldiv = 0x4fc00344;
+qsort = 0x4fc00348;
+utoa = 0x4fc00358;
+itoa = 0x4fc0035c;
+/* Data (.data, .bss, .rodata) */
+syscall_table_ptr = 0x4ffbffe4;
+_global_impure_ptr = 0x4ffbffe0;
@@ -0,0 +1,95 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32p4.rom.libgcc.ld for esp32p4
+ *
+ *
+ * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum 56d78222be1daa0502090a078288f4d5
+ *
+ * Compatible with ROM where ECO version equal or greater to 5.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group libgccdf
+ ***************************************/
+
+/* Functions */
+__absvdi2 = 0x4fc00730;
+__absvsi2 = 0x4fc00734;
+__adddf3 = 0x4fc00738;
+__addvdi3 = 0x4fc0073c;
+__addvsi3 = 0x4fc00740;
+__ashldi3 = 0x4fc00744;
+__ashrdi3 = 0x4fc00748;
+__bswapdi2 = 0x4fc0074c;
+__bswapsi2 = 0x4fc00750;
+__clear_cache = 0x4fc00754;
+__clrsbdi2 = 0x4fc00758;
+__clrsbsi2 = 0x4fc0075c;
+__clzdi2 = 0x4fc00760;
+__clzsi2 = 0x4fc00764;
+__cmpdi2 = 0x4fc00768;
+__ctzdi2 = 0x4fc0076c;
+__ctzsi2 = 0x4fc00770;
+__divdc3 = 0x4fc00774;
+__divdf3 = 0x4fc00778;
+__divdi3 = 0x4fc0077c;
+__divsc3 = 0x4fc00780;
+__divsi3 = 0x4fc00784;
+__eqdf2 = 0x4fc00788;
+__extendsfdf2 = 0x4fc0078c;
+__ffsdi2 = 0x4fc00790;
+__ffssi2 = 0x4fc00794;
+__fixdfdi = 0x4fc00798;
+__fixdfsi = 0x4fc0079c;
+__fixsfdi = 0x4fc007a0;
+__fixunsdfsi = 0x4fc007a4;
+__fixunssfdi = 0x4fc007a8;
+__fixunssfsi = 0x4fc007ac;
+__floatdidf = 0x4fc007b0;
+__floatdisf = 0x4fc007b4;
+__floatsidf = 0x4fc007b8;
+__floatundidf = 0x4fc007bc;
+__floatundisf = 0x4fc007c0;
+__floatunsidf = 0x4fc007c4;
+__gcc_bcmp = 0x4fc007c8;
+__gedf2 = 0x4fc007cc;
+__gtdf2 = 0x4fc007d0;
+__ledf2 = 0x4fc007d4;
+__lshrdi3 = 0x4fc007d8;
+__ltdf2 = 0x4fc007dc;
+__moddi3 = 0x4fc007e0;
+__modsi3 = 0x4fc007e4;
+__muldc3 = 0x4fc007e8;
+__muldf3 = 0x4fc007ec;
+__muldi3 = 0x4fc007f0;
+__mulsc3 = 0x4fc007f4;
+__mulsi3 = 0x4fc007f8;
+__mulvdi3 = 0x4fc007fc;
+__mulvsi3 = 0x4fc00800;
+__nedf2 = 0x4fc00804;
+__negdf2 = 0x4fc00808;
+__negdi2 = 0x4fc0080c;
+__negvdi2 = 0x4fc00810;
+__negvsi2 = 0x4fc00814;
+__paritysi2 = 0x4fc00818;
+__popcountdi2 = 0x4fc0081c;
+__popcountsi2 = 0x4fc00820;
+__powidf2 = 0x4fc00824;
+__subdf3 = 0x4fc00828;
+__subvdi3 = 0x4fc0082c;
+__subvsi3 = 0x4fc00830;
+__ucmpdi2 = 0x4fc00834;
+__udivdi3 = 0x4fc00838;
+__udivmoddi4 = 0x4fc0083c;
+__udivsi3 = 0x4fc00840;
+__udiv_w_sdiv = 0x4fc00844;
+__umoddi3 = 0x4fc00848;
+__umodsi3 = 0x4fc0084c;
+__unorddf2 = 0x4fc00850;
+__extenddftf2 = 0x4fc00854;
+__trunctfdf2 = 0x4fc00858;
@@ -0,0 +1,99 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32p4.rom.newlib.ld for esp32p4
+ *
+ *
+ * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum 56d78222be1daa0502090a078288f4d5
+ *
+ * Compatible with ROM where ECO version equal or greater to 5.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group newlib
+ ***************************************/
+
+/* Functions */
+esp_rom_newlib_init_common_mutexes = 0x4fc00264;
+memset = 0x4fc00268;
+memcpy = 0x4fc0026c;
+memmove = 0x4fc00270;
+memcmp = 0x4fc00274;
+strcpy = 0x4fc00278;
+strncpy = 0x4fc0027c;
+strcmp = 0x4fc00280;
+strncmp = 0x4fc00284;
+strlen = 0x4fc00288;
+strstr = 0x4fc0028c;
+bzero = 0x4fc00290;
+_isatty_r = 0x4fc00294;
+sbrk = 0x4fc00298;
+isalnum = 0x4fc0029c;
+isalpha = 0x4fc002a0;
+isascii = 0x4fc002a4;
+isblank = 0x4fc002a8;
+iscntrl = 0x4fc002ac;
+isdigit = 0x4fc002b0;
+islower = 0x4fc002b4;
+isgraph = 0x4fc002b8;
+isprint = 0x4fc002bc;
+ispunct = 0x4fc002c0;
+isspace = 0x4fc002c4;
+isupper = 0x4fc002c8;
+toupper = 0x4fc002cc;
+tolower = 0x4fc002d0;
+toascii = 0x4fc002d4;
+memccpy = 0x4fc002d8;
+memchr = 0x4fc002dc;
+memrchr = 0x4fc002e0;
+strcasecmp = 0x4fc002e4;
+strcasestr = 0x4fc002e8;
+strcat = 0x4fc002ec;
+strdup = 0x4fc002f0;
+strchr = 0x4fc002f4;
+strcspn = 0x4fc002f8;
+strcoll = 0x4fc002fc;
+strlcat = 0x4fc00300;
+strlcpy = 0x4fc00304;
+strlwr = 0x4fc00308;
+strncasecmp = 0x4fc0030c;
+strncat = 0x4fc00310;
+strndup = 0x4fc00314;
+strnlen = 0x4fc00318;
+strrchr = 0x4fc0031c;
+strsep = 0x4fc00320;
+strspn = 0x4fc00324;
+strtok_r = 0x4fc00328;
+strupr = 0x4fc0032c;
+longjmp = 0x4fc00330;
+setjmp = 0x4fc00334;
+abs = 0x4fc00338;
+div = 0x4fc0033c;
+labs = 0x4fc00340;
+ldiv = 0x4fc00344;
+qsort = 0x4fc00348;
+rand_r = 0x4fc0034c;
+rand = 0x4fc00350;
+srand = 0x4fc00354;
+utoa = 0x4fc00358;
+itoa = 0x4fc0035c;
+atoi = 0x4fc00360;
+atol = 0x4fc00364;
+strtol = 0x4fc00368;
+strtoul = 0x4fc0036c;
+fflush = 0x4fc00370;
+_fflush_r = 0x4fc00374;
+_fwalk = 0x4fc00378;
+_fwalk_reent = 0x4fc0037c;
+__smakebuf_r = 0x4fc00380;
+__swhatbuf_r = 0x4fc00384;
+__swbuf_r = 0x4fc00388;
+__swbuf = 0x4fc0038c;
+__swsetup_r = 0x4fc00390;
+/* Data (.data, .bss, .rodata) */
+syscall_table_ptr = 0x4ffbffe4;
+_global_impure_ptr = 0x4ffbffe0;
@@ -0,0 +1,101 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/* ROM function interface esp32p4.rom.rvfp.ld for esp32p4
+ *
+ *
+ * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum 56d78222be1daa0502090a078288f4d5
+ *
+ * Compatible with ROM where ECO version equal or greater to 5.
+ *
+ * THIS FILE WAS AUTOMATICALLY GENERATED. DO NOT EDIT.
+ */
+
+/***************************************
+ Group rvfplibdf
+ ***************************************/
+
+/* Functions */
+__adddf3 = 0x4fc0085c;
+__eqdf2 = 0x4fc00860;
+__fixdfdi = 0x4fc00864;
+__fixdfsi = 0x4fc00868;
+__fixunsdfsi = 0x4fc00870;
+__floatdidf = 0x4fc00878;
+__floatsidf = 0x4fc0087c;
+__floatundidf = 0x4fc00880;
+__floatunsidf = 0x4fc00884;
+__gedf2 = 0x4fc00888;
+__gtdf2 = 0x4fc0088c;
+__ledf2 = 0x4fc00890;
+__ltdf2 = 0x4fc00894;
+__muldf3 = 0x4fc00898;
+__nedf2 = 0x4fc0089c;
+__subdf3 = 0x4fc008a0;
+
+/***************************************
+ Group libgcc
+***************************************/
+
+/* Functions */
+__absvdi2 = 0x4fc00730;
+__absvsi2 = 0x4fc00734;
+__addvdi3 = 0x4fc0073c;
+__addvsi3 = 0x4fc00740;
+__ashldi3 = 0x4fc00744;
+__ashrdi3 = 0x4fc00748;
+__bswapdi2 = 0x4fc0074c;
+__bswapsi2 = 0x4fc00750;
+__clear_cache = 0x4fc00754;
+__clrsbdi2 = 0x4fc00758;
+__clrsbsi2 = 0x4fc0075c;
+__clzdi2 = 0x4fc00760;
+__clzsi2 = 0x4fc00764;
+__cmpdi2 = 0x4fc00768;
+__ctzdi2 = 0x4fc0076c;
+__ctzsi2 = 0x4fc00770;
+__divdc3 = 0x4fc00774;
+__divdf3 = 0x4fc00778;
+__divdi3 = 0x4fc0077c;
+__divsc3 = 0x4fc00780;
+__divsi3 = 0x4fc00784;
+__extendsfdf2 = 0x4fc0078c;
+__ffsdi2 = 0x4fc00790;
+__ffssi2 = 0x4fc00794;
+__fixsfdi = 0x4fc007a0;
+__fixunssfdi = 0x4fc007a8;
+__fixunssfsi = 0x4fc007ac;
+__floatdisf = 0x4fc007b4;
+__floatundisf = 0x4fc007c0;
+__gcc_bcmp = 0x4fc007c8;
+__lshrdi3 = 0x4fc007d8;
+__moddi3 = 0x4fc007e0;
+__modsi3 = 0x4fc007e4;
+__muldc3 = 0x4fc007e8;
+__muldi3 = 0x4fc007f0;
+__mulsc3 = 0x4fc007f4;
+__mulsi3 = 0x4fc007f8;
+__mulvdi3 = 0x4fc007fc;
+__mulvsi3 = 0x4fc00800;
+__negdf2 = 0x4fc00808;
+__negdi2 = 0x4fc0080c;
+__negvdi2 = 0x4fc00810;
+__negvsi2 = 0x4fc00814;
+__paritysi2 = 0x4fc00818;
+__popcountdi2 = 0x4fc0081c;
+__popcountsi2 = 0x4fc00820;
+__powidf2 = 0x4fc00824;
+__subvdi3 = 0x4fc0082c;
+__subvsi3 = 0x4fc00830;
+__ucmpdi2 = 0x4fc00834;
+__udivdi3 = 0x4fc00838;
+__udivmoddi4 = 0x4fc0083c;
+__udivsi3 = 0x4fc00840;
+__udiv_w_sdiv = 0x4fc00844;
+__umoddi3 = 0x4fc00848;
+__umodsi3 = 0x4fc0084c;
+__unorddf2 = 0x4fc00850;
+__extenddftf2 = 0x4fc00854;
+__trunctfdf2 = 0x4fc00858;
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -1,12 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 /* ROM function interface esp32p4.rom.newlib-nano.ld for esp32p4
 *
 *
- * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum f6516bd9708d890f63db87f8aed53ca7
+ * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum 56d78222be1daa0502090a078288f4d5
 *
 * Compatible with ROM where ECO version equal or greater to 0.
 *
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -47,7 +47,7 @@ __subdf3 = 0x4fc008ac;
 Group libgcc
 ***************************************/

-/* Not part of the orginal ROM interface, but RVFP versions cannot work with float-abi */
+/* Not part of the original ROM interface, but RVFP versions cannot work with float-abi */
 __fixsfdi = 0x4fc007ac;
 __fixunssfdi = 0x4fc007b4;

@@ -1,8 +1,9 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
+
 /* ROM version variables for esp32p4
 *
 * These addresses should be compatible with any ROM version for this chip.
@@ -1,12 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
 /* ROM function interface esp32p4.rom.wdt.ld for esp32p4
 *
 *
- * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum f6516bd9708d890f63db87f8aed53ca7
+ * Generated from ./target/esp32p4/interface-esp32p4.yml md5sum 56d78222be1daa0502090a078288f4d5
 *
 * Compatible with ROM where ECO version equal or greater to 0.
 *
@@ -145,7 +145,8 @@ if(NOT BOOTLOADER_BUILD)
    endif()
 endif()

-if(CONFIG_SOC_MEM_NON_CONTIGUOUS_SRAM)
+# For P4, since P4 REV2, the SRAM is contiguous
+if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
    target_link_options(${COMPONENT_LIB} INTERFACE "-Wl,--enable-non-contiguous-regions")
 endif()

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2010-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2010-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -65,8 +65,13 @@ void bootloader_clock_configure(void)
 void esp_rtc_init(void)
 {
 #if SOC_PMU_SUPPORTED
+#if CONFIG_ESP32P4_REV_MIN_300
+    //TODO: IDF-13453
+    ESP_EARLY_LOGW(TAG, "pmu_init not supported\n");
+#else
    pmu_init();
 #endif
+#endif
 }

 void esp_clk_init(void)
@@ -15,6 +15,11 @@
 #include "sdkconfig.h"
 #include "ld.common"

+#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
+#define SRAM_START       0x4FF00000 + CONFIG_CACHE_L2_CACHE_SIZE
+#define SRAM_END         0x4FFAEFC0  /* 2nd stage bootloader iram_loader_seg start address */
+#define SRAM_SIZE        SRAM_END - SRAM_START
+#else
 #define SRAM_LOW_START     0x4FF00000
 #define SRAM_LOW_END       0x4FF2CBD0  /* 2nd stage bootloader iram_loader_seg start address */
 #define SRAM_LOW_SIZE      SRAM_LOW_END - SRAM_LOW_START
@@ -25,6 +30,7 @@
 #define SRAM_HIGH_START    0x4FF40000
 #define SRAM_HIGH_SIZE     0x80000 - CONFIG_CACHE_L2_CACHE_SIZE
 #define SRAM_HIGH_END      SRAM_HIGH_START + SRAM_HIGH_SIZE
+#endif

 #define IDROM_SEG_SIZE   (CONFIG_MMU_PAGE_SIZE << 10)

@@ -65,9 +71,12 @@ MEMORY
   * Shared data RAM, excluding memory reserved for ROM bss/data/stack.
   * Enabling Bluetooth & Trace Memory features in menuconfig will decrease the amount of RAM available.
   */
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
  sram_low (RWX) :                 org = SRAM_LOW_START, len = SRAM_LOW_SIZE
-
  sram_high (RW) :                org = SRAM_HIGH_START, len = SRAM_HIGH_SIZE
+#else
+  sram_seg (RWX) :                 org = SRAM_START, len = SRAM_SIZE
+#endif

 #if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
 #if CONFIG_SPIRAM_RODATA
@@ -0,0 +1,547 @@
+/*
+ * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "sdkconfig.h"
+#include "ld.common"
+
+/* Default entry point */
+ENTRY(call_start_cpu0);
+
+SECTIONS
+{
+  /**
+   * RTC fast memory holds RTC wake stub code,
+   * including from any source file named rtc_wake_stub*.c
+   */
+  .rtc.text :
+  {
+    /* Align the start of RTC code region as per PMP granularity
+     * this ensures we do not overwrite the permissions for the previous
+     * region (ULP mem/RTC reserved) regardless of their end alignment
+     */
+    ALIGNED_SYMBOL(_esp_pmp_align_size, _rtc_fast_start)
+    ALIGNED_SYMBOL(_esp_pmp_align_size, _rtc_text_start)
+
+    arrays[rtc_text]
+    mapping[rtc_text]
+
+    *rtc_wake_stub*.*(.text .text.*)
+    *(.rtc_text_end_test)
+
+    /* Align the end of RTC code region as per PMP granularity */
+    . = ALIGN(_esp_pmp_align_size);
+
+    ALIGNED_SYMBOL(4, _rtc_text_end)
+  } > lp_ram_seg
+
+  /**
+   * This section located in RTC FAST Memory area.
+   * It holds data marked with RTC_FAST_ATTR attribute.
+   * See the file "esp_attr.h" for more information.
+   */
+  .rtc.force_fast :
+  {
+    ALIGNED_SYMBOL(4, _rtc_force_fast_start)
+
+    arrays[rtc_force_fast]
+    mapping[rtc_force_fast]
+
+    *(.rtc.force_fast .rtc.force_fast.*)
+
+    ALIGNED_SYMBOL(4, _rtc_force_fast_end)
+  } > lp_ram_seg
+
+  /**
+   * RTC data section holds RTC wake stub
+   * data/rodata, including from any source file
+   * named rtc_wake_stub*.c and the data marked with
+   * RTC_DATA_ATTR, RTC_RODATA_ATTR attributes.
+   */
+  .rtc.data :
+  {
+    _rtc_data_start = ABSOLUTE(.);
+
+    arrays[rtc_data]
+    mapping[rtc_data]
+
+    *rtc_wake_stub*.*(.data .rodata .data.* .rodata.* .srodata.*)
+
+    _rtc_data_end = ABSOLUTE(.);
+  } > lp_ram_seg
+
+  /* RTC bss, from any source file named rtc_wake_stub*.c */
+  .rtc.bss (NOLOAD) :
+  {
+    _rtc_bss_start = ABSOLUTE(.);
+
+    *rtc_wake_stub*.*(.bss .bss.* .sbss .sbss.*)
+    *rtc_wake_stub*.*(COMMON)
+
+    arrays[rtc_bss]
+    mapping[rtc_bss]
+
+    _rtc_bss_end = ABSOLUTE(.);
+  } > lp_ram_seg
+
+  /**
+   * This section holds data that should not be initialized at power up
+   * and will be retained during deep sleep.
+   * User data marked with RTC_NOINIT_ATTR will be placed
+   * into this section. See the file "esp_attr.h" for more information.
+   */
+  .rtc_noinit (NOLOAD):
+  {
+    ALIGNED_SYMBOL(4, _rtc_noinit_start)
+
+    *(.rtc_noinit .rtc_noinit.*)
+
+    ALIGNED_SYMBOL(4, _rtc_noinit_end)
+  } > lp_ram_seg
+
+  /**
+   * This section located in RTC SLOW Memory area.
+   * It holds data marked with RTC_SLOW_ATTR attribute.
+   * See the file "esp_attr.h" for more information.
+   */
+  .rtc.force_slow :
+  {
+    ALIGNED_SYMBOL(4, _rtc_force_slow_start)
+
+    *(.rtc.force_slow .rtc.force_slow.*)
+
+    ALIGNED_SYMBOL(4, _rtc_force_slow_end)
+  } > lp_ram_seg
+
+  /**
+   * This section holds RTC data that should have fixed addresses.
+   * The data are not initialized at power-up and are retained during deep
+   * sleep.
+   */
+  .rtc_reserved (NOLOAD):
+  {
+    ALIGNED_SYMBOL(4, _rtc_reserved_start)
+
+    KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*))
+    *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*)
+
+    /**
+     * New data can only be added here to ensure existing data are not moved.
+     * Because data have adhered to the beginning of the segment and code is relied
+     * on it.
+     * >> put new data here <<
+     */
+
+    _rtc_reserved_end = ABSOLUTE(.);
+  } > rtc_reserved_seg
+
+  _rtc_reserved_length = _rtc_reserved_end - _rtc_reserved_start;
+  _rtc_ulp_memory_start = _rtc_reserved_start + LENGTH(rtc_reserved_seg);
+  ASSERT((_rtc_reserved_length <= LENGTH(rtc_reserved_seg)),
+          "RTC reserved segment data does not fit.")
+
+  /* Get size of rtc slow data based on rtc_data_location alias */
+  _rtc_slow_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
+                        ? (_rtc_force_slow_end - _rtc_data_start)
+                        : (_rtc_force_slow_end - _rtc_force_slow_start);
+
+  _rtc_fast_length = (ORIGIN(rtc_slow_seg) == ORIGIN(rtc_data_location))
+                        ? (_rtc_force_fast_end - _rtc_fast_start)
+                        : (_rtc_noinit_end - _rtc_fast_start);
+
+  ASSERT((_rtc_slow_length <= LENGTH(rtc_slow_seg)),
+          "RTC_SLOW segment data does not fit.")
+
+  ASSERT((_rtc_fast_length <= LENGTH(rtc_data_seg)),
+          "RTC_FAST segment data does not fit.")
+
+  .tcm.text :
+  {
+    /* Code marked as running out of TCM */
+    _tcm_text_start = ABSOLUTE(.);
+
+    arrays[tcm_text]
+    mapping[tcm_text]
+
+    _tcm_text_end = ABSOLUTE(.);
+  } > tcm_idram_seg
+
+  .tcm.data :
+  {
+    _tcm_data_start = ABSOLUTE(.);
+
+    arrays[tcm_data]
+    mapping[tcm_data]
+
+    _tcm_data_end = ABSOLUTE(.);
+  } > tcm_idram_seg
+
+  .iram0.text :
+  {
+    _iram_start = ABSOLUTE(.);
+    /* Vectors go to start of IRAM */
+    ASSERT(ABSOLUTE(.) % 0x40 == 0, "vector address must be 64 byte aligned");
+    KEEP(*(.exception_vectors_table.text));
+    KEEP(*(.exception_vectors.text));
+
+    /* Code marked as running out of IRAM */
+    _iram_text_start = ABSOLUTE(.);
+
+    mapping[iram0_text]
+
+  } > sram_seg
+
+  /* Marks the end of IRAM code segment */
+  .iram0.text_end (NOLOAD) :
+  {
+    /* Align the end of code region as per PMP region granularity */
+    . = ALIGN(_esp_pmp_align_size);
+
+    ALIGNED_SYMBOL(4, _iram_text_end)
+  } > sram_seg
+
+  .iram0.data :
+  {
+    ALIGNED_SYMBOL(16, _iram_data_start)
+
+    mapping[iram0_data]
+
+    _iram_data_end = ABSOLUTE(.);
+  } > sram_seg
+
+  .iram0.bss (NOLOAD) :
+  {
+    ALIGNED_SYMBOL(16, _iram_bss_start)
+
+    mapping[iram0_bss]
+
+    _iram_bss_end = ABSOLUTE(.);
+
+    ALIGNED_SYMBOL(16, _iram_end)
+  } > sram_seg
+
+  /**
+   * This section is required to skip .iram0.text area because sram_seg and
+   * sram_seg reflect the same address space on different buses.
+   */
+  .dram0.dummy (NOLOAD):
+  {
+    . = ORIGIN(sram_seg) + _iram_end - _iram_start;
+  } > sram_seg
+
+  .dram0.data :
+  {
+    _data_start = ABSOLUTE(.);
+    *(.gnu.linkonce.d.*)
+    *(.data1)
+    __global_pointer$ = . + 0x800;
+    *(.sdata)
+    *(.sdata.*)
+    *(.gnu.linkonce.s.*)
+    *(.gnu.linkonce.s2.*)
+    *(.jcr)
+
+    mapping[dram0_data]
+
+    _data_end = ABSOLUTE(.);
+  } > sram_seg
+
+  /**
+   * This section holds data that should not be initialized at power up.
+   * The section located in Internal SRAM memory region. The macro _NOINIT
+   * can be used as attribute to place data into this section.
+   * See the "esp_attr.h" file for more information.
+   */
+  .noinit (NOLOAD):
+  {
+    ALIGNED_SYMBOL(4, _noinit_start)
+
+    *(.noinit .noinit.*)
+
+    ALIGNED_SYMBOL(4, _noinit_end)
+  } > sram_seg
+
+    .dram0.bss (NOLOAD) :
+  {
+    ALIGNED_SYMBOL(4, _bss_start)
+
+    /**
+     * ldgen places all bss-related data to mapping[dram0_bss]
+     * (See components/esp_system/app.lf).
+     */
+    mapping[dram0_bss]
+
+    ALIGNED_SYMBOL(4, _bss_end)
+  } > sram_seg
+
+  /* Marks the end of data, bss and possibly rodata */
+  .dram0.heap_start (NOLOAD) :
+  {
+    ALIGNED_SYMBOL(16, _heap_start)
+  } > sram_seg
+
+  ASSERT(((_heap_start - ORIGIN(sram_seg)) <= LENGTH(sram_seg)), "DRAM segment data does not fit.")
+
+  .flash.text :
+  {
+    _stext = .;
+    /**
+     * Mark the start of flash.text.
+     * This can be used by the MMU driver to maintain the virtual address.
+     */
+    _instruction_reserved_start = ABSOLUTE(.);
+    _text_start = ABSOLUTE(.);
+
+    arrays[flash_text]
+    mapping[flash_text]
+
+    *(.stub)
+    *(.gnu.linkonce.t.*)
+    *(.gnu.warning)
+    *(.irom0.text) /* catch stray ICACHE_RODATA_ATTR */
+
+    /**
+     * CPU will try to prefetch up to 16 bytes of of instructions.
+     * This means that any configuration (e.g. MMU, PMS) must allow
+     * safe access to up to 16 bytes after the last real instruction, add
+     * dummy bytes to ensure this
+     */
+    . += _esp_flash_mmap_prefetch_pad_size;
+
+#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION
+    /* Align the end of flash text region as per PMP granularity to allow using the
+     * page alignment gap created while mapping the flash region into the PSRAM memory.
+     */
+    . = ALIGN(_esp_pmp_align_size);
+#endif // CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION
+
+    _text_end = ABSOLUTE(.);
+    /**
+     * Mark the flash.text end.
+     * This can be used for MMU driver to maintain virtual address.
+     */
+    _instruction_reserved_end = ABSOLUTE(.);
+    _etext = .;
+
+    /**
+     * Similar to _iram_start, this symbol goes here so it is
+     * resolved by addr2line in preference to the first symbol in
+     * the flash.text segment.
+     */
+    _flash_cache_start = ABSOLUTE(0);
+  } > text_seg_low
+
+  /**
+   * Dummy section represents the .flash.text section but in default_rodata_seg.
+   * Thus, it must have its alignment and (at least) its size.
+   */
+  .flash_rodata_dummy (NOLOAD):
+  {
+    _flash_rodata_dummy_start = .;
+
+    . = ALIGN(ALIGNOF(.flash.text)) + SIZEOF(.flash.text);
+
+    /* Add alignment of MMU page size + 0x20 bytes for the mapping header. */
+    . = ALIGN(_esp_mmu_page_size) + 0x20;
+  } > rodata_seg_low
+
+  .flash.appdesc : ALIGN(0x10)
+  {
+    /**
+     * Mark flash.rodata start.
+     * This can be used for mmu driver to maintain virtual address
+     */
+    _rodata_reserved_start = ABSOLUTE(.);
+    _rodata_start = ABSOLUTE(.);
+
+    /* !DO NOT PUT ANYTHING BEFORE THIS! */
+
+    /* Should be the first.  App version info. */
+    *(.rodata_desc .rodata_desc.*)
+    /* Should be the second. Custom app version info. */
+    *(.rodata_custom_desc .rodata_custom_desc.*)
+
+    /**
+     * Create an empty gap within this section. Thanks to this, the end of this
+     * section will match .flash.rodata's begin address. Thus, both sections
+     * will be merged when creating the final bin image.
+     */
+    . = ALIGN(ALIGNOF(.flash.rodata));
+  } > rodata_seg_low
+  ASSERT_SECTIONS_GAP(.flash.appdesc, .flash.rodata)
+
+  .flash.rodata : ALIGN(0x10)
+  {
+    _flash_rodata_start = ABSOLUTE(.);
+
+    arrays[flash_rodata]
+    mapping[flash_rodata]
+
+    *(.irom1.text) /* catch stray ICACHE_RODATA_ATTR */
+    *(.gnu.linkonce.r.*)
+    *(.rodata1)
+    *(.gcc_except_table .gcc_except_table.*)
+    *(.gnu.linkonce.e.*)
+    . = ALIGN(ALIGNOF(.flash.init_array));
+  } > rodata_seg_low
+  ASSERT_SECTIONS_GAP(.flash.rodata, .flash.init_array)
+
+  .flash.init_array :
+  {
+    /**
+     * C++ constructor tables.
+     *
+     * Excluding crtbegin.o/crtend.o since IDF doesn't use the toolchain crt.
+     *
+     * RISC-V gcc is configured with --enable-initfini-array so it emits
+     * .init_array section instead. But the init_priority sections will be
+     * sorted for iteration in ascending order during startup.
+     * The rest of the init_array sections is sorted for iteration in descending
+     * order during startup, however. Hence a different section is generated for
+     * the init_priority functions which is iterated in ascending order during
+     * startup. The corresponding code can be found in startup.c.
+     */
+    ALIGNED_SYMBOL(4, __init_priority_array_start)
+    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array.*))
+    __init_priority_array_end = ABSOLUTE(.);
+
+    ALIGNED_SYMBOL(4, __init_array_start)
+    KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .init_array))
+    __init_array_end = ABSOLUTE(.);
+
+    /* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */
+    ALIGNED_SYMBOL(4, soc_reserved_memory_region_start)
+    KEEP (*(.reserved_memory_address))
+    soc_reserved_memory_region_end = ABSOLUTE(.);
+
+    /* System init functions registered via ESP_SYSTEM_INIT_FN */
+    ALIGNED_SYMBOL(4, _esp_system_init_fn_array_start)
+    KEEP (*(SORT_BY_INIT_PRIORITY(.esp_system_init_fn.*)))
+    _esp_system_init_fn_array_end = ABSOLUTE(.);
+
+    _rodata_end = ABSOLUTE(.);
+    . = ALIGN(ALIGNOF(.eh_frame_hdr));
+  } > rodata_seg_low
+  ASSERT_SECTIONS_GAP(.flash.init_array, .eh_frame_hdr)
+
+  .eh_frame_hdr :
+  {
+#if CONFIG_COMPILER_CXX_EXCEPTIONS || CONFIG_ESP_SYSTEM_USE_EH_FRAME
+    ALIGNED_SYMBOL(4, __eh_frame_hdr)
+
+    KEEP (*(.eh_frame_hdr))
+
+    __eh_frame_hdr_end = ABSOLUTE(.);
+#endif // CONFIG_COMPILER_CXX_EXCEPTIONS || CONFIG_ESP_SYSTEM_USE_EH_FRAME
+
+    . = ALIGN(ALIGNOF(.eh_frame));
+  } > rodata_seg_low
+  ASSERT_SECTIONS_GAP(.eh_frame_hdr, .eh_frame)
+
+  .eh_frame :
+  {
+#if CONFIG_COMPILER_CXX_EXCEPTIONS || CONFIG_ESP_SYSTEM_USE_EH_FRAME
+    ALIGNED_SYMBOL(4, __eh_frame)
+
+    KEEP (*(.eh_frame))
+    /**
+     * As we are not linking with crtend.o, which includes the CIE terminator
+     * (see __FRAME_END__ in libgcc sources), it is manually provided here.
+     */
+    LONG(0);
+
+    __eh_frame_end = ABSOLUTE(.);
+#endif // CONFIG_COMPILER_CXX_EXCEPTIONS || CONFIG_ESP_SYSTEM_USE_EH_FRAME
+
+    . = ALIGN(ALIGNOF(.flash.tdata));
+  } > rodata_seg_low
+  ASSERT_SECTIONS_GAP(.eh_frame, .flash.tdata)
+
+  .flash.tdata :
+  {
+    _thread_local_data_start = ABSOLUTE(.);
+
+    *(.tdata .tdata.* .gnu.linkonce.td.*)
+
+    . = ALIGN(ALIGNOF(.flash.tbss));
+
+#if CONFIG_SPIRAM_RODATA && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION
+    /* Align the end of flash rodata region as per PMP granularity to allow using the
+     * page alignment gap created while mapping the flash region into the PSRAM memory.
+     */
+    . = ALIGN(_esp_pmp_align_size);
+#endif // CONFIG_SPIRAM_RODATA && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION
+
+    _thread_local_data_end = ABSOLUTE(.);
+  } > rodata_seg_low
+  ASSERT_SECTIONS_GAP(.flash.tdata, .flash.tbss)
+
+  .flash.tbss (NOLOAD) :
+  {
+    _thread_local_bss_start = ABSOLUTE(.);
+
+    *(.tbss .tbss.* .gnu.linkonce.tb.*)
+    *(.tcommon .tcommon.*)
+
+    _thread_local_bss_end = ABSOLUTE(.);
+  } > rodata_seg_low
+
+  /**
+   * This section contains all the rodata that is not used
+   * at runtime, helping to avoid an increase in binary size.
+   */
+  .flash.rodata_noload (NOLOAD) :
+  {
+    /**
+     * This symbol marks the end of flash.rodata. It can be utilized by the MMU
+     * driver to maintain the virtual address.
+     * NOLOAD rodata may not be included in this section.
+     */
+    _rodata_reserved_end = ADDR(.flash.tbss);
+
+    arrays[rodata_noload]
+    mapping[rodata_noload]
+  } > rodata_seg_low
+
+#if CONFIG_SPIRAM_XIP_FROM_PSRAM
+  /**
+   * This section is required to skip flash sections, because `extern_ram_seg`
+   * and `drom_seg` / `irom_seg` are on the same bus when xip on psram
+   */
+  .ext_ram.dummy (NOLOAD):
+  {
+    . = ORIGIN(ext_ram_seg) + (_rodata_reserved_end - _flash_rodata_dummy_start);
+    . = ALIGN (_esp_mmu_page_size);
+  } > ext_ram_seg
+#endif  //CONFIG_SPIRAM_XIP_FROM_PSRAM
+
+#if CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
+  /* This section holds .ext_ram.bss data, and will be put in PSRAM */
+  .ext_ram.bss (NOLOAD) :
+  {
+    _ext_ram_bss_start = ABSOLUTE(.);
+    arrays[extern_ram]
+    mapping[extern_ram]
+    ALIGNED_SYMBOL(4, _ext_ram_bss_end)
+  } > ext_ram_seg
+#endif  //CONFIG_SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY
+
+#if CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY
+  /**
+   * This section holds data that won't be initialised when startup.
+   * This section locates in External RAM region.
+   */
+  .ext_ram_noinit (NOLOAD) :
+  {
+    _ext_ram_noinit_start = ABSOLUTE(.);
+
+    *(.ext_ram_noinit*)
+
+    ALIGNED_SYMBOL(4, _ext_ram_noinit_end)
+  } > ext_ram_seg
+#endif //CONFIG_SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY
+
+#include "elf_misc.ld.in"
+}
@@ -48,6 +48,10 @@ preprocess_linker_file("memory.ld.in" "memory.ld" ld_out_path)
 target_linker_script(${COMPONENT_LIB} INTERFACE "${ld_out_path}")

 # Generate sections.ld.in and pass it through linker script generator
-preprocess_linker_file("sections.ld.in" "sections.ld.in" ld_out_path)
+if(CONFIG_ESP32P4_REV_MIN_300)
+    preprocess_linker_file("sections.rev3.ld.in" "sections.ld.in" ld_out_path)
+else()
+    preprocess_linker_file("sections.ld.in" "sections.ld.in" ld_out_path)
+endif()
 target_linker_script(${COMPONENT_LIB} INTERFACE "${ld_out_path}"
                    PROCESS "${CMAKE_CURRENT_BINARY_DIR}/ld/sections.ld")
@@ -121,13 +121,13 @@
 #include "esp_private/startup_internal.h"
 #include "esp_private/system_internal.h"

-#if SOC_MEM_NON_CONTIGUOUS_SRAM
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 extern int _bss_start_low, _bss_start_high;
 extern int _bss_end_low, _bss_end_high;
 #else
 extern int _bss_start;
 extern int _bss_end;
-#endif // SOC_MEM_NON_CONTIGUOUS_SRAM
+#endif // CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 extern int _rtc_bss_start;
 extern int _rtc_bss_end;
 #if CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
@@ -431,12 +431,12 @@ void IRAM_ATTR call_start_cpu0(void)
 #endif

    //Clear BSS. Please do not attempt to do any complex stuff (like early logging) before this.
-#if SOC_MEM_NON_CONTIGUOUS_SRAM
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
    memset(&_bss_start_low, 0, (&_bss_end_low - &_bss_start_low) * sizeof(_bss_start_low));
    memset(&_bss_start_high, 0, (&_bss_end_high - &_bss_start_high) * sizeof(_bss_start_high));
 #else
    memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
-#endif // SOC_MEM_NON_CONTIGUOUS_SRAM
+#endif // CONFIG_ESP32P4_SELECTS_REV_LESS_V3

 #if CONFIG_BT_LE_RELEASE_IRAM_SUPPORTED
    // Clear Bluetooth bss
@@ -523,12 +523,6 @@ void IRAM_ATTR call_start_cpu0(void)
    Cache_Resume_DCache(0);
 #endif // CONFIG_IDF_TARGET_ESP32S3

-#if CONFIG_IDF_TARGET_ESP32P4
-    //TODO: IDF-5670, add cache init API
-    extern void esp_config_l2_cache_mode(void);
-    esp_config_l2_cache_mode();
-#endif
-
 #if ESP_ROM_NEEDS_SET_CACHE_MMU_SIZE
 #if CONFIG_APP_BUILD_TYPE_ELF_RAM
    // For RAM loadable ELF case, we don't need to reserve IROM/DROM as instructions and data
@@ -1,7 +1,8 @@
 choice ESP_DEFAULT_CPU_FREQ_MHZ
    prompt "CPU frequency"
    default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA || ESP_BRINGUP_BYPASS_CPU_CLK_SETTING
-    default ESP_DEFAULT_CPU_FREQ_MHZ_360
+    default ESP_DEFAULT_CPU_FREQ_MHZ_360 if ESP32P4_SELECTS_REV_LESS_V3
+    default ESP_DEFAULT_CPU_FREQ_MHZ_400
    help
        CPU frequency to be set on application startup.

@@ -10,9 +11,13 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
        depends on IDF_ENV_FPGA || ESP_BRINGUP_BYPASS_CPU_CLK_SETTING
    config ESP_DEFAULT_CPU_FREQ_MHZ_360
        bool "360 MHz"
+        depends on ESP32P4_SELECTS_REV_LESS_V3
+    config ESP_DEFAULT_CPU_FREQ_MHZ_400
+        bool "400 MHz"
 endchoice

 config ESP_DEFAULT_CPU_FREQ_MHZ
    int
    default 40 if ESP_DEFAULT_CPU_FREQ_MHZ_40
    default 360 if ESP_DEFAULT_CPU_FREQ_MHZ_360
+    default 400 if ESP_DEFAULT_CPU_FREQ_MHZ_400
@@ -55,6 +55,31 @@ void s_cache_hal_init_ctx(void)
    ctx.l2.i_autoload_en = cache_ll_is_cache_autoload_enabled(2, CACHE_TYPE_INSTRUCTION, CACHE_LL_ID_ALL);
 }

+#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+//TODO: IDF-5670, add cache init API, then don't need sdkconfig
+void cache_hal_init_l2_cache(void)
+{
+    cache_size_t cache_size;
+    cache_line_size_t cache_line_size;
+#if CONFIG_CACHE_L2_CACHE_128KB
+    cache_size = CACHE_SIZE_128K;
+#elif CONFIG_CACHE_L2_CACHE_256KB
+    cache_size = CACHE_SIZE_256K;
+#else
+    cache_size = CACHE_SIZE_512K;
+#endif
+
+#if CONFIG_CACHE_L2_CACHE_LINE_64B
+    cache_line_size = CACHE_LINE_SIZE_64B;
+#else
+    cache_line_size = CACHE_LINE_SIZE_128B;
+#endif
+
+    Cache_Set_L2_Cache_Mode(cache_size, 8, cache_line_size);
+    Cache_Invalidate_All(CACHE_MAP_L2_CACHE);
+}
+#endif
+
 void cache_hal_init(void)
 {
    s_cache_hal_init_ctx();
@@ -78,6 +103,10 @@ void cache_hal_init(void)
    ctx.l2.i_cache_enabled = 1;
    ctx.l2.d_cache_enabled = 1;
 #endif
+
+#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
+    cache_hal_init_l2_cache();
+#endif
 }

 #if CACHE_LL_ENABLE_DISABLE_STATE_SW
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -74,8 +74,19 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
 /**
 * Register the shared buffer area of the last memory block into the heap during heap initialization
 */
-#define APP_USABLE_DIRAM_END    (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE) // 0x4ff3cfc0 - 0x2000 = 0x4ff3afc0
-#define STARTUP_DATA_SIZE      (SOC_DRAM_HIGH - CONFIG_CACHE_L2_CACHE_SIZE - APP_USABLE_DIRAM_END) // 0x4ffc0000 - 0x20000/0x40000/0x80000 - 0x4ff3afc0 = 0x65040 / 0x45040 / 0x5040
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
+#define ROM_STACK_START         (SOC_ROM_STACK_START)
+#define APP_USABLE_DIRAM_END    (ROM_STACK_START - SOC_ROM_STACK_SIZE) // 0x4ff3cfc0 - 0x2000 = 0x4ff3afc0
+#define STARTUP_DATA_SIZE       (SOC_DRAM_HIGH - CONFIG_CACHE_L2_CACHE_SIZE - APP_USABLE_DIRAM_END) // 0x4ffc0000 - 0x20000/0x40000/0x80000 - 0x4ff3afc0 = 0x65040 / 0x45040 / 0x5040
+#define SOC_DRAM_USABLE_LOW     (SOC_DRAM_LOW)
+#define SOC_IRAM_USABLE_LOW     (SOC_IRAM_LOW)
+#else
+#define ROM_STACK_START         (SOC_ROM_STACK_START_REV2)
+#define APP_USABLE_DIRAM_END    (ROM_STACK_START - SOC_ROM_STACK_SIZE) // 0x4ffbcfc0 - 0x2000 = 0x4ffbafc0
+#define STARTUP_DATA_SIZE       (SOC_DRAM_HIGH - APP_USABLE_DIRAM_END) // 0x4ffc0000 - 0x4ffbafc0 = 0x65040 / 0x45040 / 0x5040
+#define SOC_DRAM_USABLE_LOW     (SOC_DRAM_LOW + CONFIG_CACHE_L2_CACHE_SIZE)
+#define SOC_IRAM_USABLE_LOW     (SOC_IRAM_LOW + CONFIG_CACHE_L2_CACHE_SIZE)
+#endif

 #if CONFIG_ULP_COPROC_ENABLED
 #define APP_USABLE_LP_RAM_SIZE  0x8000 - LP_ROM_DRAM_SIZE
@@ -85,20 +96,23 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor

 const soc_memory_region_t soc_memory_regions[] = {
 #ifdef CONFIG_SPIRAM
-    { SOC_EXTRAM_LOW,       SOC_EXTRAM_SIZE,                        SOC_MEMORY_TYPE_SPIRAM, 0,                      false}, //PSRAM, if available
+    { SOC_EXTRAM_LOW,       SOC_EXTRAM_SIZE,                               SOC_MEMORY_TYPE_SPIRAM, 0,                      false}, //PSRAM, if available
 #endif
-    { SOC_DRAM_LOW,         APP_USABLE_DIRAM_END - SOC_DRAM_LOW,    SOC_MEMORY_TYPE_L2MEM,  SOC_IRAM_LOW,           false},
-    { APP_USABLE_DIRAM_END, STARTUP_DATA_SIZE,                      SOC_MEMORY_TYPE_L2MEM,  APP_USABLE_DIRAM_END,   true},
+    { SOC_DRAM_USABLE_LOW,  APP_USABLE_DIRAM_END - SOC_DRAM_USABLE_LOW,    SOC_MEMORY_TYPE_L2MEM,  SOC_IRAM_USABLE_LOW,    false},
+    { APP_USABLE_DIRAM_END, STARTUP_DATA_SIZE,                             SOC_MEMORY_TYPE_L2MEM,  APP_USABLE_DIRAM_END,   true},
 #ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
-    { 0x50108000,           APP_USABLE_LP_RAM_SIZE,                 SOC_MEMORY_TYPE_RTCRAM, 0,                      false}, //LPRAM
+    { 0x50108000,           APP_USABLE_LP_RAM_SIZE,                        SOC_MEMORY_TYPE_RTCRAM, 0,                      false}, //LPRAM
 #endif
-    { 0x30100000,           0x2000,                                 SOC_MEMORY_TYPE_TCM,    0,                      false},
+    { 0x30100000,           0x2000,                                        SOC_MEMORY_TYPE_TCM,    0,                      false},
 };

 const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);

-
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 extern int _data_start_low, _data_start_high, _heap_start_low, _heap_start_high, _iram_start, _iram_end, _rtc_force_slow_end;
+#else
+extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end;
+#endif
 extern int _tcm_text_start, _tcm_data_end;
 extern int _rtc_reserved_start, _rtc_reserved_end;
 extern int _rtc_ulp_memory_start;
@@ -110,8 +124,12 @@ extern int _rtc_ulp_memory_start;
 */

 // Static data region. DRAM used by data+bss and possibly rodata
+#if CONFIG_ESP32P4_SELECTS_REV_LESS_V3
 SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start_low, (intptr_t)&_heap_start_low, dram_data_low);
 SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start_high, (intptr_t)&_heap_start_high, dram_data_high);
+#else
+SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_data_high)
+#endif

 // Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips
 SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
@@ -75,7 +75,7 @@ static void s_prepare_reserved_regions(soc_reserved_region_t *reserved, size_t c
    /* Get the ROM layout to find which part of DRAM is reserved */
    const ets_rom_layout_t *layout = ets_rom_layout_p;
    reserved[0].start = (intptr_t)layout->dram0_rtos_reserved_start;
-#ifdef SOC_DIRAM_ROM_RESERVE_HIGH
+#if SOC_DIRAM_ROM_RESERVE_HIGH && CONFIG_ESP32P4_SELECTS_REV_LESS_V3
    reserved[0].end = SOC_DIRAM_ROM_RESERVE_HIGH;
 #else
    reserved[0].end = SOC_DIRAM_DRAM_HIGH;
@@ -46,7 +46,7 @@ extern "C" {
 #define MTVT_CSR    0x307


-#if CONFIG_IDF_TARGET_ESP32P4
+#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_SELECTS_REV_LESS_V3

 /**
 * The ESP32-P4 and the beta version of the ESP32-C5 implement a non-standard version of the CLIC:
@@ -56,9 +56,9 @@ extern "C" {
 #define INTTHRESH_STANDARD  0
 #define MINTSTATUS_CSR      0x346

-#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61
+#elif CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || !CONFIG_ESP32P4_SELECTS_REV_LESS_V3

-/* The ESP32-C5 (MP) and C61 use the standard CLIC specification, for example, it defines the mintthresh CSR */
+/* The ESP32-C5 (MP), C61 and P4 (since REV2) use the standard CLIC specification, for example, it defines the mintthresh CSR */
 #define INTTHRESH_STANDARD  1
 #define MINTSTATUS_CSR      0xFB1
 #define MINTTHRESH_CSR      0x347
@@ -20,7 +20,11 @@ endif()

 # register headers that generated by script from CSV
 if(CONFIG_IDF_TARGET_ESP32P4)
-    list(APPEND includes "${target_folder}/register/hw_ver1")
+    if(CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
+        list(APPEND includes "${target_folder}/register/hw_ver1")
+    else()
+        list(APPEND includes "${target_folder}/register/hw_ver3")
+    endif()
 else()
    if(EXISTS "${CMAKE_CURRENT_SOURCE_DIR}/${target_folder}/register")
        list(APPEND includes "${target_folder}/register")
@@ -2071,10 +2071,6 @@ config SOC_MEM_TCM_SUPPORTED
    bool
    default y

-config SOC_MEM_NON_CONTIGUOUS_SRAM
-    bool
-    default y
-
 config SOC_ASYNCHRONOUS_BUS_ERROR_MODE
    bool
    default y
@@ -773,7 +773,6 @@

 /*-------------------------- Memory CAPS --------------------------*/
 #define SOC_MEM_TCM_SUPPORTED                      (1)
-#define SOC_MEM_NON_CONTIGUOUS_SRAM                (1)
 #define SOC_ASYNCHRONOUS_BUS_ERROR_MODE            (1)
 /*--------------------------- EMAC --------------------------------*/
 #define SOC_EMAC_IEEE_1588_SUPPORT                 (1)      /*!< EMAC Supports IEEE1588 time stamping */
@@ -930,28 +930,3 @@ esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable)
    return ESP_OK;
 }
 #endif // CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32C2
-
-#if CONFIG_IDF_TARGET_ESP32P4
-//TODO: IDF-5670
-void IRAM_ATTR esp_config_l2_cache_mode(void)
-{
-    cache_size_t cache_size;
-    cache_line_size_t cache_line_size;
-#if CONFIG_CACHE_L2_CACHE_128KB
-    cache_size = CACHE_SIZE_128K;
-#elif CONFIG_CACHE_L2_CACHE_256KB
-    cache_size = CACHE_SIZE_256K;
-#else
-    cache_size = CACHE_SIZE_512K;
-#endif
-
-#if CONFIG_CACHE_L2_CACHE_LINE_64B
-    cache_line_size = CACHE_LINE_SIZE_64B;
-#else
-    cache_line_size = CACHE_LINE_SIZE_128B;
-#endif
-
-    Cache_Set_L2_Cache_Mode(cache_size, 8, cache_line_size);
-    Cache_Invalidate_All(CACHE_MAP_L2_CACHE);
-}
-#endif
@@ -156,6 +156,7 @@ components_not_formatted_permanent:
    - "/components/rt/"
    # SoC header files (generated)
    - "/components/soc/*/include/soc/"
+    - "/components/soc/*/register/hw_ver*/soc/"
    # Example resource files (generated)
    - "/examples/peripherals/lcd/i80_controller/main/images/"
    - "/examples/peripherals/dac/dac_continuous/dac_audio/main/audio_example_file.h"
@@ -18,4 +18,4 @@ tools/test_apps/build_system/embed_test:

 tools/test_apps/build_system/ld_non_contiguous_memory:
  disable:
-    - if: SOC_MEM_NON_CONTIGUOUS_SRAM != 1
+    - if: SOC_MEM_NON_CONTIGUOUS_SRAM != 1  # TODO: IDF-13411, since P4 REV2, the SRAM is contiguous
@@ -0,0 +1,3 @@
+CONFIG_IDF_TARGET="esp32p4"
+# To be replaced to P4 rev0/1
+CONFIG_ESP32P4_SELECTS_REV_LESS_V3=n