espressif/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-04-27 19:13:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

feat(efuse): Update efuse table for ESP32-H4

Browse Source
This commit is contained in:
Konstantin Kondrashov
2026-03-31 13:58:53 +03:00
parent 1c43172477
commit 8701705ec3
14 changed files with 1972 additions and 408 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/bootloader_support/src/bootloader_efuse.c
-1
View File
@@ -46,7 +46,6 @@ int bootloader_clock_get_rated_freq_mhz(void)
return 96;
#elif CONFIG_IDF_TARGET_ESP32H4
//TODO: [ESP32H4] IDF-12322 inherited from verification branch, need check
return 96;
#elif CONFIG_IDF_TARGET_ESP32P4
components/efuse/esp32h4/esp_efuse_table.c
+767 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -9,7 +9,7 @@
#include <assert.h>
#include "esp_efuse_table.h"
// md5_digest_table 00c61e1122b40bab1153117e162a713c
// md5_digest_table 4d334deda739743601735f09078a9fd5
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -79,6 +79,14 @@ static const esp_efuse_desc_t WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
{EFUSE_BLK0, 2, 1}, // [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT,
};
static const esp_efuse_desc_t WR_DIS_PVT_GLITCH_EN[] = {
{EFUSE_BLK0, 2, 1}, // [] wr_dis of PVT_GLITCH_EN,
};
static const esp_efuse_desc_t WR_DIS_PVT_GLITCH_MODE[] = {
{EFUSE_BLK0, 2, 1}, // [] wr_dis of PVT_GLITCH_MODE,
};
static const esp_efuse_desc_t WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
{EFUSE_BLK0, 4, 1}, // [] wr_dis of SPI_BOOT_CRYPT_CNT,
};
@@ -135,6 +143,10 @@ static const esp_efuse_desc_t WR_DIS_ECC_FORCE_CONST_TIME[] = {
{EFUSE_BLK0, 14, 1}, // [] wr_dis of ECC_FORCE_CONST_TIME,
};
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_SHA384_EN[] = {
{EFUSE_BLK0, 14, 1}, // [] wr_dis of SECURE_BOOT_SHA384_EN,
};
static const esp_efuse_desc_t WR_DIS_SECURE_BOOT_EN[] = {
{EFUSE_BLK0, 15, 1}, // [] wr_dis of SECURE_BOOT_EN,
};
@@ -231,10 +243,170 @@ static const esp_efuse_desc_t WR_DIS_FLASH_LDO_POWER_SEL[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_LDO_POWER_SEL,
};
static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MINOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MINOR,
};
static const esp_efuse_desc_t WR_DIS_WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of WAFER_VERSION_MAJOR,
};
static const esp_efuse_desc_t WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR,
};
static const esp_efuse_desc_t WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of DISABLE_BLK_VERSION_MAJOR,
};
static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MINOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MINOR,
};
static const esp_efuse_desc_t WR_DIS_BLK_VERSION_MAJOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of BLK_VERSION_MAJOR,
};
static const esp_efuse_desc_t WR_DIS_FLASH_CAP[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_CAP,
};
static const esp_efuse_desc_t WR_DIS_FLASH_VENDOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of FLASH_VENDOR,
};
static const esp_efuse_desc_t WR_DIS_PSRAM_CAP[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_CAP,
};
static const esp_efuse_desc_t WR_DIS_PSRAM_VENDOR[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PSRAM_VENDOR,
};
static const esp_efuse_desc_t WR_DIS_TEMP[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of TEMP,
};
static const esp_efuse_desc_t WR_DIS_PKG_VERSION[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PKG_VERSION,
};
static const esp_efuse_desc_t WR_DIS_PVT_DBIAS[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of PVT_DBIAS,
};
static const esp_efuse_desc_t WR_DIS_ADJUST_1V2[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of ADJUST_1V2,
};
static const esp_efuse_desc_t WR_DIS_ADJUST_1V8[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of ADJUST_1V8,
};
static const esp_efuse_desc_t WR_DIS_ACTIVE_DCDC_1V25[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_DCDC_1V25,
};
static const esp_efuse_desc_t WR_DIS_ACTIVE_DCDC_1V35[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of ACTIVE_DCDC_1V35,
};
static const esp_efuse_desc_t WR_DIS_SLP_DCDC[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of SLP_DCDC,
};
static const esp_efuse_desc_t WR_DIS_LSLP_HP_DRVB[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of LSLP_HP_DRVB,
};
static const esp_efuse_desc_t WR_DIS_DSLP_LP_DBIAS[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of DSLP_LP_DBIAS,
};
static const esp_efuse_desc_t WR_DIS_TEMP_CALIB[] = {
{EFUSE_BLK0, 20, 1}, // [] wr_dis of TEMP_CALIB,
};
static const esp_efuse_desc_t WR_DIS_SYS_DATA_PART1[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of BLOCK2,
};
static const esp_efuse_desc_t WR_DIS_OPTIONAL_UNIQUE_ID[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of OPTIONAL_UNIQUE_ID,
};
static const esp_efuse_desc_t WR_DIS_OCODE[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of OCODE,
};
static const esp_efuse_desc_t WR_DIS_DCDC_OCODE[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of DCDC_OCODE,
};
static const esp_efuse_desc_t WR_DIS_VDD_3V4_DOUT[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of VDD_3V4_DOUT,
};
static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0,
};
static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1,
};
static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2,
};
static const esp_efuse_desc_t WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3,
};
static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN0,
};
static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN1,
};
static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN2,
};
static const esp_efuse_desc_t WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_HI_DOUT_ATTEN3,
};
static const esp_efuse_desc_t WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF,
};
static const esp_efuse_desc_t WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF,
};
static const esp_efuse_desc_t WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF,
};
static const esp_efuse_desc_t WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF,
};
static const esp_efuse_desc_t WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF,
};
static const esp_efuse_desc_t WR_DIS_INITCODE_DIFF_1P8_3P3[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of INITCODE_DIFF_1P8_3P3,
};
static const esp_efuse_desc_t WR_DIS_HI_DOUT_DIFF_1P8_3P3[] = {
{EFUSE_BLK0, 21, 1}, // [] wr_dis of HI_DOUT_DIFF_1P8_3P3,
};
static const esp_efuse_desc_t WR_DIS_BLOCK_USR_DATA[] = {
{EFUSE_BLK0, 22, 1}, // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA,
};
@@ -275,6 +447,14 @@ static const esp_efuse_desc_t WR_DIS_USB_EXCHG_PINS[] = {
{EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_EXCHG_PINS,
};
static const esp_efuse_desc_t WR_DIS_USB_OTG_FS_EXCHG_PINS[] = {
{EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_OTG_FS_EXCHG_PINS,
};
static const esp_efuse_desc_t WR_DIS_USB_PHY_SEL[] = {
{EFUSE_BLK0, 30, 1}, // [] wr_dis of USB_PHY_SEL,
};
static const esp_efuse_desc_t WR_DIS_SOFT_DIS_JTAG[] = {
{EFUSE_BLK0, 31, 1}, // [] wr_dis of SOFT_DIS_JTAG,
};
@@ -569,6 +749,166 @@ static const esp_efuse_desc_t FLASH_LDO_POWER_SEL[] = {
{EFUSE_BLK1, 113, 1}, // [] Represents which flash ldo be select: 1: FLASH LDO 1P2 0 : FLASH LDO 1P8,
};
static const esp_efuse_desc_t WAFER_VERSION_MINOR[] = {
{EFUSE_BLK1, 114, 4}, // [] Minor chip version,
};
static const esp_efuse_desc_t WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK1, 118, 2}, // [] Major chip version,
};
static const esp_efuse_desc_t DISABLE_WAFER_VERSION_MAJOR[] = {
{EFUSE_BLK1, 120, 1}, // [] Disables check of wafer version major,
};
static const esp_efuse_desc_t DISABLE_BLK_VERSION_MAJOR[] = {
{EFUSE_BLK1, 121, 1}, // [] Disables check of blk version major,
};
static const esp_efuse_desc_t BLK_VERSION_MINOR[] = {
{EFUSE_BLK1, 122, 3}, // [] BLK_VERSION_MINOR of BLOCK2,
};
static const esp_efuse_desc_t BLK_VERSION_MAJOR[] = {
{EFUSE_BLK1, 125, 2}, // [] BLK_VERSION_MAJOR of BLOCK2,
};
static const esp_efuse_desc_t FLASH_CAP[] = {
{EFUSE_BLK1, 127, 3}, // [] Flash capacity,
};
static const esp_efuse_desc_t FLASH_VENDOR[] = {
{EFUSE_BLK1, 130, 3}, // [] Flash vendor,
};
static const esp_efuse_desc_t PSRAM_CAP[] = {
{EFUSE_BLK1, 133, 3}, // [] Psram capacity,
};
static const esp_efuse_desc_t PSRAM_VENDOR[] = {
{EFUSE_BLK1, 136, 2}, // [] Psram vendor,
};
static const esp_efuse_desc_t TEMP[] = {
{EFUSE_BLK1, 138, 2}, // [] Temp (die embedded inside),
};
static const esp_efuse_desc_t PKG_VERSION[] = {
{EFUSE_BLK1, 140, 3}, // [] Package version,
};
static const esp_efuse_desc_t PVT_DBIAS[] = {
{EFUSE_BLK1, 143, 5}, // [] PVT DBIAS,
};
static const esp_efuse_desc_t ADJUST_1V2[] = {
{EFUSE_BLK1, 148, 4}, // [] SPI LDO adjust of 1.2v,
};
static const esp_efuse_desc_t ADJUST_1V8[] = {
{EFUSE_BLK1, 152, 4}, // [] SPI LDO adjust of 1.8v,
};
static const esp_efuse_desc_t ACTIVE_DCDC_1V25[] = {
{EFUSE_BLK1, 156, 4}, // [] DCDC-DCDC DBIAS of 1.25v,
};
static const esp_efuse_desc_t ACTIVE_DCDC_1V35[] = {
{EFUSE_BLK1, 160, 4}, // [] DCDC-DCDC DBIAS of 1.35v,
};
static const esp_efuse_desc_t SLP_DCDC[] = {
{EFUSE_BLK1, 164, 5}, // [] DCDC DBIAS in sleep,
};
static const esp_efuse_desc_t LSLP_HP_DRVB[] = {
{EFUSE_BLK1, 169, 5}, // [] HP DRVB in light sleep,
};
static const esp_efuse_desc_t DSLP_LP_DBIAS[] = {
{EFUSE_BLK1, 174, 2}, // [] LP DBIAS in deep sleep,
};
static const esp_efuse_desc_t TEMP_CALIB[] = {
{EFUSE_BLK1, 176, 10}, // [] Temperature calibration data,
};
static const esp_efuse_desc_t OPTIONAL_UNIQUE_ID[] = {
{EFUSE_BLK2, 0, 128}, // [] Optional unique 128-bit ID,
};
static const esp_efuse_desc_t OCODE[] = {
{EFUSE_BLK2, 128, 8}, // [] ADC OCode,
};
static const esp_efuse_desc_t DCDC_OCODE[] = {
{EFUSE_BLK2, 136, 8}, // [] DCDC OCode,
};
static const esp_efuse_desc_t VDD_3V4_DOUT[] = {
{EFUSE_BLK2, 144, 10}, // [] ADC dout of vdd 3.4v,
};
static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN0[] = {
{EFUSE_BLK2, 154, 9}, // [] Average initcode of ADC1 atten0,
};
static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN1[] = {
{EFUSE_BLK2, 163, 9}, // [] Average initcode of ADC1 atten1,
};
static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN2[] = {
{EFUSE_BLK2, 172, 9}, // [] Average initcode of ADC1 atten2,
};
static const esp_efuse_desc_t ADC1_AVE_INITCODE_ATTEN3[] = {
{EFUSE_BLK2, 181, 9}, // [] Average initcode of ADC1 atten3,
};
static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN0[] = {
{EFUSE_BLK2, 190, 9}, // [] HI dout of ADC1 atten0,
};
static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN1[] = {
{EFUSE_BLK2, 199, 9}, // [] HI dout of ADC1 atten1,
};
static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN2[] = {
{EFUSE_BLK2, 208, 9}, // [] HI dout of ADC1 atten2,
};
static const esp_efuse_desc_t ADC1_HI_DOUT_ATTEN3[] = {
{EFUSE_BLK2, 217, 9}, // [] HI dout of ADC1 atten3,
};
static const esp_efuse_desc_t ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK2, 226, 3}, // [] Gap between ADC1 CH0 and average initcode,
};
static const esp_efuse_desc_t ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK2, 229, 3}, // [] Gap between ADC1 CH1 and average initcode,
};
static const esp_efuse_desc_t ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK2, 232, 3}, // [] Gap between ADC1 CH2 and average initcode,
};
static const esp_efuse_desc_t ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK2, 235, 3}, // [] Gap between ADC1 CH3 and average initcode,
};
static const esp_efuse_desc_t ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
{EFUSE_BLK2, 238, 3}, // [] Gap between ADC1 CH4 and average initcode,
};
static const esp_efuse_desc_t INITCODE_DIFF_1P8_3P3[] = {
{EFUSE_BLK2, 241, 5}, // [] Initcode diff between IO LDO 1.8v and 3.3v,
};
static const esp_efuse_desc_t HI_DOUT_DIFF_1P8_3P3[] = {
{EFUSE_BLK2, 246, 5}, // [] HI dout diff between IO LDO 1.8v and 3.3v,
};
static const esp_efuse_desc_t USER_DATA[] = {
{EFUSE_BLK3, 0, 256}, // [BLOCK_USR_DATA] User data,
};
@@ -689,6 +1029,16 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_EN[] = {
&WR_DIS_PVT_GLITCH_EN[0], // [] wr_dis of PVT_GLITCH_EN
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_MODE[] = {
&WR_DIS_PVT_GLITCH_MODE[0], // [] wr_dis of PVT_GLITCH_MODE
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[] = {
&WR_DIS_SPI_BOOT_CRYPT_CNT[0], // [] wr_dis of SPI_BOOT_CRYPT_CNT
NULL
@@ -759,6 +1109,11 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_SHA384_EN[] = {
&WR_DIS_SECURE_BOOT_SHA384_EN[0], // [] wr_dis of SECURE_BOOT_SHA384_EN
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[] = {
&WR_DIS_SECURE_BOOT_EN[0], // [] wr_dis of SECURE_BOOT_EN
NULL
@@ -879,11 +1234,211 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_LDO_POWER_SEL[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[] = {
&WR_DIS_WAFER_VERSION_MINOR[0], // [] wr_dis of WAFER_VERSION_MINOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[] = {
&WR_DIS_WAFER_VERSION_MAJOR[0], // [] wr_dis of WAFER_VERSION_MAJOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[] = {
&WR_DIS_DISABLE_WAFER_VERSION_MAJOR[0], // [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[] = {
&WR_DIS_DISABLE_BLK_VERSION_MAJOR[0], // [] wr_dis of DISABLE_BLK_VERSION_MAJOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[] = {
&WR_DIS_BLK_VERSION_MINOR[0], // [] wr_dis of BLK_VERSION_MINOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[] = {
&WR_DIS_BLK_VERSION_MAJOR[0], // [] wr_dis of BLK_VERSION_MAJOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[] = {
&WR_DIS_FLASH_CAP[0], // [] wr_dis of FLASH_CAP
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[] = {
&WR_DIS_FLASH_VENDOR[0], // [] wr_dis of FLASH_VENDOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[] = {
&WR_DIS_PSRAM_CAP[0], // [] wr_dis of PSRAM_CAP
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[] = {
&WR_DIS_PSRAM_VENDOR[0], // [] wr_dis of PSRAM_VENDOR
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[] = {
&WR_DIS_TEMP[0], // [] wr_dis of TEMP
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[] = {
&WR_DIS_PKG_VERSION[0], // [] wr_dis of PKG_VERSION
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_DBIAS[] = {
&WR_DIS_PVT_DBIAS[0], // [] wr_dis of PVT_DBIAS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADJUST_1V2[] = {
&WR_DIS_ADJUST_1V2[0], // [] wr_dis of ADJUST_1V2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADJUST_1V8[] = {
&WR_DIS_ADJUST_1V8[0], // [] wr_dis of ADJUST_1V8
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_DCDC_1V25[] = {
&WR_DIS_ACTIVE_DCDC_1V25[0], // [] wr_dis of ACTIVE_DCDC_1V25
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_DCDC_1V35[] = {
&WR_DIS_ACTIVE_DCDC_1V35[0], // [] wr_dis of ACTIVE_DCDC_1V35
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SLP_DCDC[] = {
&WR_DIS_SLP_DCDC[0], // [] wr_dis of SLP_DCDC
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DRVB[] = {
&WR_DIS_LSLP_HP_DRVB[0], // [] wr_dis of LSLP_HP_DRVB
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[] = {
&WR_DIS_DSLP_LP_DBIAS[0], // [] wr_dis of DSLP_LP_DBIAS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[] = {
&WR_DIS_TEMP_CALIB[0], // [] wr_dis of TEMP_CALIB
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[] = {
&WR_DIS_SYS_DATA_PART1[0], // [] wr_dis of BLOCK2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[] = {
&WR_DIS_OPTIONAL_UNIQUE_ID[0], // [] wr_dis of OPTIONAL_UNIQUE_ID
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[] = {
&WR_DIS_OCODE[0], // [] wr_dis of OCODE
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DCDC_OCODE[] = {
&WR_DIS_DCDC_OCODE[0], // [] wr_dis of DCDC_OCODE
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_3V4_DOUT[] = {
&WR_DIS_VDD_3V4_DOUT[0], // [] wr_dis of VDD_3V4_DOUT
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[] = {
&WR_DIS_ADC1_AVE_INITCODE_ATTEN0[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[] = {
&WR_DIS_ADC1_AVE_INITCODE_ATTEN1[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[] = {
&WR_DIS_ADC1_AVE_INITCODE_ATTEN2[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[] = {
&WR_DIS_ADC1_AVE_INITCODE_ATTEN3[0], // [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[] = {
&WR_DIS_ADC1_HI_DOUT_ATTEN0[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN0
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[] = {
&WR_DIS_ADC1_HI_DOUT_ATTEN1[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN1
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[] = {
&WR_DIS_ADC1_HI_DOUT_ATTEN2[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[] = {
&WR_DIS_ADC1_HI_DOUT_ATTEN3[0], // [] wr_dis of ADC1_HI_DOUT_ATTEN3
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
&WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
&WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
&WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
&WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
&WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_INITCODE_DIFF_1P8_3P3[] = {
&WR_DIS_INITCODE_DIFF_1P8_3P3[0], // [] wr_dis of INITCODE_DIFF_1P8_3P3
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HI_DOUT_DIFF_1P8_3P3[] = {
&WR_DIS_HI_DOUT_DIFF_1P8_3P3[0], // [] wr_dis of HI_DOUT_DIFF_1P8_3P3
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[] = {
&WR_DIS_BLOCK_USR_DATA[0], // [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
NULL
@@ -934,6 +1489,16 @@ const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG_FS_EXCHG_PINS[] = {
&WR_DIS_USB_OTG_FS_EXCHG_PINS[0], // [] wr_dis of USB_OTG_FS_EXCHG_PINS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[] = {
&WR_DIS_USB_PHY_SEL[0], // [] wr_dis of USB_PHY_SEL
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[] = {
&WR_DIS_SOFT_DIS_JTAG[0], // [] wr_dis of SOFT_DIS_JTAG
NULL
@@ -1300,6 +1865,206 @@ const esp_efuse_desc_t* ESP_EFUSE_FLASH_LDO_POWER_SEL[] = {
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[] = {
&WAFER_VERSION_MINOR[0], // [] Minor chip version
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[] = {
&WAFER_VERSION_MAJOR[0], // [] Major chip version
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[] = {
&DISABLE_WAFER_VERSION_MAJOR[0], // [] Disables check of wafer version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[] = {
&DISABLE_BLK_VERSION_MAJOR[0], // [] Disables check of blk version major
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[] = {
&BLK_VERSION_MINOR[0], // [] BLK_VERSION_MINOR of BLOCK2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[] = {
&BLK_VERSION_MAJOR[0], // [] BLK_VERSION_MAJOR of BLOCK2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[] = {
&FLASH_CAP[0], // [] Flash capacity
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[] = {
&FLASH_VENDOR[0], // [] Flash vendor
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[] = {
&PSRAM_CAP[0], // [] Psram capacity
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[] = {
&PSRAM_VENDOR[0], // [] Psram vendor
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_TEMP[] = {
&TEMP[0], // [] Temp (die embedded inside)
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[] = {
&PKG_VERSION[0], // [] Package version
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_PVT_DBIAS[] = {
&PVT_DBIAS[0], // [] PVT DBIAS
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADJUST_1V2[] = {
&ADJUST_1V2[0], // [] SPI LDO adjust of 1.2v
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADJUST_1V8[] = {
&ADJUST_1V8[0], // [] SPI LDO adjust of 1.8v
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_DCDC_1V25[] = {
&ACTIVE_DCDC_1V25[0], // [] DCDC-DCDC DBIAS of 1.25v
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_DCDC_1V35[] = {
&ACTIVE_DCDC_1V35[0], // [] DCDC-DCDC DBIAS of 1.35v
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_SLP_DCDC[] = {
&SLP_DCDC[0], // [] DCDC DBIAS in sleep
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DRVB[] = {
&LSLP_HP_DRVB[0], // [] HP DRVB in light sleep
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[] = {
&DSLP_LP_DBIAS[0], // [] LP DBIAS in deep sleep
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[] = {
&TEMP_CALIB[0], // [] Temperature calibration data
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[] = {
&OPTIONAL_UNIQUE_ID[0], // [] Optional unique 128-bit ID
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_OCODE[] = {
&OCODE[0], // [] ADC OCode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_DCDC_OCODE[] = {
&DCDC_OCODE[0], // [] DCDC OCode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_VDD_3V4_DOUT[] = {
&VDD_3V4_DOUT[0], // [] ADC dout of vdd 3.4v
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[] = {
&ADC1_AVE_INITCODE_ATTEN0[0], // [] Average initcode of ADC1 atten0
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[] = {
&ADC1_AVE_INITCODE_ATTEN1[0], // [] Average initcode of ADC1 atten1
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[] = {
&ADC1_AVE_INITCODE_ATTEN2[0], // [] Average initcode of ADC1 atten2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[] = {
&ADC1_AVE_INITCODE_ATTEN3[0], // [] Average initcode of ADC1 atten3
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[] = {
&ADC1_HI_DOUT_ATTEN0[0], // [] HI dout of ADC1 atten0
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[] = {
&ADC1_HI_DOUT_ATTEN1[0], // [] HI dout of ADC1 atten1
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[] = {
&ADC1_HI_DOUT_ATTEN2[0], // [] HI dout of ADC1 atten2
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[] = {
&ADC1_HI_DOUT_ATTEN3[0], // [] HI dout of ADC1 atten3
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[] = {
&ADC1_CH0_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH0 and average initcode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[] = {
&ADC1_CH1_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH1 and average initcode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[] = {
&ADC1_CH2_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH2 and average initcode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[] = {
&ADC1_CH3_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH3 and average initcode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[] = {
&ADC1_CH4_ATTEN0_INITCODE_DIFF[0], // [] Gap between ADC1 CH4 and average initcode
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_INITCODE_DIFF_1P8_3P3[] = {
&INITCODE_DIFF_1P8_3P3[0], // [] Initcode diff between IO LDO 1.8v and 3.3v
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_HI_DOUT_DIFF_1P8_3P3[] = {
&HI_DOUT_DIFF_1P8_3P3[0], // [] HI dout diff between IO LDO 1.8v and 3.3v
NULL
};
const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[] = {
&USER_DATA[0], // [BLOCK_USR_DATA] User data
NULL
components/efuse/esp32h4/esp_efuse_table.csv
+86 -1
View File
@@ -9,7 +9,7 @@
# this will generate new source files, next rebuild all the sources.
# !!!!!!!!!!! #
# This file was generated by regtools.py based on the efuses.yaml file with the version: 7bc342bad0952907e1db21112d258c6b
# This file was generated by regtools.py based on the efuses.yaml file with the version: 6c3ca4b9e6c9ee71a1a0627fa77a905a
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
@@ -27,6 +27,8 @@ WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [] wr_dis
WR_DIS.JTAG_SEL_ENABLE, EFUSE_BLK0, 2, 1, [] wr_dis of JTAG_SEL_ENABLE
WR_DIS.DIS_PAD_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_PAD_JTAG
WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
WR_DIS.PVT_GLITCH_EN, EFUSE_BLK0, 2, 1, [] wr_dis of PVT_GLITCH_EN
WR_DIS.PVT_GLITCH_MODE, EFUSE_BLK0, 2, 1, [] wr_dis of PVT_GLITCH_MODE
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
@@ -41,6 +43,7 @@ WR_DIS.SEC_DPA_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis
WR_DIS.XTS_DPA_PSEUDO_LEVEL, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_PSEUDO_LEVEL
WR_DIS.XTS_DPA_CLK_ENABLE, EFUSE_BLK0, 14, 1, [] wr_dis of XTS_DPA_CLK_ENABLE
WR_DIS.ECC_FORCE_CONST_TIME, EFUSE_BLK0, 14, 1, [] wr_dis of ECC_FORCE_CONST_TIME
WR_DIS.SECURE_BOOT_SHA384_EN, EFUSE_BLK0, 14, 1, [] wr_dis of SECURE_BOOT_SHA384_EN
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
@@ -65,7 +68,47 @@ WR_DIS.HYS_EN_PAD, EFUSE_BLK0, 20, 1, [] wr_dis
WR_DIS.PVT_GLITCH_CHARGE_RESET, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_GLITCH_CHARGE_RESET
WR_DIS.VDD_SPI_LDO_ADJUST, EFUSE_BLK0, 20, 1, [] wr_dis of VDD_SPI_LDO_ADJUST
WR_DIS.FLASH_LDO_POWER_SEL, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_LDO_POWER_SEL
WR_DIS.WAFER_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR
WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR
WR_DIS.DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_WAFER_VERSION_MAJOR
WR_DIS.DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of DISABLE_BLK_VERSION_MAJOR
WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MINOR
WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR
WR_DIS.FLASH_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_CAP
WR_DIS.FLASH_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VENDOR
WR_DIS.PSRAM_CAP, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_CAP
WR_DIS.PSRAM_VENDOR, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VENDOR
WR_DIS.TEMP, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
WR_DIS.PVT_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of PVT_DBIAS
WR_DIS.ADJUST_1V2, EFUSE_BLK0, 20, 1, [] wr_dis of ADJUST_1V2
WR_DIS.ADJUST_1V8, EFUSE_BLK0, 20, 1, [] wr_dis of ADJUST_1V8
WR_DIS.ACTIVE_DCDC_1V25, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_DCDC_1V25
WR_DIS.ACTIVE_DCDC_1V35, EFUSE_BLK0, 20, 1, [] wr_dis of ACTIVE_DCDC_1V35
WR_DIS.SLP_DCDC, EFUSE_BLK0, 20, 1, [] wr_dis of SLP_DCDC
WR_DIS.LSLP_HP_DRVB, EFUSE_BLK0, 20, 1, [] wr_dis of LSLP_HP_DRVB
WR_DIS.DSLP_LP_DBIAS, EFUSE_BLK0, 20, 1, [] wr_dis of DSLP_LP_DBIAS
WR_DIS.TEMP_CALIB, EFUSE_BLK0, 20, 1, [] wr_dis of TEMP_CALIB
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
WR_DIS.OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of OCODE
WR_DIS.DCDC_OCODE, EFUSE_BLK0, 21, 1, [] wr_dis of DCDC_OCODE
WR_DIS.VDD_3V4_DOUT, EFUSE_BLK0, 21, 1, [] wr_dis of VDD_3V4_DOUT
WR_DIS.ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN0
WR_DIS.ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN1
WR_DIS.ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN2
WR_DIS.ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_AVE_INITCODE_ATTEN3
WR_DIS.ADC1_HI_DOUT_ATTEN0, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN0
WR_DIS.ADC1_HI_DOUT_ATTEN1, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN1
WR_DIS.ADC1_HI_DOUT_ATTEN2, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN2
WR_DIS.ADC1_HI_DOUT_ATTEN3, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_HI_DOUT_ATTEN3
WR_DIS.ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH0_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH1_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH2_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH3_ATTEN0_INITCODE_DIFF
WR_DIS.ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK0, 21, 1, [] wr_dis of ADC1_CH4_ATTEN0_INITCODE_DIFF
WR_DIS.INITCODE_DIFF_1P8_3P3, EFUSE_BLK0, 21, 1, [] wr_dis of INITCODE_DIFF_1P8_3P3
WR_DIS.HI_DOUT_DIFF_1P8_3P3, EFUSE_BLK0, 21, 1, [] wr_dis of HI_DOUT_DIFF_1P8_3P3
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
@@ -76,6 +119,8 @@ WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.K
WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS
WR_DIS.USB_OTG_FS_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_OTG_FS_EXCHG_PINS
WR_DIS.USB_PHY_SEL, EFUSE_BLK0, 30, 1, [] wr_dis of USB_PHY_SEL
WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 31, 1, [] wr_dis of SOFT_DIS_JTAG
RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10
RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
@@ -154,6 +199,46 @@ HYS_EN_PAD, EFUSE_BLK1, 102, 1, [] Repres
PVT_GLITCH_CHARGE_RESET, EFUSE_BLK1, 103, 1, [] Represents whether to trigger reset or charge pump when PVT power glitch happened.1:Trigger charge pump. 0:Trigger reset
VDD_SPI_LDO_ADJUST, EFUSE_BLK1, 105, 8, [] Represents configuration of FLASH LDO mode and voltage.
FLASH_LDO_POWER_SEL, EFUSE_BLK1, 113, 1, [] Represents which flash ldo be select: 1: FLASH LDO 1P2 0 : FLASH LDO 1P8
WAFER_VERSION_MINOR, EFUSE_BLK1, 114, 4, [] Minor chip version
WAFER_VERSION_MAJOR, EFUSE_BLK1, 118, 2, [] Major chip version
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK1, 120, 1, [] Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK1, 121, 1, [] Disables check of blk version major
BLK_VERSION_MINOR, EFUSE_BLK1, 122, 3, [] BLK_VERSION_MINOR of BLOCK2
BLK_VERSION_MAJOR, EFUSE_BLK1, 125, 2, [] BLK_VERSION_MAJOR of BLOCK2
FLASH_CAP, EFUSE_BLK1, 127, 3, [] Flash capacity
FLASH_VENDOR, EFUSE_BLK1, 130, 3, [] Flash vendor
PSRAM_CAP, EFUSE_BLK1, 133, 3, [] Psram capacity
PSRAM_VENDOR, EFUSE_BLK1, 136, 2, [] Psram vendor
TEMP, EFUSE_BLK1, 138, 2, [] Temp (die embedded inside)
PKG_VERSION, EFUSE_BLK1, 140, 3, [] Package version
PVT_DBIAS, EFUSE_BLK1, 143, 5, [] PVT DBIAS
ADJUST_1V2, EFUSE_BLK1, 148, 4, [] SPI LDO adjust of 1.2v
ADJUST_1V8, EFUSE_BLK1, 152, 4, [] SPI LDO adjust of 1.8v
ACTIVE_DCDC_1V25, EFUSE_BLK1, 156, 4, [] DCDC-DCDC DBIAS of 1.25v
ACTIVE_DCDC_1V35, EFUSE_BLK1, 160, 4, [] DCDC-DCDC DBIAS of 1.35v
SLP_DCDC, EFUSE_BLK1, 164, 5, [] DCDC DBIAS in sleep
LSLP_HP_DRVB, EFUSE_BLK1, 169, 5, [] HP DRVB in light sleep
DSLP_LP_DBIAS, EFUSE_BLK1, 174, 2, [] LP DBIAS in deep sleep
TEMP_CALIB, EFUSE_BLK1, 176, 10, [] Temperature calibration data
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
OCODE, EFUSE_BLK2, 128, 8, [] ADC OCode
DCDC_OCODE, EFUSE_BLK2, 136, 8, [] DCDC OCode
VDD_3V4_DOUT, EFUSE_BLK2, 144, 10, [] ADC dout of vdd 3.4v
ADC1_AVE_INITCODE_ATTEN0, EFUSE_BLK2, 154, 9, [] Average initcode of ADC1 atten0
ADC1_AVE_INITCODE_ATTEN1, EFUSE_BLK2, 163, 9, [] Average initcode of ADC1 atten1
ADC1_AVE_INITCODE_ATTEN2, EFUSE_BLK2, 172, 9, [] Average initcode of ADC1 atten2
ADC1_AVE_INITCODE_ATTEN3, EFUSE_BLK2, 181, 9, [] Average initcode of ADC1 atten3
ADC1_HI_DOUT_ATTEN0, EFUSE_BLK2, 190, 9, [] HI dout of ADC1 atten0
ADC1_HI_DOUT_ATTEN1, EFUSE_BLK2, 199, 9, [] HI dout of ADC1 atten1
ADC1_HI_DOUT_ATTEN2, EFUSE_BLK2, 208, 9, [] HI dout of ADC1 atten2
ADC1_HI_DOUT_ATTEN3, EFUSE_BLK2, 217, 9, [] HI dout of ADC1 atten3
ADC1_CH0_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 226, 3, [] Gap between ADC1 CH0 and average initcode
ADC1_CH1_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 229, 3, [] Gap between ADC1 CH1 and average initcode
ADC1_CH2_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 232, 3, [] Gap between ADC1 CH2 and average initcode
ADC1_CH3_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 235, 3, [] Gap between ADC1 CH3 and average initcode
ADC1_CH4_ATTEN0_INITCODE_DIFF, EFUSE_BLK2, 238, 3, [] Gap between ADC1 CH4 and average initcode
INITCODE_DIFF_1P8_3P3, EFUSE_BLK2, 241, 5, [] Initcode diff between IO LDO 1.8v and 3.3v
HI_DOUT_DIFF_1P8_3P3, EFUSE_BLK2, 246, 5, [] HI dout diff between IO LDO 1.8v and 3.3v
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
Can't render this file because it contains an unexpected character in line 8 and column 53.
components/efuse/esp32h4/include/esp_efuse_chip.h
+13 -4
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -62,16 +62,25 @@ typedef enum {
*/
typedef enum {
ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (Expected in little endian order)*/
ESP_EFUSE_KEY_PURPOSE_RESERVED = 2, /**< Reserved (Used as a place holder)*/
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (P256) (Expected in little endian order)*/
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P256 = ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY, /**< ECDSA private key (P256) (Expected in little endian order)*/
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1 = 2, /**< Flash encryption key (XTS_AES_256_KEY_1) */
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_2 = 3, /**< Flash encryption key (XTS_AES_256_KEY_2) */
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4, /**< XTS_AES_128_KEY (flash/PSRAM encryption) */
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5, /**< HMAC Downstream mode */
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6, /**< JTAG soft enable key (uses HMAC Downstream mode) */
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Digital Signature peripheral key (uses HMAC Downstream mode) */
ESP_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, /**< Keep for compatibility although H4 has no DS peripheral */
ESP_EFUSE_KEY_PURPOSE_HMAC_UP = 8, /**< HMAC Upstream mode */
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9, /**< SECURE_BOOT_DIGEST0 (Secure Boot key digest) */
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10, /**< SECURE_BOOT_DIGEST1 (Secure Boot key digest) */
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */
ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY = 12, /**< KM_INIT_KEY */
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 = 13, /**< PSRAM encryption key (XTS_AES_256_KEY_1) */
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 = 14, /**< PSRAM encryption key (XTS_AES_256_KEY_2) */
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY = 15, /**< PSRAM encryption key (XTS_AES_128_KEY) */
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 = 16, /**< ECDSA private key (P192) */
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L = 17, /**< ECDSA private key (P384 low) */
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H = 18, /**< ECDSA private key (P384 high) */
ESP_EFUSE_KEY_PURPOSE_MAX = 32, /**< MAX PURPOSE */
} esp_efuse_purpose_t;
components/efuse/esp32h4/include/esp_efuse_table.h
+87 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,7 +10,7 @@ extern "C" {
#include "esp_efuse.h"
// md5_digest_table 00c61e1122b40bab1153117e162a713c
// md5_digest_table 4d334deda739743601735f09078a9fd5
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -33,6 +33,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_JTAG_SEL_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_PAD_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
@@ -53,6 +55,7 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SEC_DPA_LEVEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_PSEUDO_LEVEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_XTS_DPA_CLK_ENABLE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ECC_FORCE_CONST_TIME[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_SHA384_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
@@ -78,7 +81,47 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HYS_EN_PAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_GLITCH_CHARGE_RESET[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_LDO_ADJUST[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_LDO_POWER_SEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PVT_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADJUST_1V2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADJUST_1V8[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_DCDC_1V25[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ACTIVE_DCDC_1V35[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SLP_DCDC[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_LSLP_HP_DRVB[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DSLP_LP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OCODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DCDC_OCODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_3V4_DOUT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_AVE_INITCODE_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_HI_DOUT_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_INITCODE_DIFF_1P8_3P3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HI_DOUT_DIFF_1P8_3P3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
@@ -99,6 +142,8 @@ extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_OTG_FS_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_PHY_SEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
@@ -185,6 +230,46 @@ extern const esp_efuse_desc_t* ESP_EFUSE_HYS_EN_PAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_GLITCH_CHARGE_RESET[];
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_LDO_ADJUST[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_LDO_POWER_SEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_CAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VENDOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_PVT_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADJUST_1V2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADJUST_1V8[];
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_DCDC_1V25[];
extern const esp_efuse_desc_t* ESP_EFUSE_ACTIVE_DCDC_1V35[];
extern const esp_efuse_desc_t* ESP_EFUSE_SLP_DCDC[];
extern const esp_efuse_desc_t* ESP_EFUSE_LSLP_HP_DRVB[];
extern const esp_efuse_desc_t* ESP_EFUSE_DSLP_LP_DBIAS[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_OCODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DCDC_OCODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_3V4_DOUT[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_AVE_INITCODE_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN0[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN1[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN2[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_HI_DOUT_ATTEN3[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH0_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH1_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH2_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH3_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC1_CH4_ATTEN0_INITCODE_DIFF[];
extern const esp_efuse_desc_t* ESP_EFUSE_INITCODE_DIFF_1P8_3P3[];
extern const esp_efuse_desc_t* ESP_EFUSE_HI_DOUT_DIFF_1P8_3P3[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
components/efuse/test_apps/main/with_key_purposes/test_efuse_keys.c
+7 -4
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -189,8 +189,8 @@ TEST_CASE("Test esp_efuse_write_key for virt mode", "[efuse]")
purpose == ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY ||
#endif
purpose == ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY)) {
printf("BLOCK9 can not have the %d purpose, use RESERVED instead\n", purpose);
purpose = ESP_EFUSE_KEY_PURPOSE_RESERVED;
printf("BLOCK9 can not have the %d purpose, use ESP_EFUSE_KEY_PURPOSE_USER instead\n", purpose);
purpose = ESP_EFUSE_KEY_PURPOSE_USER;
}
#endif // SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK
int id = num_key - EFUSE_BLK_KEY0;
@@ -198,6 +198,9 @@ TEST_CASE("Test esp_efuse_write_key for virt mode", "[efuse]")
test_write_key(num_key, purpose);
TEST_ASSERT_EQUAL(id, esp_efuse_count_unused_key_blocks());
if (num_key == EFUSE_BLK9 && purpose == ESP_EFUSE_KEY_PURPOSE_USER) {
continue; // Skip checking purpose for BLOCK9 if it is set to PURPOSE_USER due to the quirk, since there may be other purpose set in this block before.
}
esp_efuse_block_t key_block = EFUSE_BLK_KEY_MAX;
TEST_ASSERT_TRUE(esp_efuse_find_purpose(purpose, &key_block));
TEST_ASSERT_EQUAL(num_key, key_block);
@@ -223,7 +226,7 @@ TEST_CASE("Test 1 esp_efuse_write_key for FPGA", "[efuse]")
#if SOC_EFUSE_ECDSA_KEY
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY,
#else
ESP_EFUSE_KEY_PURPOSE_RESERVED,
ESP_EFUSE_KEY_PURPOSE_USER,
#endif
#ifdef SOC_EFUSE_XTS_AES_KEY_256
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_1,
components/esp_rom/esp32h4/include/esp32h4/rom/efuse.h
+13 -6
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -11,8 +11,6 @@
extern "C" {
#endif
//TODO: [ESP32H4] IDF-12322 inherit from verification branch, need check
#include <stdint.h>
#include <stddef.h>
#include <stdbool.h>
@@ -29,15 +27,24 @@ extern "C" {
typedef enum {
ETS_EFUSE_KEY_PURPOSE_USER = 0,
ETS_EFUSE_KEY_PURPOSE_RESERVED = 1,
ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY = 4,
ETS_EFUSE_KEY_PURPOSE_ECDSA_KEY_P256 = 1,
ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_FLASH_1 = 2,
ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_FLASH_2 = 3,
ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY_FLASH = 4,
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_ALL = 5,
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_JTAG = 6,
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7,
ETS_EFUSE_KEY_PURPOSE_HMAC_DOWN_DIGITAL_SIGNATURE = 7, // no ds in h4, keep to make hmac compile pass
ETS_EFUSE_KEY_PURPOSE_HMAC_UP = 8,
ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST0 = 9,
ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST1 = 10,
ETS_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11,
ETS_EFUSE_KEY_PURPOSE_KM_INIT_KEY = 12,
ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_PSRAM_1 = 13,
ETS_EFUSE_KEY_PURPOSE_XTS_AES_256_KEY_PSRAM_2 = 14,
ETS_EFUSE_KEY_PURPOSE_XTS_AES_128_KEY_PSRAM = 15,
ETS_EFUSE_KEY_PURPOSE_ECDSA_KEY_P192 = 16,
ETS_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_L = 17,
ETS_EFUSE_KEY_PURPOSE_ECDSA_KEY_P384_H = 18,
ETS_EFUSE_KEY_PURPOSE_MAX,
} ets_efuse_purpose_t;
components/hal/esp32h4/efuse_hal.c
-2
View File
@@ -11,8 +11,6 @@
#include "hal/efuse_ll.h"
#include "esp_attr.h"
//TODO: [ESP32H4] IDF-12322 inherited from verification branch, need check
#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x08 << (4 * (block))))
#define ESP_EFUSE_BLOCK_ERROR_NUM_BITS(error_reg, block) ((error_reg) & (0x07 << (4 * (block))))
components/hal/esp32h4/include/hal/efuse_hal.h
-2
View File
@@ -12,8 +12,6 @@
#include "hal/efuse_ll.h"
#include_next "hal/efuse_hal.h"
//TODO: [ESP32H4] IDF-12322 inherited from verification branch, need check
#ifdef __cplusplus
extern "C" {
#endif
components/hal/esp32h4/include/hal/efuse_ll.h
+15 -24
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,8 +13,6 @@
#include "hal/assert.h"
#include "rom/efuse.h"
//TODO: [ESP32H4] IDF-12322 inherited from verification branch, need check
#ifdef __cplusplus
extern "C" {
#endif
@@ -51,50 +49,43 @@ __attribute__((always_inline)) static inline bool efuse_ll_get_secure_boot_v2_en
// use efuse_hal_get_major_chip_version() to get major chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_major(void)
{
//ESP32H4 TODO
return 0;
return EFUSE.rd_mac_sys3.wafer_version_major;
}
// use efuse_hal_get_minor_chip_version() to get minor chip version
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_wafer_version_minor(void)
{
//ESP32H4 TODO
return 0;
return EFUSE.rd_mac_sys3.wafer_version_minor;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_wafer_version_major(void)
{
//ESP32H4 TODO
return 0;
return EFUSE.rd_mac_sys3.disable_wafer_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_major(void)
{
//ESP32H4 TODO
return 0;
return EFUSE.rd_mac_sys3.blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_blk_version_minor(void)
{
//ESP32H4 TODO
return 0;
return EFUSE.rd_mac_sys3.blk_version_minor;
}
__attribute__((always_inline)) static inline bool efuse_ll_get_disable_blk_version_major(void)
{
//ESP32H4 TODO
return 0;
return EFUSE.rd_mac_sys3.disable_blk_version_major;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_chip_ver_pkg(void)
{
//ESP32H4 TODO
return 0;
return EFUSE.rd_mac_sys4.pkg_version;
}
__attribute__((always_inline)) static inline uint32_t efuse_ll_get_ecdsa_key_blk(void)
{
//ESP32H4 TODO
return 0;
return EFUSE.ecdsa.cur_ecdsa_p256_blk;
}
/******************* eFuse control functions *************************/
@@ -127,7 +118,7 @@ __attribute__((always_inline)) static inline void efuse_ll_set_conf_read_op_code
__attribute__((always_inline)) static inline int efuse_ll_get_ocode(void)
{
return 0;
return EFUSE.rd_sys_part1_data4.ocode;
}
__attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_code(void)
@@ -137,17 +128,17 @@ __attribute__((always_inline)) static inline void efuse_ll_set_conf_write_op_cod
__attribute__((always_inline)) static inline void efuse_ll_set_dac_num(uint8_t val)
{
//HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_num, val);
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_dac_clk_div(uint8_t val)
{
//HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_clk_div, val);
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.dac_conf, dac_clk_div, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_on_num(uint16_t val)
{
//HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf1, pwr_on_num, val);
HAL_FORCE_MODIFY_U32_REG_FIELD(EFUSE.wr_tim_conf1, pwr_on_num, val);
}
__attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint16_t value)
@@ -157,7 +148,7 @@ __attribute__((always_inline)) static inline void efuse_ll_set_pwr_off_num(uint1
__attribute__((always_inline)) static inline void efuse_ll_rs_bypass_update(void)
{
// EFUSE.wr_tim_conf0_rs_bypass.update = 1;
EFUSE.wr_tim_conf0_rs_bypass.update = 1;
}
/******************* eFuse control functions *************************/
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+9 -1
View File
@@ -845,12 +845,16 @@ config SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK
config SOC_EFUSE_ECDSA_KEY
bool
default n
default y
config SOC_EFUSE_XTS_AES_KEY_128
bool
default y
config SOC_EFUSE_XTS_AES_KEY_256
bool
default y
config SOC_SECURE_BOOT_V2_RSA
bool
default y
@@ -883,6 +887,10 @@ config SOC_FLASH_ENCRYPTION_XTS_AES_128
bool
default y
config SOC_FLASH_ENCRYPTION_XTS_AES_256
bool
default y
config SOC_APM_CTRL_FILTER_SUPPORTED
bool
default y
components/soc/esp32h4/include/soc/soc_caps.h
+5 -3
View File
@@ -54,8 +54,8 @@
#define SOC_USB_SERIAL_JTAG_SUPPORTED 1
// #define SOC_TEMP_SENSOR_SUPPORTED 1 // TODO: [ESP32H4] IDF-12404
// #define SOC_SUPPORTS_SECURE_DL_MODE 1
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1 // TODO: [ESP32H4] IDF-12268
#define SOC_EFUSE_SUPPORTED 1 // TODO: [ESP32H4] IDF-12268
#define SOC_EFUSE_KEY_PURPOSE_FIELD 1
#define SOC_EFUSE_SUPPORTED 1
// #define SOC_RTC_MEM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12313
#define SOC_I2S_SUPPORTED 1
#define SOC_RMT_SUPPORTED 1
@@ -413,8 +413,9 @@
#define SOC_EFUSE_SOFT_DIS_JTAG 0
#define SOC_EFUSE_DIS_ICACHE 0
#define SOC_EFUSE_BLOCK9_KEY_PURPOSE_QUIRK 1 // XTS-AES key purpose not supported for this block
#define SOC_EFUSE_ECDSA_KEY 0 // TODO: [ESP32H4] IDF-12259
#define SOC_EFUSE_ECDSA_KEY 1
#define SOC_EFUSE_XTS_AES_KEY_128 1
#define SOC_EFUSE_XTS_AES_KEY_256 1
/*-------------------------- Secure Boot CAPS----------------------------*/
#define SOC_SECURE_BOOT_V2_RSA 1
@@ -427,6 +428,7 @@
#define SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX (64)
#define SOC_FLASH_ENCRYPTION_XTS_AES 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_128 1
#define SOC_FLASH_ENCRYPTION_XTS_AES_256 1
/*-------------------------- APM CAPS ----------------------------------------*/
#define SOC_APM_CTRL_FILTER_SUPPORTED 1 /*!< Support for APM control filter */
components/soc/esp32h4/register/soc/efuse_reg.h
+485 -199
View File
File diff suppressed because it is too large Load Diff
components/soc/esp32h4/register/soc/efuse_struct.h
+485 -157
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0 OR MIT
*/
@@ -46,9 +46,7 @@ typedef union {
struct {
/** wr_dis : RO; bitpos: [31:0]; default: 0;
* Represents whether programming of individual eFuse memory bit is disabled or
* enabled.
* 1: Disabled
* 0: Enabled
* enabled.\\ 1: Disabled\\ 0: Enabled\\
*/
uint32_t wr_dis:32;
};
@@ -62,108 +60,95 @@ typedef union {
struct {
/** rd_dis : RO; bitpos: [6:0]; default: 0;
* Represents whether reading of individual eFuse block(block4~block10) is disabled or
* enabled.
* 1: disabled
* 0: enabled
* enabled.\\ 1: disabled\\ 0: enabled\\
*/
uint32_t rd_dis:7;
/** dis_usb_jtag : RO; bitpos: [7]; default: 0;
* Represents whether the function of usb switch to jtag is disabled or enabled.
* 1: disabled
* 0: enabled
* Represents whether the function of usb switch to jtag is disabled or enabled.\\ 1:
* disabled\\ 0: enabled\\
*/
uint32_t dis_usb_jtag:1;
/** dis_usb_serial_jtag : RO; bitpos: [8]; default: 0;
* Represents whether USB-Serial-JTAG is disabled or enabled.
* 1: disabled
* 0: enabled
*
* This field is only for internal debugging purposes. Do not use it in applications.
* Represents whether USB-Serial-JTAG is disabled or enabled.\\ 1: disabled\\ 0:
* enabled\\
*/
uint32_t dis_usb_serial_jtag:1;
/** dis_force_download : RO; bitpos: [9]; default: 0;
* Represents whether the function that forces chip into download mode is disabled or
* enabled.
* 1: disabled
* 0: enabled
* enabled.\\ 1: disabled\\ 0: enabled\\
*/
uint32_t dis_force_download:1;
/** spi_download_mspi_dis : RO; bitpos: [10]; default: 0;
* Represents whether SPI0 controller during boot_mode_download is disabled or enabled.
* 1: disabled
* 0: enabled
* Represents whether SPI0 controller during boot_mode_download is disabled or
* enabled.\\ 1: disabled\\ 0: enabled\\
*/
uint32_t spi_download_mspi_dis:1;
/** dis_twai : RO; bitpos: [11]; default: 0;
* Represents whether TWAI function is disabled or enabled.
* 1: disabled
* 0: enabled
* Represents whether TWAI function is disabled or enabled.\\ 1: disabled\\ 0:
* enabled\\
*/
uint32_t dis_twai:1;
/** jtag_sel_enable : RO; bitpos: [12]; default: 0;
* Represents whether the selection between usb_to_jtag and pad_to_jtag through
* strapping gpio15 when both EFUSE_DIS_PAD_JTAG and EFUSE_DIS_USB_JTAG are equal to 0
* is enabled or disabled.
* 1: enabled
* 0: disabled
* is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
*/
uint32_t jtag_sel_enable:1;
/** dis_pad_jtag : RO; bitpos: [13]; default: 0;
* Represents whether JTAG is disabled in the hard way(permanently).
* 1: disabled
* 0: enabled
* Represents whether JTAG is disabled in the hard way(permanently).\\ 1: disabled\\
* 0: enabled\\
*/
uint32_t dis_pad_jtag:1;
/** dis_download_manual_encrypt : RO; bitpos: [14]; default: 0;
* Represents whether flash encrypt function is disabled or enabled(except in SPI boot
* mode).
* 1: disabled
* 0: enabled
* mode).\\ 1: disabled\\ 0: enabled\\
*/
uint32_t dis_download_manual_encrypt:1;
uint32_t reserved_15:3;
/** rd_reserve_0_47 : RW; bitpos: [17:15]; default: 0;
* Reserved, it was created by set_missed_fields_in_regs func
*/
uint32_t rd_reserve_0_47:3;
/** pvt_glitch_en : RO; bitpos: [18]; default: 0;
* Represents whether to enable PVT power glitch monitor function.
* 1:Enable.
* 0:Disable
* Represents whether to enable PVT power glitch monitor function.\\1:Enable.
* \\0:Disable
*/
uint32_t pvt_glitch_en:1;
uint32_t reserved_19:1;
/** rd_reserve_0_51 : RW; bitpos: [19]; default: 0;
* Reserved, it was created by set_missed_fields_in_regs func
*/
uint32_t rd_reserve_0_51:1;
/** pvt_glitch_mode : RO; bitpos: [21:20]; default: 0;
* Use to configure glitch mode
*/
uint32_t pvt_glitch_mode:2;
/** dis_core1 : RO; bitpos: [22]; default: 0;
* Represents whether the CPU-Core1 is disabled.
* 1: Disabled.
* 0: Not disable.
* Represents whether the CPU-Core1 is disabled. \\ 1: Disabled. \\ 0: Not disable.
*/
uint32_t dis_core1:1;
/** spi_boot_crypt_cnt : RO; bitpos: [25:23]; default: 0;
* Represents whether SPI boot encrypt/decrypt is disabled or enabled.
* Odd number of 1: enabled
* Even number of 1: disabled
* Represents whether SPI boot encrypt/decrypt is disabled or enabled.\\ Odd number of
* 1: enabled\\ Even number of 1: disabled\\
*/
uint32_t spi_boot_crypt_cnt:3;
/** secure_boot_key_revoke0 : RO; bitpos: [26]; default: 0;
* Represents whether revoking first secure boot key is enabled or disabled.
* 1: enabled
* 0: disabled
* Represents whether revoking first secure boot key is enabled or disabled.\\ 1:
* enabled\\ 0: disabled\\
*/
uint32_t secure_boot_key_revoke0:1;
/** secure_boot_key_revoke1 : RO; bitpos: [27]; default: 0;
* Represents whether revoking second secure boot key is enabled or disabled.
* 1: enabled
* 0: disabled
* Represents whether revoking second secure boot key is enabled or disabled.\\ 1:
* enabled\\ 0: disabled\\
*/
uint32_t secure_boot_key_revoke1:1;
/** secure_boot_key_revoke2 : RO; bitpos: [28]; default: 0;
* Represents whether revoking third secure boot key is enabled or disabled.
* 1: enabled
* 0: disabled
* Represents whether revoking third secure boot key is enabled or disabled.\\ 1:
* enabled\\ 0: disabled\\
*/
uint32_t secure_boot_key_revoke2:1;
uint32_t reserved_29:3;
/** rd_reserve_0_61 : RW; bitpos: [31:29]; default: 0;
* Reserved, it was created by set_missed_fields_in_regs func
*/
uint32_t rd_reserve_0_61:3;
};
uint32_t val;
} efuse_rd_repeat_data0_reg_t;
@@ -211,22 +196,18 @@ typedef union {
typedef union {
struct {
/** xts_dpa_pseudo_level : RO; bitpos: [1:0]; default: 0;
* Represents the pseudo round level of xts-aes anti-dpa attack.
* 3: High.
* 2: Moderate 1. Low
* 0: Disabled
* Represents the pseudo round level of xts-aes anti-dpa attack.\\ 3: High.\\ 2:
* Moderate 1. Low\\ 0: Disabled\\
*/
uint32_t xts_dpa_pseudo_level:2;
/** xts_dpa_clk_enable : RO; bitpos: [2]; default: 0;
* Represents whether xts-aes anti-dpa attack clock is enabled.
* 1. Enable.
* 0: Disable.
* Represents whether xts-aes anti-dpa attack clock is enabled.\\ 1. Enable.\\ 0:
* Disable.\\
*/
uint32_t xts_dpa_clk_enable:1;
/** ecc_force_const_time : RO; bitpos: [3]; default: 0;
* Represents whether to force ecc to use const-time calculation mode.
* 1: Enable.
* 0: Disable.
* Represents whether to force ecc to use const-time calculation mode. \\ 1: Enable.
* \\ 0: Disable.
*/
uint32_t ecc_force_const_time:1;
/** secure_boot_sha384_en : RO; bitpos: [4]; default: 0;
@@ -234,15 +215,12 @@ typedef union {
*/
uint32_t secure_boot_sha384_en:1;
/** secure_boot_en : RO; bitpos: [5]; default: 0;
* Represents whether secure boot is enabled or disabled.
* 1: enabled
* 0: disabled
* Represents whether secure boot is enabled or disabled.\\ 1: enabled\\ 0: disabled\\
*/
uint32_t secure_boot_en:1;
/** secure_boot_aggressive_revoke : RO; bitpos: [6]; default: 0;
* Represents whether revoking aggressive secure boot is enabled or disabled.
* 1: enabled.
* 0: disabled
* Represents whether revoking aggressive secure boot is enabled or disabled.\\ 1:
* enabled.\\ 0: disabled\\
*/
uint32_t secure_boot_aggressive_revoke:1;
/** km_disable_deploy_mode : RO; bitpos: [11:7]; default: 0;
@@ -263,8 +241,8 @@ typedef union {
*/
uint32_t km_disable_deploy_mode:5;
/** km_rnd_switch_cycle : RO; bitpos: [13:12]; default: 0;
* Represents the cycle at which the Key Manager switches random numbers.
* 0: Controlled by the
* Represents the cycle at which the Key Manager switches random numbers.\\0:
* Controlled by the
* \hyperref[fielddesc:KEYMNGRNDSWITCHCYCLE]{KEYMNG\_RND\_SWITCH\_CYCLE} register. For
* more information, please refer to Chapter \ref{mod:keymng}
* \textit{\nameref{mod:keymng}}
@@ -331,11 +309,13 @@ typedef union {
* is 2 times the programmed value.
*/
uint32_t flash_tpuw:3;
uint32_t reserved_30:1;
/** rd_reserve_0_126 : RW; bitpos: [30]; default: 0;
* Reserved, it was created by set_missed_fields_in_regs func
*/
uint32_t rd_reserve_0_126:1;
/** dis_download_mode : RO; bitpos: [31]; default: 0;
* Represents whether Download mode is disabled or enabled.
* 1: disabled
* 0: enabled
* Represents whether Download mode is disabled or enabled.\\ 1: disabled\\ 0:
* enabled\\
*/
uint32_t dis_download_mode:1;
};
@@ -348,41 +328,34 @@ typedef union {
typedef union {
struct {
/** dis_direct_boot : RO; bitpos: [0]; default: 0;
* Represents whether direct boot mode is disabled or enabled.
* 1: disabled
* 0: enabled
* Represents whether direct boot mode is disabled or enabled.\\ 1: disabled\\ 0:
* enabled\\
*/
uint32_t dis_direct_boot:1;
/** dis_usb_serial_jtag_rom_print : RO; bitpos: [1]; default: 0;
* Represents whether print from USB-Serial-JTAG is disabled or enabled.
* 1: disabled
* 0: enabled
* Represents whether print from USB-Serial-JTAG is disabled or enabled.\\ 1:
* disabled\\ 0: enabled\\
*/
uint32_t dis_usb_serial_jtag_rom_print:1;
/** dis_usb_serial_jtag_download_mode : RO; bitpos: [2]; default: 0;
* Represents whether the USB-Serial-JTAG download function is disabled or enabled.
* 1: Disable
* 0: Enable
* Represents whether the USB-Serial-JTAG download function is disabled or enabled.\\
* 1: Disable\\ 0: Enable\\
*/
uint32_t dis_usb_serial_jtag_download_mode:1;
/** enable_security_download : RO; bitpos: [3]; default: 0;
* Represents whether security download is enabled or disabled.
* 1: enabled
* 0: disabled
* Represents whether security download is enabled or disabled.\\ 1: enabled\\ 0:
* disabled\\
*/
uint32_t enable_security_download:1;
/** uart_print_control : RO; bitpos: [5:4]; default: 0;
* Represents the type of UART printing.
* 00: force enable printing
* 01: enable printing when GPIO8 is reset at low level
* 10: enable printing when GPIO8 is reset at high level
* 11: force disable printing
* Represents the type of UART printing.\\ 00: force enable printing\\ 01: enable
* printing when GPIO8 is reset at low level\\ 10: enable printing when GPIO8 is reset
* at high level\\ 11: force disable printing\\
*/
uint32_t uart_print_control:2;
/** force_send_resume : RO; bitpos: [6]; default: 0;
* Represents whether ROM code is forced to send a resume command during SPI boot.
* 1: forced
* 0:not forced
* Represents whether ROM code is forced to send a resume command during SPI boot.\\
* 1: forced\\ 0:not forced\\
*/
uint32_t force_send_resume:1;
/** secure_version : RO; bitpos: [22:7]; default: 0;
@@ -390,17 +363,19 @@ typedef union {
*/
uint32_t secure_version:16;
/** huk_gen_state : RO; bitpos: [27:23]; default: 0;
* Represents whether the HUK generate mode is valid.
* Odd count of bits with a value of 1: Invalid
* Even count of bits with a value of 1: Valid
* Represents whether the HUK generate mode is valid.\\Odd count of bits with a value
* of 1: Invalid\\Even count of bits with a value of 1: Valid\\
*/
uint32_t huk_gen_state:5;
/** flash_ldo_efuse_sel : RO; bitpos: [28]; default: 0;
* Represents whether to select efuse control flash ldo default voltage.
* 1 : efuse 0 : strapping
* Represents whether to select efuse control flash ldo default voltage. \\ 1 : efuse
* 0 : strapping
*/
uint32_t flash_ldo_efuse_sel:1;
uint32_t reserved_29:3;
/** rd_reserve_0_157 : RW; bitpos: [31:29]; default: 0;
* Reserved, it was created by set_missed_fields_in_regs func
*/
uint32_t rd_reserve_0_157:3;
};
uint32_t val;
} efuse_rd_repeat_data3_reg_t;
@@ -413,66 +388,59 @@ typedef union {
/** usb_drefh : RO; bitpos: [1:0]; default: 0;
* Represents the single-end input threshold vrefh of USB_SERIAL_JTAG PHY, 1.76 V to 2
* V with step of 80 mV.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t usb_drefh:2;
/** usb_drefl : RO; bitpos: [3:2]; default: 0;
* Represents the single-end input threshold vrefl of USB_SERIAL_JTAG PHY, 1.76 V to 2
* V with step of 80 mV.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t usb_drefl:2;
/** usb_otg_fs_drefh : RO; bitpos: [5:4]; default: 0;
* Represents the single-end input threshold vrefh of USB_OTG_FS PHY, 1.76 V to 2 V
* with step of 80 mV.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t usb_otg_fs_drefh:2;
/** usb_otg_fs_drefl : RO; bitpos: [7:6]; default: 0;
* Represents the single-end input threshold vrefl of USB_OTG_FS PHY, 1.76 V to 2 V
* with step of 80 mV.
* This field is only for internal debugging purposes. Do not use it in applications.
*/
uint32_t usb_otg_fs_drefl:2;
/** usb_exchg_pins : RO; bitpos: [8]; default: 0;
* Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged.
* 1: exchanged
* 0: not exchanged
* Represents whether the D+ and D- pins of USB_SERIAL_JTAG PHY is exchanged.\\ 1:
* exchanged\\ 0: not exchanged\\
*/
uint32_t usb_exchg_pins:1;
/** usb_otg_fs_exchg_pins : RO; bitpos: [9]; default: 0;
* Represents whether the D+ and D- pins of USB_OTG_FS PHY is exchanged.
* 1: exchanged
* 0: not exchanged
* Represents whether the D+ and D- pins of USB_OTG_FS PHY is exchanged.\\ 1:
* exchanged\\ 0: not exchanged\\
*/
uint32_t usb_otg_fs_exchg_pins:1;
/** usb_phy_sel : RO; bitpos: [10]; default: 0;
* Represents whether to exchange the USB_SERIAL_JTAG PHY with USB_OTG_FS PHY.
* 1: exchanged.
* 0: not exchanged.
* Represents whether to exchange the USB_SERIAL_JTAG PHY with USB_OTG_FS PHY. \\ 1:
* exchanged. \\ 0: not exchanged.
*/
uint32_t usb_phy_sel:1;
/** soft_dis_jtag : RO; bitpos: [13:11]; default: 0;
* Represents whether JTAG is disabled in soft way.
* Odd number: disabled
* Even number: enabled
* Represents whether JTAG is disabled in soft way.\\ Odd number: disabled\\ Even
* number: enabled\\
*/
uint32_t soft_dis_jtag:3;
/** io_ldo_adjust : RO; bitpos: [21:14]; default: 0;
* Represents configuration of IO LDO mode and voltage.
* Represents configuration of IO LDO mode and voltage.\\
*/
uint32_t io_ldo_adjust:8;
/** io_ldo_1p8 : RO; bitpos: [22]; default: 0;
* Represents select IO LDO voltage to 1.8V or 3.3V.
* 1: 1.8V
* 0: 3.3V
* Represents select IO LDO voltage to 1.8V or 3.3V.\\ 1: 1.8V\\ 0: 3.3V\\
*/
uint32_t io_ldo_1p8:1;
/** dcdc_ccm_en : RO; bitpos: [23]; default: 0;
* Represents whether change DCDC to CCM mode
*/
uint32_t dcdc_ccm_en:1;
uint32_t reserved_24:8;
/** rd_reserve_0_184 : RW; bitpos: [31:24]; default: 0;
* Reserved, it was created by set_missed_fields_in_regs func
*/
uint32_t rd_reserve_0_184:8;
};
uint32_t val;
} efuse_rd_repeat_data4_reg_t;
@@ -526,7 +494,10 @@ typedef union {
* Use to configure voltage monitor limit for charge pump
*/
uint32_t pvt_pump_limit:8;
uint32_t reserved_31:1;
/** rd_reserve_1_95 : RW; bitpos: [31]; default: 0;
* Reserved, it was created by set_missed_fields_in_regs func
*/
uint32_t rd_reserve_1_95:1;
};
uint32_t val;
} efuse_rd_mac_sys2_reg_t;
@@ -549,32 +520,55 @@ typedef union {
*/
uint32_t wdt_delay_sel:2;
/** hys_en_pad : RO; bitpos: [6]; default: 0;
* Represents whether the hysteresis function of corresponding PAD is enabled.
* 1: enabled
* 0:disabled
* Represents whether the hysteresis function of corresponding PAD is enabled.\\ 1:
* enabled\\ 0:disabled\\
*/
uint32_t hys_en_pad:1;
/** pvt_glitch_charge_reset : RO; bitpos: [7]; default: 0;
* Represents whether to trigger reset or charge pump when PVT power glitch happened.
* 1:Trigger charge pump.
* 0:Trigger reset
* Represents whether to trigger reset or charge pump when PVT power glitch
* happened.\\1:Trigger charge pump. \\0:Trigger reset
*/
uint32_t pvt_glitch_charge_reset:1;
uint32_t reserved_8:1;
/** rd_reserve_1_104 : RW; bitpos: [8]; default: 0;
* Reserved, it was created by set_missed_fields_in_regs func
*/
uint32_t rd_reserve_1_104:1;
/** vdd_spi_ldo_adjust : RO; bitpos: [16:9]; default: 0;
* Represents configuration of FLASH LDO mode and voltage.
* Represents configuration of FLASH LDO mode and voltage.\\
*/
uint32_t vdd_spi_ldo_adjust:8;
/** flash_ldo_power_sel : RO; bitpos: [17]; default: 0;
* Represents which flash ldo be select:
* 1: FLASH LDO 1P2
* 0 : FLASH LDO 1P8
* Represents which flash ldo be select:\\ 1: FLASH LDO 1P2\\ 0 : FLASH LDO 1P8\\
*/
uint32_t flash_ldo_power_sel:1;
/** sys_data_part0_0 : RO; bitpos: [31:18]; default: 0;
* Represents the first 14-bit of zeroth part of system data.
/** wafer_version_minor : R; bitpos: [21:18]; default: 0;
* Minor chip version
*/
uint32_t sys_data_part0_0:14;
uint32_t wafer_version_minor:4;
/** wafer_version_major : R; bitpos: [23:22]; default: 0;
* Major chip version
*/
uint32_t wafer_version_major:2;
/** disable_wafer_version_major : R; bitpos: [24]; default: 0;
* Disables check of wafer version major
*/
uint32_t disable_wafer_version_major:1;
/** disable_blk_version_major : R; bitpos: [25]; default: 0;
* Disables check of blk version major
*/
uint32_t disable_blk_version_major:1;
/** blk_version_minor : R; bitpos: [28:26]; default: 0;
* BLK_VERSION_MINOR of BLOCK2
*/
uint32_t blk_version_minor:3;
/** blk_version_major : R; bitpos: [30:29]; default: 0;
* BLK_VERSION_MAJOR of BLOCK2
*/
uint32_t blk_version_major:2;
/** flash_cap : R; bitpos: [31]; default: 0;
* Flash capacity
*/
uint32_t flash_cap:1;
};
uint32_t val;
} efuse_rd_mac_sys3_reg_t;
@@ -584,10 +578,46 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part0_1 : RO; bitpos: [31:0]; default: 0;
* Represents the first 14-bit of zeroth part of system data.
/** flash_cap_1 : R; bitpos: [1:0]; default: 0;
* Flash capacity
*/
uint32_t sys_data_part0_1:32;
uint32_t flash_cap_1:2;
/** flash_vendor : R; bitpos: [4:2]; default: 0;
* Flash vendor
*/
uint32_t flash_vendor:3;
/** psram_cap : R; bitpos: [7:5]; default: 0;
* Psram capacity
*/
uint32_t psram_cap:3;
/** psram_vendor : R; bitpos: [9:8]; default: 0;
* Psram vendor
*/
uint32_t psram_vendor:2;
/** temp : R; bitpos: [11:10]; default: 0;
* Temp (die embedded inside)
*/
uint32_t temp:2;
/** pkg_version : R; bitpos: [14:12]; default: 0;
* Package version
*/
uint32_t pkg_version:3;
/** pvt_dbias : R; bitpos: [19:15]; default: 0;
* PVT DBIAS
*/
uint32_t pvt_dbias:5;
/** adjust_1v2 : R; bitpos: [23:20]; default: 0;
* SPI LDO adjust of 1.2v
*/
uint32_t adjust_1v2:4;
/** adjust_1v8 : R; bitpos: [27:24]; default: 0;
* SPI LDO adjust of 1.8v
*/
uint32_t adjust_1v8:4;
/** active_dcdc_1v25 : R; bitpos: [31:28]; default: 0;
* DCDC-DCDC DBIAS of 1.25v
*/
uint32_t active_dcdc_1v25:4;
};
uint32_t val;
} efuse_rd_mac_sys4_reg_t;
@@ -597,43 +627,326 @@ typedef union {
*/
typedef union {
struct {
/** sys_data_part0_2 : RO; bitpos: [31:0]; default: 0;
* Represents the second 32-bit of zeroth part of system data.
/** active_dcdc_1v35 : R; bitpos: [3:0]; default: 0;
* DCDC-DCDC DBIAS of 1.35v
*/
uint32_t sys_data_part0_2:32;
uint32_t active_dcdc_1v35:4;
/** slp_dcdc : R; bitpos: [8:4]; default: 0;
* DCDC DBIAS in sleep
*/
uint32_t slp_dcdc:5;
/** lslp_hp_drvb : R; bitpos: [13:9]; default: 0;
* HP DRVB in light sleep
*/
uint32_t lslp_hp_drvb:5;
/** dslp_lp_dbias : R; bitpos: [15:14]; default: 0;
* LP DBIAS in deep sleep
*/
uint32_t dslp_lp_dbias:2;
/** temp_calib : R; bitpos: [25:16]; default: 0;
* Temperature calibration data
*/
uint32_t temp_calib:10;
/** reserved_1_186 : R; bitpos: [31:26]; default: 0;
* reserved
*/
uint32_t reserved_1_186:6;
};
uint32_t val;
} efuse_rd_mac_sys5_reg_t;
/** Group: block2 registers */
/** Type of rd_sys_part1_datan register
* Represents rd_sys_part1_datan
/** Type of rd_sys_part1_data0 register
* Represents rd_sys_part1_data0
*/
typedef union {
struct {
/** sys_data_part1_n : RO; bitpos: [31:0]; default: 0;
* Represents the zeroth 32-bit of first part of system data.
/** optional_unique_id : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t sys_data_part1_n:32;
uint32_t optional_unique_id:32;
};
uint32_t val;
} efuse_rd_sys_part1_datan_reg_t;
} efuse_rd_sys_part1_data0_reg_t;
/** Type of rd_sys_part1_data1 register
* Represents rd_sys_part1_data1
*/
typedef union {
struct {
/** optional_unique_id_1 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t optional_unique_id_1:32;
};
uint32_t val;
} efuse_rd_sys_part1_data1_reg_t;
/** Type of rd_sys_part1_data2 register
* Represents rd_sys_part1_data2
*/
typedef union {
struct {
/** optional_unique_id_2 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t optional_unique_id_2:32;
};
uint32_t val;
} efuse_rd_sys_part1_data2_reg_t;
/** Type of rd_sys_part1_data3 register
* Represents rd_sys_part1_data3
*/
typedef union {
struct {
/** optional_unique_id_3 : R; bitpos: [31:0]; default: 0;
* Optional unique 128-bit ID
*/
uint32_t optional_unique_id_3:32;
};
uint32_t val;
} efuse_rd_sys_part1_data3_reg_t;
/** Type of rd_sys_part1_data4 register
* Represents rd_sys_part1_data4
*/
typedef union {
struct {
/** ocode : R; bitpos: [7:0]; default: 0;
* ADC OCode
*/
uint32_t ocode:8;
/** dcdc_ocode : R; bitpos: [15:8]; default: 0;
* DCDC OCode
*/
uint32_t dcdc_ocode:8;
/** vdd_3v4_dout : R; bitpos: [25:16]; default: 0;
* ADC dout of vdd 3.4v
*/
uint32_t vdd_3v4_dout:10;
/** adc1_ave_initcode_atten0 : R; bitpos: [31:26]; default: 0;
* Average initcode of ADC1 atten0
*/
uint32_t adc1_ave_initcode_atten0:6;
};
uint32_t val;
} efuse_rd_sys_part1_data4_reg_t;
/** Type of rd_sys_part1_data5 register
* Represents rd_sys_part1_data5
*/
typedef union {
struct {
/** adc1_ave_initcode_atten0_1 : R; bitpos: [2:0]; default: 0;
* Average initcode of ADC1 atten0
*/
uint32_t adc1_ave_initcode_atten0_1:3;
/** adc1_ave_initcode_atten1 : R; bitpos: [11:3]; default: 0;
* Average initcode of ADC1 atten1
*/
uint32_t adc1_ave_initcode_atten1:9;
/** adc1_ave_initcode_atten2 : R; bitpos: [20:12]; default: 0;
* Average initcode of ADC1 atten2
*/
uint32_t adc1_ave_initcode_atten2:9;
/** adc1_ave_initcode_atten3 : R; bitpos: [29:21]; default: 0;
* Average initcode of ADC1 atten3
*/
uint32_t adc1_ave_initcode_atten3:9;
/** adc1_hi_dout_atten0 : R; bitpos: [31:30]; default: 0;
* HI dout of ADC1 atten0
*/
uint32_t adc1_hi_dout_atten0:2;
};
uint32_t val;
} efuse_rd_sys_part1_data5_reg_t;
/** Type of rd_sys_part1_data6 register
* Represents rd_sys_part1_data6
*/
typedef union {
struct {
/** adc1_hi_dout_atten0_1 : R; bitpos: [6:0]; default: 0;
* HI dout of ADC1 atten0
*/
uint32_t adc1_hi_dout_atten0_1:7;
/** adc1_hi_dout_atten1 : R; bitpos: [15:7]; default: 0;
* HI dout of ADC1 atten1
*/
uint32_t adc1_hi_dout_atten1:9;
/** adc1_hi_dout_atten2 : R; bitpos: [24:16]; default: 0;
* HI dout of ADC1 atten2
*/
uint32_t adc1_hi_dout_atten2:9;
/** adc1_hi_dout_atten3 : R; bitpos: [31:25]; default: 0;
* HI dout of ADC1 atten3
*/
uint32_t adc1_hi_dout_atten3:7;
};
uint32_t val;
} efuse_rd_sys_part1_data6_reg_t;
/** Type of rd_sys_part1_data7 register
* Represents rd_sys_part1_data7
*/
typedef union {
struct {
/** adc1_hi_dout_atten3_1 : R; bitpos: [1:0]; default: 0;
* HI dout of ADC1 atten3
*/
uint32_t adc1_hi_dout_atten3_1:2;
/** adc1_ch0_atten0_initcode_diff : R; bitpos: [4:2]; default: 0;
* Gap between ADC1 CH0 and average initcode
*/
uint32_t adc1_ch0_atten0_initcode_diff:3;
/** adc1_ch1_atten0_initcode_diff : R; bitpos: [7:5]; default: 0;
* Gap between ADC1 CH1 and average initcode
*/
uint32_t adc1_ch1_atten0_initcode_diff:3;
/** adc1_ch2_atten0_initcode_diff : R; bitpos: [10:8]; default: 0;
* Gap between ADC1 CH2 and average initcode
*/
uint32_t adc1_ch2_atten0_initcode_diff:3;
/** adc1_ch3_atten0_initcode_diff : R; bitpos: [13:11]; default: 0;
* Gap between ADC1 CH3 and average initcode
*/
uint32_t adc1_ch3_atten0_initcode_diff:3;
/** adc1_ch4_atten0_initcode_diff : R; bitpos: [16:14]; default: 0;
* Gap between ADC1 CH4 and average initcode
*/
uint32_t adc1_ch4_atten0_initcode_diff:3;
/** initcode_diff_1p8_3p3 : R; bitpos: [21:17]; default: 0;
* Initcode diff between IO LDO 1.8v and 3.3v
*/
uint32_t initcode_diff_1p8_3p3:5;
/** hi_dout_diff_1p8_3p3 : R; bitpos: [26:22]; default: 0;
* HI dout diff between IO LDO 1.8v and 3.3v
*/
uint32_t hi_dout_diff_1p8_3p3:5;
/** reserved_2_251 : R; bitpos: [31:27]; default: 0;
* reserved
*/
uint32_t reserved_2_251:5;
};
uint32_t val;
} efuse_rd_sys_part1_data7_reg_t;
/** Group: block3 registers */
/** Type of rd_usr_datan register
* Represents rd_usr_datan
/** Type of rd_usr_data0 register
* Represents rd_usr_data0
*/
typedef union {
struct {
/** usr_datan : RO; bitpos: [31:0]; default: 0;
/** usr_data0 : RO; bitpos: [31:0]; default: 0;
* Represents the zeroth 32-bit of block3 (user).
*/
uint32_t usr_datan:32;
uint32_t usr_data0:32;
};
uint32_t val;
} efuse_rd_usr_datan_reg_t;
} efuse_rd_usr_data0_reg_t;
/** Type of rd_usr_data1 register
* Represents rd_usr_data1
*/
typedef union {
struct {
/** usr_data1 : RO; bitpos: [31:0]; default: 0;
* Represents the zeroth 32-bit of block3 (user).
*/
uint32_t usr_data1:32;
};
uint32_t val;
} efuse_rd_usr_data1_reg_t;
/** Type of rd_usr_data2 register
* Represents rd_usr_data2
*/
typedef union {
struct {
/** usr_data2 : RO; bitpos: [31:0]; default: 0;
* Represents the zeroth 32-bit of block3 (user).
*/
uint32_t usr_data2:32;
};
uint32_t val;
} efuse_rd_usr_data2_reg_t;
/** Type of rd_usr_data3 register
* Represents rd_usr_data3
*/
typedef union {
struct {
/** usr_data3 : RO; bitpos: [31:0]; default: 0;
* Represents the zeroth 32-bit of block3 (user).
*/
uint32_t usr_data3:32;
};
uint32_t val;
} efuse_rd_usr_data3_reg_t;
/** Type of rd_usr_data4 register
* Represents rd_usr_data4
*/
typedef union {
struct {
/** usr_data4 : RO; bitpos: [31:0]; default: 0;
* Represents the zeroth 32-bit of block3 (user).
*/
uint32_t usr_data4:32;
};
uint32_t val;
} efuse_rd_usr_data4_reg_t;
/** Type of rd_usr_data5 register
* Represents rd_usr_data5
*/
typedef union {
struct {
/** usr_data5 : RO; bitpos: [31:0]; default: 0;
* Represents the zeroth 32-bit of block3 (user).
*/
uint32_t usr_data5:32;
};
uint32_t val;
} efuse_rd_usr_data5_reg_t;
/** Type of rd_usr_data6 register
* Represents rd_usr_data6
*/
typedef union {
struct {
/** reserved_3_192 : R; bitpos: [7:0]; default: 0;
* reserved
*/
uint32_t reserved_3_192:8;
/** custom_mac : R; bitpos: [31:8]; default: 0;
* Custom MAC
*/
uint32_t custom_mac:24;
};
uint32_t val;
} efuse_rd_usr_data6_reg_t;
/** Type of rd_usr_data7 register
* Represents rd_usr_data7
*/
typedef union {
struct {
/** custom_mac_1 : R; bitpos: [23:0]; default: 0;
* Custom MAC
*/
uint32_t custom_mac_1:24;
/** reserved_3_248 : R; bitpos: [31:24]; default: 0;
* reserved
*/
uint32_t reserved_3_248:8;
};
uint32_t val;
} efuse_rd_usr_data7_reg_t;
/** Group: block4 registers */
@@ -741,6 +1054,7 @@ typedef union {
} efuse_rd_sys_part2_datan_reg_t;
/** Group: block0 error report registers */
/** Type of rd_repeat_data_err0 register
* Represents rd_repeat_data_err
@@ -3667,8 +3981,22 @@ typedef struct {
volatile efuse_rd_mac_sys3_reg_t rd_mac_sys3;
volatile efuse_rd_mac_sys4_reg_t rd_mac_sys4;
volatile efuse_rd_mac_sys5_reg_t rd_mac_sys5;
volatile efuse_rd_sys_part1_datan_reg_t rd_sys_part1_datan[8];
volatile efuse_rd_usr_datan_reg_t rd_usr_datan[8];
volatile efuse_rd_sys_part1_data0_reg_t rd_sys_part1_data0;
volatile efuse_rd_sys_part1_data1_reg_t rd_sys_part1_data1;
volatile efuse_rd_sys_part1_data2_reg_t rd_sys_part1_data2;
volatile efuse_rd_sys_part1_data3_reg_t rd_sys_part1_data3;
volatile efuse_rd_sys_part1_data4_reg_t rd_sys_part1_data4;
volatile efuse_rd_sys_part1_data5_reg_t rd_sys_part1_data5;
volatile efuse_rd_sys_part1_data6_reg_t rd_sys_part1_data6;
volatile efuse_rd_sys_part1_data7_reg_t rd_sys_part1_data7;
volatile efuse_rd_usr_data0_reg_t rd_usr_data0;
volatile efuse_rd_usr_data1_reg_t rd_usr_data1;
volatile efuse_rd_usr_data2_reg_t rd_usr_data2;
volatile efuse_rd_usr_data3_reg_t rd_usr_data3;
volatile efuse_rd_usr_data4_reg_t rd_usr_data4;
volatile efuse_rd_usr_data5_reg_t rd_usr_data5;
volatile efuse_rd_usr_data6_reg_t rd_usr_data6;
volatile efuse_rd_usr_data7_reg_t rd_usr_data7;
volatile efuse_rd_key0_datan_reg_t rd_key0_datan[8];
volatile efuse_rd_key1_datan_reg_t rd_key1_datan[8];
volatile efuse_rd_key2_datan_reg_t rd_key2_datan[8];