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feat(clk): support clk tree on h4mp

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This commit is contained in:
Chen Jichang
2025-12-04 10:59:29 +08:00
parent 7dfc2f0343
commit 8702d5c986
18 changed files with 268 additions and 179 deletions
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Kconfig
-2
View File
@@ -148,8 +148,6 @@ mainmenu "Espressif IoT Development Framework Configuration"
bool
default "y" if IDF_TARGET="esp32h4"
select IDF_TARGET_ARCH_RISCV
select IDF_ENV_BRINGUP
select IDF_ENV_FPGA if ESP32H4_SELECTS_REV_MP
config IDF_TARGET_ESP32S31
bool
components/bootloader/Kconfig.projbuild
+1 -2
View File
@@ -41,8 +41,7 @@ menu "Bootloader config"
config BOOTLOADER_CPU_CLK_FREQ_MHZ
int
default 64 if IDF_TARGET_ESP32H2
default 48 if IDF_TARGET_ESP32H21 || IDF_TARGET_ESP32H4
default 64 if IDF_TARGET_ESP32H2 || IDF_TARGET_ESP32H21 || IDF_TARGET_ESP32H4
default 90 if IDF_TARGET_ESP32P4 && ESP32P4_SELECTS_REV_LESS_V3
default 100 if IDF_TARGET_ESP32P4 && !ESP32P4_SELECTS_REV_LESS_V3
default 80
components/esp_hw_support/linker.lf
+4 -1
View File
@@ -45,8 +45,11 @@ entries:
pmu_init (noflash)
pmu_param (noflash)
elif PM_SLP_IRAM_OPT = y && IDF_TARGET_ESP32P4 != y:
pmu_param:get_act_hp_dbias (noflash)
pmu_param:get_act_lp_dbias (noflash)
if IDF_TARGET_ESP32H4 = y:
pmu_param:get_act_hp_drvb (noflash)
else:
pmu_param:get_act_hp_dbias (noflash)
if SOC_PMU_PVT_SUPPORTED = y:
pmu_pvt (noflash)
if PM_SLP_IRAM_OPT = y && SOC_USB_SERIAL_JTAG_SUPPORTED = y:
components/esp_hw_support/port/esp32h4/esp_clk_tree.c
+36 -36
View File
@@ -30,15 +30,15 @@ uint32_t *freq_value)
case SOC_MOD_CLK_XTAL:
clk_src_freq = clk_hal_xtal_get_freq_mhz() * MHZ;
break;
// case SOC_MOD_CLK_XTAL_X2_F32M:
// clk_src_freq = CLK_LL_PLL_32M_FREQ_MHZ * MHZ;
// break;
case SOC_MOD_CLK_XTAL_X2_F32M:
clk_src_freq = CLK_LL_PLL_32M_FREQ_MHZ * MHZ;
break;
case SOC_MOD_CLK_PLL_F48M:
clk_src_freq = CLK_LL_PLL_48M_FREQ_MHZ * MHZ;
break;
// case SOC_MOD_CLK_XTAL_X2_F64M:
// clk_src_freq = CLK_LL_PLL_64M_FREQ_MHZ * MHZ;
// break;
case SOC_MOD_CLK_XTAL_X2_F64M:
clk_src_freq = CLK_LL_PLL_64M_FREQ_MHZ * MHZ;
break;
case SOC_MOD_CLK_PLL_F96M:
clk_src_freq = CLK_LL_PLL_96M_FREQ_MHZ * MHZ;
break;
@@ -63,23 +63,23 @@ uint32_t *freq_value)
return ESP_OK;
}
// static int16_t s_xtal_x2_ref_cnt = 0;
static int16_t s_xtal_x2_ref_cnt = 0;
void esp_clk_tree_initialize(void)
{
// // TODO: IDF-14962
// // // In bootloader, flash clock source will always be switched to use XTAL_X2 clock
// // s_xtal_x2_ref_cnt++;
// if (clk_ll_cpu_get_src() == SOC_CPU_CLK_SRC_XTAL_X2) {
// s_xtal_x2_ref_cnt++;
// }
// TODO: IDF-14962
// // In bootloader, flash clock source will always be switched to use XTAL_X2 clock
// s_xtal_x2_ref_cnt++;
if (clk_ll_cpu_get_src() == SOC_CPU_CLK_SRC_XTAL_X2) {
s_xtal_x2_ref_cnt++;
}
}
bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit)
{
switch (clk_circuit) {
// case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
// return s_xtal_x2_ref_cnt > 0;
case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
return s_xtal_x2_ref_cnt > 0;
default:
break;
}
@@ -89,21 +89,21 @@ bool esp_clk_tree_is_power_on(soc_root_clk_circuit_t clk_circuit)
esp_err_t esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool enable)
{
switch (clk_circuit) {
// case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
// if (enable) {
// s_xtal_x2_ref_cnt++;
// } else {
// s_xtal_x2_ref_cnt--;
// }
case SOC_ROOT_CIRCUIT_CLK_XTAL_X2:
if (enable) {
s_xtal_x2_ref_cnt++;
} else {
s_xtal_x2_ref_cnt--;
}
// if (s_xtal_x2_ref_cnt == 1) {
// clk_ll_xtal_x2_enable();
// } else if (s_xtal_x2_ref_cnt == 0) {
// clk_ll_xtal_x2_disable();
// }
if (s_xtal_x2_ref_cnt == 1) {
clk_ll_xtal_x2_enable();
} else if (s_xtal_x2_ref_cnt == 0) {
clk_ll_xtal_x2_disable();
}
// assert(s_xtal_x2_ref_cnt >= 0);
// break;
assert(s_xtal_x2_ref_cnt >= 0);
break;
default:
break;
}
@@ -113,14 +113,14 @@ esp_err_t esp_clk_tree_enable_power(soc_root_clk_circuit_t clk_circuit, bool ena
esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
{
switch (clk_src) {
// case SOC_MOD_CLK_XTAL_X2_F32M:
// // later, here should handle ref count for XTAL_X2_F32M clock gating, then also handle XTAL_X2 circuit enable/disable
// esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable);
// break;
// case SOC_MOD_CLK_XTAL_X2_F64M:
// // later, here should handle ref count for XTAL_X2_F64M clock gating, then also handle XTAL_X2 circuit enable/disable
// esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable);
// break;
case SOC_MOD_CLK_XTAL_X2_F32M:
// later, here should handle ref count for XTAL_X2_F32M clock gating, then also handle XTAL_X2 circuit enable/disable
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable);
break;
case SOC_MOD_CLK_XTAL_X2_F64M:
// later, here should handle ref count for XTAL_X2_F64M clock gating, then also handle XTAL_X2 circuit enable/disable
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, enable);
break;
default:
break;
}
components/esp_hw_support/port/esp32h4/pmu_init.c
+26 -5
View File
@@ -15,6 +15,9 @@
#include "pmu_param.h"
#include "esp_private/esp_pmu.h"
#include "soc/regi2c_dcdc.h"
#include "soc/regi2c_ulp.h"
#include "soc/lp_aon_reg.h"
#include "soc/rtc.h"
#include "regi2c_ctrl.h"
#include "esp_rom_sys.h"
@@ -194,7 +197,7 @@ static inline void pmu_hp_system_param_default(pmu_hp_mode_t mode, pmu_hp_system
param->retent = pmu_hp_system_retention_param_default(mode);
if (mode == PMU_MODE_HP_ACTIVE || mode == PMU_MODE_HP_MODEM) {
param->analog->regulator0.dbias = get_act_hp_dbias();
param->analog->regulator1.drv_b = get_act_hp_drvb();
}
}
@@ -216,10 +219,6 @@ static inline void pmu_lp_system_param_default(pmu_lp_mode_t mode, pmu_lp_system
param->power = pmu_lp_system_power_param_default(mode);
*param->analog = *pmu_lp_system_analog_param_default(mode); //copy default value
if (mode == PMU_MODE_LP_ACTIVE) {
param->analog->regulator0.dbias = get_act_lp_dbias();
}
}
static void pmu_lp_system_init_default(pmu_context_t *ctx)
@@ -234,6 +233,20 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx)
}
}
uint32_t get_ulp_ocode()
{
uint32_t ulp_ocode = 0;
#if !CONFIG_IDF_ENV_FPGA
bool ulp_force_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE);
if (ulp_force_flag) {
ulp_ocode = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_EXT_CODE);
} else {
ulp_ocode = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_OCODE);
}
#endif
return ulp_ocode;
}
void pmu_init(void)
{
pmu_hp_system_init_default(PMU_instance());
@@ -259,4 +272,12 @@ void pmu_init(void)
// esp_ocode_calib_init();
// }
#endif
uint32_t ulp_ocode = get_ulp_ocode();
REG_SET_FIELD(PMU_BLE_BANDGAP_CTRL_REG, PMU_EXT_OCODE, ulp_ocode);
SET_PERI_REG_MASK(PMU_BLE_BANDGAP_CTRL_REG, PMU_EXT_FORCE_OCODE);
//For dcdc ldo mode when VDD is low than about a certion value, eg 2.6v
CLEAR_PERI_REG_MASK(LP_AON_DATE_REG, LP_AON_DREG_LDO_HW);
REG_SET_FIELD(LP_AON_DATE_REG, LP_AON_DREG_LDO_SW, 15);
}
components/esp_hw_support/port/esp32h4/pmu_param.c
+43 -21
View File
@@ -42,7 +42,7 @@ static __attribute__((unused)) const char *TAG = "pmu_param";
.xpd_bbpll = 1 \
}, \
.xtal = { \
.xpd_xtalx2 = 0, \
.xpd_xtalx2 = 1, \
.xpd_xtal = 1 \
} \
}
@@ -66,11 +66,19 @@ static __attribute__((unused)) const char *TAG = "pmu_param";
.xpd_bbpll = 1 \
}, \
.xtal = { \
.xpd_xtalx2 = 0, \
.xpd_xtalx2 = 1, \
.xpd_xtal = 1 \
} \
}
/*
flash_mode :
0: normal mode;
1: off mode
2: external mode;
3: standby mode
4: 4(through mode), only used when vdd low than 3v
*/
#define PMU_HP_SLEEP_POWER_CONFIG_DEFAULT() { \
.dig_power = { \
.vdd_flash_mode = 3, \
@@ -85,7 +93,7 @@ static __attribute__((unused)) const char *TAG = "pmu_param";
.clk_power = { \
.i2c_iso_en = 1, \
.i2c_retention = 1, \
.xpd_bb_i2c = 1, \
.xpd_bb_i2c = 0, \
.xpd_bbpll_i2c = 0, \
.xpd_bbpll = 0, \
}, \
@@ -211,7 +219,7 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
.dcdc_ccm_enb = 0, \
.dcdc_clear_rdy = 0, \
.dig_reg_dpcur_bias = 3, \
.dig_reg_dsfmos = 6, \
.dig_reg_dsfmos = 15, \
.dcm_mode = 3, \
.dcm_vset = 24, \
.xpd_trx = 1, \
@@ -231,10 +239,10 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
.xpd = 1, \
.slp_mem_dbias = 0, \
.slp_logic_dbias = 0, \
.dbias = HP_CALI_DBIAS_DEFAULT \
.dbias = 0 \
}, \
.regulator1 = { \
.drv_b = 2 \
.drv_b = HP_CALI_DRVB_DEFAULT \
} \
}
@@ -243,7 +251,7 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
.dcdc_ccm_enb = 0, \
.dcdc_clear_rdy = 0, \
.dig_reg_dpcur_bias = 1, \
.dig_reg_dsfmos = 4, \
.dig_reg_dsfmos = 15, \
.dcm_mode = 3, \
.dcm_vset = 24, \
.xpd_trx = 1, \
@@ -259,10 +267,10 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
.xpd = 1, \
.slp_mem_dbias = 0, \
.slp_logic_dbias = 0, \
.dbias = HP_CALI_DBIAS_DEFAULT \
.dbias = 0 \
}, \
.regulator1 = { \
.drv_b = 2 \
.drv_b = HP_CALI_DRVB_DEFAULT \
} \
}
@@ -273,7 +281,7 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
.dig_reg_dpcur_bias = 1, \
.dig_reg_dsfmos = 4, \
.dcm_mode = 3, \
.dcm_vset = 24, \
.dcm_vset = 20, \
.xpd_trx = 0, \
.xpd_bias = 0, \
.discnnt_dig_rtc = 0, \
@@ -290,7 +298,7 @@ const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp
.dbias = 0 \
}, \
.regulator1 = { \
.drv_b = 7 \
.drv_b = 25 \
} \
}
@@ -365,6 +373,14 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
# define PMU_SLOW_CLK_USE_EXT_XTAL (0)
#endif
/*
vdd_io_mode :
0: normal mode;
1: off mode
2: external mode;
3: standby mode
4: 4(through mode), only used when vdd low than 3v
*/
#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
.dig_power = { \
.vdd_io_mode = 0, \
@@ -382,9 +398,17 @@ const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pm
} \
}
/*
vdd_io_mode :
0: normal mode;
1: off mode
2: external mode;
3: standby mode
4: 4(through mode), only used when vdd low than 3v
*/
#define PMU_LP_SLEEP_POWER_CONFIG_DEFAULT() { \
.dig_power = { \
.vdd_io_mode = 3, \
.vdd_io_mode = 0, \
.bod_source_sel = 0, \
.vddbat_mode = 0, \
.mem_dslp = 0, \
@@ -421,7 +445,7 @@ const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mod
.dbias = LP_CALI_DBIAS_DEFAULT \
}, \
.regulator1 = { \
.drv_b = 2 \
.drv_b = 0 \
} \
}
@@ -432,7 +456,7 @@ const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mod
.dig_reg_dpcur_bias = 1, \
.dig_reg_dsfmos = 4, \
.dcm_mode = 3, \
.dcm_vset = 0, \
.dcm_vset = 20, \
.xpd_bias = 0, \
.discnnt_dig_rtc = 1, \
.pd_cur = 1, \
@@ -442,10 +466,10 @@ const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mod
.slp_xpd = 0, \
.xpd = 1, \
.slp_dbias = 0, \
.dbias = 0 \
.dbias = 3 \
}, \
.regulator1 = { \
.drv_b = 7 \
.drv_b = 0 \
} \
}
@@ -459,14 +483,12 @@ const pmu_lp_system_analog_param_t * pmu_lp_system_analog_param_default(pmu_lp_m
return &lp_analog[mode];
}
uint32_t get_act_hp_dbias(void)
uint32_t get_act_hp_drvb(void)
{
// TODO: IDF-12313
return HP_CALI_DBIAS_DEFAULT;
return HP_CALI_DRVB_DEFAULT;
}
uint32_t get_act_lp_dbias(void)
{
// TODO: IDF-12313
return LP_CALI_DBIAS_DEFAULT;
return LP_CALI_DBIAS_DEFAULT;
}
components/esp_hw_support/port/esp32h4/pmu_sleep.c
+2 -2
View File
@@ -152,7 +152,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_slp_lp_dbias();
if (!(sleep_flags & PMU_SLEEP_PD_XTAL)){
analog_default.hp_sys.analog.xpd_trx = PMU_XPD_TRX_SLEEP_ON;
analog_default.hp_sys.analog.dbias = get_act_hp_dbias();
analog_default.hp_sys.analog.dbias = get_act_hp_drvb();
analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
analog_default.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
@@ -160,7 +160,7 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
analog_default.lp_sys[LP(SLEEP)].analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_act_lp_dbias();
} else if (!(sleep_flags & PMU_SLEEP_PD_RC_FAST)) {
analog_default.hp_sys.analog.dbias = get_act_hp_dbias();
analog_default.hp_sys.analog.dbias = get_act_hp_drvb();
analog_default.lp_sys[LP(SLEEP)].analog.dbias = get_act_lp_dbias();
}
config->analog = analog_default;
components/esp_hw_support/port/esp32h4/private_include/pmu_param.h
+2 -2
View File
@@ -16,7 +16,7 @@
extern "C" {
#endif
#define HP_CALI_DBIAS_DEFAULT 0
#define HP_CALI_DRVB_DEFAULT 6
#define LP_CALI_DBIAS_DEFAULT 0
// FOR XTAL FORCE PU IN SLEEP
@@ -52,7 +52,7 @@ extern "C" {
#define PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT 12
#define PMU_LP_DBIAS_SLEEP_0V7_DEFAULT 23
uint32_t get_act_hp_dbias(void);
uint32_t get_act_hp_drvb(void);
uint32_t get_act_lp_dbias(void);
typedef struct {
components/esp_hw_support/port/esp32h4/rtc_clk.c
+46 -46
View File
@@ -206,22 +206,22 @@ static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
}
// /**
// * Switch to XTAL_X2 as cpu clock source.
// * On ESP32H4, XTAL_X2 frequency is 64MHz.
// * XTAL_X2 circuit must already been enabled.
// */
// static void rtc_clk_cpu_freq_to_xtal_x2(uint32_t cpu_freq_mhz, uint32_t cpu_divider)
// {
// // f_hp_root = 64MHz
// clk_ll_cpu_set_divider(cpu_divider);
// // Constraint: f_ahb <= 32MHz
// uint32_t ahb_divider = (cpu_divider == 1) ? 2 : 1;
// clk_ll_ahb_set_divider(ahb_divider);
// clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL_X2);
// clk_ll_bus_update();
// esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
// }
/**
* Switch to XTAL_X2 as cpu clock source.
* On ESP32H4, XTAL_X2 frequency is 64MHz.
* XTAL_X2 circuit must already been enabled.
*/
static void rtc_clk_cpu_freq_to_xtal_x2(uint32_t cpu_freq_mhz, uint32_t cpu_divider)
{
// f_hp_root = 64MHz
clk_ll_cpu_set_divider(cpu_divider);
// Constraint: f_ahb <= 32MHz
uint32_t ahb_divider = (cpu_divider == 1) ? 2 : 1;
clk_ll_ahb_set_divider(ahb_divider);
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL_X2);
clk_ll_bus_update();
esp_rom_set_cpu_ticks_per_us(cpu_freq_mhz);
}
bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
{
@@ -246,11 +246,11 @@ bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *ou
source = SOC_CPU_CLK_SRC_PLL;
source_freq_mhz = CLK_LL_PLL_96M_FREQ_MHZ;
divider = 1;
// } else if (freq_mhz == 64) {
// real_freq_mhz = freq_mhz;
// source = SOC_CPU_CLK_SRC_XTAL_X2;
// source_freq_mhz = CLK_LL_PLL_64M_FREQ_MHZ;
// divider = 1;
} else if (freq_mhz == 64) {
real_freq_mhz = freq_mhz;
source = SOC_CPU_CLK_SRC_XTAL_X2;
source_freq_mhz = CLK_LL_PLL_64M_FREQ_MHZ;
divider = 1;
} else if (freq_mhz == 48) {
real_freq_mhz = freq_mhz;
source = SOC_CPU_CLK_SRC_PLL;
@@ -278,12 +278,12 @@ static void rtc_clk_cpu_src_clk_enable(soc_cpu_clk_src_t new_src, uint32_t new_s
if (new_src == SOC_CPU_CLK_SRC_PLL) {
rtc_clk_bbpll_enable();
rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), new_src_freq_mhz);
// } else if (new_src == SOC_CPU_CLK_SRC_XTAL_X2) {
// #if BOOTLOADER_BUILD
// clk_ll_xtal_x2_enable();
// #else
// esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, true);
// #endif
} else if (new_src == SOC_CPU_CLK_SRC_XTAL_X2) {
#if BOOTLOADER_BUILD
clk_ll_xtal_x2_enable();
#else
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, true);
#endif
}
}
@@ -291,12 +291,12 @@ static void rtc_clk_cpu_src_clk_disable(soc_cpu_clk_src_t old_src)
{
if ((old_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) {
rtc_clk_bbpll_disable();
// } else if (old_src == SOC_CPU_CLK_SRC_XTAL_X2) {
// #if BOOTLOADER_BUILD
// clk_ll_xtal_x2_disable();
// #else
// esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, false);
// #endif
} else if (old_src == SOC_CPU_CLK_SRC_XTAL_X2) {
#if BOOTLOADER_BUILD
clk_ll_xtal_x2_disable();
#else
esp_clk_tree_enable_power(SOC_ROOT_CIRCUIT_CLK_XTAL_X2, false);
#endif
}
}
@@ -316,8 +316,8 @@ void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
rtc_clk_set_cpu_switch_to_bbpll(SLEEP_EVENT_HW_PLL_EN_STOP);
} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
rtc_clk_cpu_freq_to_rc_fast();
// } else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2) {
// rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div);
} else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2) {
rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div);
}
if (old_cpu_clk_src != config->source) {
@@ -341,9 +341,9 @@ void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
case SOC_CPU_CLK_SRC_RC_FAST:
source_freq_mhz = 8;
break;
// case SOC_CPU_CLK_SRC_XTAL_X2:
// source_freq_mhz = clk_ll_xtal_x2_get_freq_mhz();
// break;
case SOC_CPU_CLK_SRC_XTAL_X2:
source_freq_mhz = clk_ll_xtal_x2_get_freq_mhz();
break;
default:
ESP_HW_LOGE(TAG, "unsupported frequency configuration");
abort();
@@ -367,9 +367,9 @@ void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
rtc_clk_cpu_freq_to_rc_fast();
// } else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2
// && esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_XTAL_X2)) {
// rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div);
} else if (config->source == SOC_CPU_CLK_SRC_XTAL_X2
&& esp_clk_tree_is_power_on(SOC_ROOT_CIRCUIT_CLK_XTAL_X2)) {
rtc_clk_cpu_freq_to_xtal_x2(config->freq_mhz, config->div);
} else {
/* fallback */
rtc_clk_cpu_freq_set_config(config);
@@ -399,8 +399,8 @@ void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
{
if (cpu_freq_mhz == 96 || cpu_freq_mhz == 48) {
rtc_clk_cpu_freq_to_pll_mhz(cpu_freq_mhz);
// } else { // cpu_freq_mhz == 64
// rtc_clk_cpu_freq_to_xtal_x2(cpu_freq_mhz, 1);
} else { // cpu_freq_mhz == 64
rtc_clk_cpu_freq_to_xtal_x2(cpu_freq_mhz, 1);
}
clk_ll_cpu_clk_src_lock_release();
}
@@ -428,9 +428,9 @@ static uint32_t rtc_clk_ahb_freq_get(void)
case SOC_CPU_CLK_SRC_RC_FAST:
soc_root_freq_mhz = 8;
break;
// case SOC_CPU_CLK_SRC_XTAL_X2:
// soc_root_freq_mhz = clk_ll_xtal_x2_get_freq_mhz();
// break;
case SOC_CPU_CLK_SRC_XTAL_X2:
soc_root_freq_mhz = clk_ll_xtal_x2_get_freq_mhz();
break;
default:
// Unknown SOC_ROOT clock source
soc_root_freq_mhz = 0;
components/esp_hw_support/port/esp32h4/rtc_clk_init.c
+19 -2
View File
@@ -24,6 +24,7 @@
#include "hal/modem_lpcon_ll.h"
#endif
#include "pmu_param.h"
#include "soc/regi2c_dcdc.h"
ESP_HW_LOG_ATTR_TAG(TAG, "rtc_clk_init");
@@ -79,10 +80,26 @@ void rtc_clk_init(rtc_clk_config_t cfg)
REG_SET_FIELD(LP_CLKRST_FOSC_CNTL_REG, LP_CLKRST_FOSC_DFREQ, cfg.clk_8m_dfreq);
REG_SET_FIELD(LP_CLKRST_RC32K_CNTL_REG, LP_CLKRST_RC32K_DFREQ, cfg.slow_clk_dcap); // h4 specific workaround (RC32K_DFREQ is used for RC_SLOW clock tuning) TODO: IDF-12313
uint32_t hp_dbias = get_act_hp_dbias();
// switch to ccm mode
REG_SET_FIELD(PMU_DCM_CTRL_REG, PMU_DCDC_CCM_SW_EN, 1);
REG_SET_FIELD(PMU_HP_ACTIVE_BIAS_REG, PMU_HP_ACTIVE_DCDC_CCM_ENB, 0);
// dcdc init
REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_CCM_DREG0, 24);
REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_CCM_PCUR_LIMIT0, 4);
REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_VCM_DREG0, 24);
REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_VCM_PCUR_LIMIT0, 2);
REGI2C_WRITE_MASK(I2C_DCDC, I2C_DCDC_XPD_TRX, 0);
// close rf_pll
CLEAR_PERI_REG_MASK(PMU_DATE_REG, BIT(25)); //bit25 control rfpll
uint32_t hp_drvb = get_act_hp_drvb();
uint32_t lp_dbias = get_act_lp_dbias();
pmu_ll_hp_set_regulator_xpd(&PMU, PMU_MODE_HP_ACTIVE, true);
pmu_ll_hp_set_regulator_dbias(&PMU, PMU_MODE_HP_ACTIVE, hp_dbias);
pmu_ll_hp_set_regulator_driver_bar(&PMU, PMU_MODE_HP_ACTIVE, hp_drvb);
pmu_ll_lp_set_regulator_dbias(&PMU, PMU_MODE_LP_ACTIVE, lp_dbias);
// XTAL freq can be directly informed from register field PCR_CLK_XTAL_FREQ
components/esp_hw_support/test_apps/rtc_clk/main/test_rtc_clk.c
+6 -2
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -370,9 +370,13 @@ RTC_NOINIT_ATTR
#if CONFIG_IDF_TARGET_ESP32C2
#define TEMP_RTC_STORE_REG RTC_CNTL_DATE_REG
#define TEMP_RTC_STORE_REG_M RTC_CNTL_DATE_M
#elif CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H4
#elif CONFIG_IDF_TARGET_ESP32C61
#define TEMP_RTC_STORE_REG LP_AON_DATE_REG
#define TEMP_RTC_STORE_REG_M LP_AON_DATE_M
#elif CONFIG_IDF_TARGET_ESP32H4
#include "soc/pmu_reg.h"
#define TEMP_RTC_STORE_REG PMU_DATE_REG
#define TEMP_RTC_STORE_REG_M PMU_PMU_DATE_M
#endif
#endif
static int64_t start = 0;
components/esp_system/port/soc/esp32h4/Kconfig.cpu
+4 -4
View File
@@ -11,9 +11,9 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
config ESP_DEFAULT_CPU_FREQ_MHZ_48
bool "48 MHz"
depends on !IDF_ENV_FPGA
#config ESP_DEFAULT_CPU_FREQ_MHZ_64
# bool "64 MHz"
# depends on !IDF_ENV_FPGA
config ESP_DEFAULT_CPU_FREQ_MHZ_64
bool "64 MHz"
depends on !IDF_ENV_FPGA
config ESP_DEFAULT_CPU_FREQ_MHZ_96
bool "96 MHz"
depends on !IDF_ENV_FPGA
@@ -23,5 +23,5 @@ config ESP_DEFAULT_CPU_FREQ_MHZ
int
default 32 if ESP_DEFAULT_CPU_FREQ_MHZ_32
default 48 if ESP_DEFAULT_CPU_FREQ_MHZ_48
#default 64 if ESP_DEFAULT_CPU_FREQ_MHZ_64
default 64 if ESP_DEFAULT_CPU_FREQ_MHZ_64
default 96 if ESP_DEFAULT_CPU_FREQ_MHZ_96
components/hal/esp32h4/clk_tree_hal.c
+2 -2
View File
@@ -18,8 +18,8 @@ uint32_t clk_hal_soc_root_get_freq_mhz(soc_cpu_clk_src_t cpu_clk_src)
return clk_ll_bbpll_get_freq_mhz();
case SOC_CPU_CLK_SRC_RC_FAST:
return SOC_CLK_RC_FAST_FREQ_APPROX / MHZ;
// case SOC_CPU_CLK_SRC_XTAL_X2:
// return clk_ll_xtal_x2_get_freq_mhz();
case SOC_CPU_CLK_SRC_XTAL_X2:
return clk_ll_xtal_x2_get_freq_mhz();
default:
// Unknown CPU_CLK mux input
HAL_ASSERT(false);
components/hal/esp32h4/include/hal/clk_tree_ll.h
+36 -37
View File
@@ -26,9 +26,9 @@ extern "C" {
#define MHZ (1000000)
#define CLK_LL_PLL_8M_FREQ_MHZ (8)
// #define CLK_LL_PLL_32M_FREQ_MHZ (32)
#define CLK_LL_PLL_32M_FREQ_MHZ (32)
#define CLK_LL_PLL_48M_FREQ_MHZ (48)
// #define CLK_LL_PLL_64M_FREQ_MHZ (64)
#define CLK_LL_PLL_64M_FREQ_MHZ (64)
#define CLK_LL_PLL_96M_FREQ_MHZ (96)
#define CLK_LL_XTAL32K_CONFIG_DEFAULT() { \
@@ -62,8 +62,7 @@ typedef struct {
*/
static inline __attribute__((always_inline)) void clk_ll_bbpll_enable(void)
{
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_BB_I2C | PMU_TIE_HIGH_XPD_BBPLL | PMU_TIE_HIGH_XPD_BBPLL_I2C);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_BBPLL_ICG);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_BBPLL | PMU_TIE_HIGH_XPD_BBPLL_I2C);
}
/**
@@ -83,26 +82,26 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_clk_src_lock_releas
SET_PERI_REG_MASK(PMU_IMM_SLEEP_SYSCLK_REG, PMU_UPDATE_DIG_SYS_CLK_SEL);
}
// /**
// * @brief Power up XTAL_X2 circuit
// */
// static inline __attribute__((always_inline)) void clk_ll_xtal_x2_enable(void)
// {
// CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
// CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
// }
/**
* @brief Power up XTAL_X2 circuit
*/
static inline __attribute__((always_inline)) void clk_ll_xtal_x2_enable(void)
{
CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
}
// /**
// * @brief Power down XTAL_X2 circuit
// */
// static inline __attribute__((always_inline)) void clk_ll_xtal_x2_disable(void)
// {
// CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2 | PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
// SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
// }
/**
* @brief Power down XTAL_X2 circuit
*/
static inline __attribute__((always_inline)) void clk_ll_xtal_x2_disable(void)
{
CLEAR_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XTALX2 | PMU_TIE_HIGH_GLOBAL_XTALX2_ICG);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_XTALX2);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_XTALX2_ICG);
}
/**
* @brief Enable the 32kHz crystal oscillator
@@ -281,15 +280,15 @@ static inline __attribute__((always_inline)) void clk_ll_bbpll_set_config(uint32
REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, oc_dlref_sel);
}
// /**
// * @brief Get XTAL_X2_CLK frequency
// *
// * @return XTAL_X2 clock frequency, in MHz
// */
// static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_x2_get_freq_mhz(void)
// {
// return SOC_XTAL_FREQ_32M * 2;
// }
/**
* @brief Get XTAL_X2_CLK frequency
*
* @return XTAL_X2 clock frequency, in MHz
*/
static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_x2_get_freq_mhz(void)
{
return SOC_XTAL_FREQ_32M * 2;
}
/**
* @brief To enable the change of soc_clk_sel, cpu_div_num, ahb_div_num, apb_div_num
@@ -316,9 +315,9 @@ static inline __attribute__((always_inline)) void clk_ll_cpu_set_src(soc_cpu_clk
case SOC_CPU_CLK_SRC_RC_FAST:
PCR.sysclk_conf.soc_clk_sel = 1;
break;
// case SOC_CPU_CLK_SRC_XTAL_X2:
// PCR.sysclk_conf.soc_clk_sel = 2;
// break;
case SOC_CPU_CLK_SRC_XTAL_X2:
PCR.sysclk_conf.soc_clk_sel = 2;
break;
case SOC_CPU_CLK_SRC_PLL:
PCR.sysclk_conf.soc_clk_sel = 3;
break;
@@ -341,8 +340,8 @@ static inline __attribute__((always_inline)) soc_cpu_clk_src_t clk_ll_cpu_get_sr
return SOC_CPU_CLK_SRC_XTAL;
case 1:
return SOC_CPU_CLK_SRC_RC_FAST;
// case 2:
// return SOC_CPU_CLK_SRC_XTAL_X2;
case 2:
return SOC_CPU_CLK_SRC_XTAL_X2;
case 3:
return SOC_CPU_CLK_SRC_PLL;
default:
components/soc/esp32h4/include/soc/clk_tree_defs.h
+6 -6
View File
@@ -68,7 +68,7 @@ typedef enum {
*/
typedef enum {
SOC_ROOT_CIRCUIT_CLK_BBPLL, /*!< BBPLL_CLK is the output of the PLL generator circuit */
// SOC_ROOT_CIRCUIT_CLK_XTAL_X2, /*!< XTAL_X2_CLK is the output of the XTAL_X2 generator circuit */
SOC_ROOT_CIRCUIT_CLK_XTAL_X2, /*!< XTAL_X2_CLK is the output of the XTAL_X2 generator circuit */
} soc_root_clk_circuit_t;
/**
@@ -78,7 +78,7 @@ typedef enum {
typedef enum {
SOC_CPU_CLK_SRC_XTAL = 0, /*!< Select XTAL_CLK as CPU_CLK source */
SOC_CPU_CLK_SRC_RC_FAST = 1, /*!< Select RC_FAST_CLK as CPU_CLK source */
// SOC_CPU_CLK_SRC_XTAL_X2 = 2, /*!< Select XTAL_X2_CLK as CPU_CLK source (XTAL_X2_CLK is the other output of 32MHz crystal oscillator frequency multiplier, 64MHz) */
SOC_CPU_CLK_SRC_XTAL_X2 = 2, /*!< Select XTAL_X2_CLK as CPU_CLK source (XTAL_X2_CLK is the other output of 32MHz crystal oscillator frequency multiplier, 64MHz) */
SOC_CPU_CLK_SRC_PLL = 3, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 32MHz crystal oscillator frequency multiplier, 96MHz) */
SOC_CPU_CLK_SRC_INVALID, /*!< Invalid CPU_CLK source */
} soc_cpu_clk_src_t;
@@ -134,9 +134,9 @@ typedef enum {
SOC_MOD_CLK_RTC_FAST, /*!< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
SOC_MOD_CLK_RTC_SLOW, /*!< RTC_SLOW_CLK can be sourced from RC_SLOW_D4, XTAL32K, or OSC_SLOW by configuring soc_rtc_slow_clk_src_t */
// For digital domain: peripherals, BLE
// SOC_MOD_CLK_XTAL_X2_F32M, /*!< XTAL_X2_F32M_CLK is derived from XTAL_X2 (clock gating + fixed divider of 2), it has a fixed frequency of 32MHz */
SOC_MOD_CLK_XTAL_X2_F32M, /*!< XTAL_X2_F32M_CLK is derived from XTAL_X2 (clock gating + fixed divider of 2), it has a fixed frequency of 32MHz */
SOC_MOD_CLK_PLL_F48M, /*!< PLL_F48M_CLK is derived from PLL (clock gating + fixed divider of 2), it has a fixed frequency of 48MHz */
// SOC_MOD_CLK_XTAL_X2_F64M, /*!< XTAL_X2_F64M_CLK is derived from XTAL_X2 (clock gating), it has a fixed frequency of 64MHz */
SOC_MOD_CLK_XTAL_X2_F64M, /*!< XTAL_X2_F64M_CLK is derived from XTAL_X2 (clock gating), it has a fixed frequency of 64MHz */
SOC_MOD_CLK_PLL_F96M, /*!< PLL_F96M_CLK is derived from PLL (clock gating), it has a fixed frequency of 96MHz */
SOC_MOD_CLK_XTAL32K, /*!< XTAL32K_CLK comes from the external 32kHz crystal, passing a clock gating to the peripherals */
SOC_MOD_CLK_RC_FAST, /*!< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
@@ -285,7 +285,7 @@ typedef enum {
typedef enum {
FLASH_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
FLASH_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
// FLASH_CLK_SRC_REF_F64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
FLASH_CLK_SRC_REF_F64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
FLASH_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the source clock */
FLASH_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
FLASH_CLK_SRC_ROM_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as ROM default clock source */
@@ -428,7 +428,7 @@ typedef enum {
typedef enum {
I2S_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default source clock */
I2S_CLK_SRC_PLL_96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
// I2S_CLK_SRC_PLL_64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
I2S_CLK_SRC_PLL_64M = SOC_MOD_CLK_XTAL_X2_F64M, /*!< Select XTAL_X2_F64M as the source clock */
I2S_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
I2S_CLK_SRC_EXTERNAL = -1, /*!< Select external clock as source clock */
} soc_periph_i2s_clk_src_t;
components/soc/esp32h4/include/soc/regi2c_ulp.h
+8
View File
@@ -49,3 +49,11 @@
#define I2C_ULP_EXT_CODE 6
#define I2C_ULP_EXT_CODE_MSB 7
#define I2C_ULP_EXT_CODE_LSB 0
#define I2C_ULP_CPREG_DREG 8
#define I2C_ULP_CPREG_DREG_MSB 2
#define I2C_ULP_CPREG_DREG_LSB 0
#define I2C_ULP_CPREG_DREG1P1 8
#define I2C_ULP_CPREG_DREG1P1_MSB 4
#define I2C_ULP_CPREG_DREG1P1_LSB 3
components/soc/esp32h4/register/soc/lp_aon_reg.h
+16 -6
View File
@@ -669,13 +669,23 @@ extern "C" {
* reserved
*/
#define LP_AON_DATE_REG (DR_REG_LP_AON_BASE + 0x3fc)
/** LP_AON_DATE : R/W; bitpos: [30:0]; default: 38814352;
* version register
/** LP_AON_CLK_EN : R/W; bitpos: [5]; default: 0;
* 0: DREG_LDO control by SW;
* 1: DREG_LDO control by HW;
*/
#define LP_AON_DATE 0x7FFFFFFFU
#define LP_AON_DATE_M (LP_AON_DATE_V << LP_AON_DATE_S)
#define LP_AON_DATE_V 0x7FFFFFFFU
#define LP_AON_DATE_S 0
#define LP_AON_DREG_LDO_HW BIT(5)
#define LP_AON_DREG_LDO_HW_M (LP_AON_DREG_LDO_HW_V << LP_AON_DREG_LDO_HW_S)
#define LP_AON_DREG_LDO_HW_V 0x00000001U
#define LP_AON_DREG_LDO_HW_S 31
/** LP_AON_IO_LDO_ADJUST_SW : R/W; bitpos: [30:23]; default: 0;
* need_des
*/
#define LP_AON_DREG_LDO_SW 0x0000000FU
#define LP_AON_DREG_LDO_SW_M (LP_AON_DREG_LDO_SW_V << LP_AON_DREG_LDO_SW_S)
#define LP_AON_DREG_LDO_SW_V 0x0000000FU
#define LP_AON_DREG_LDO_SW_S 11
/** LP_AON_CLK_EN : R/W; bitpos: [31]; default: 0;
* version register
*/
components/soc/esp32h4/register/soc/lp_aon_struct.h
+11 -3
View File
@@ -602,10 +602,18 @@ typedef union {
*/
typedef union {
struct {
/** aon_date : R/W; bitpos: [30:0]; default: 38814352;
* version register
uint32_t reserved_0:5;
/** aon_dreg_ldo_hw : R/W; bitpos: [5]; default: 0;
* control the ldo of dreg by hw or sw
* 0: DREG_LDO control by SW;
* 1: DREG_LDO control by HW;
*/
uint32_t aon_date:31;
uint32_t aon_dreg_ldo_hw:1;
uint32_t reserved_6:17;
/** aon_dreg_ldo_sw : R/W; bitpos: [30:23]; default: 0;
* control the ldo of dreg by sw
*/
uint32_t aon_dreg_ldo_sw:8;
/** aon_clk_en : R/W; bitpos: [31]; default: 0;
* version register
*/