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Merge branch 'feature/esp32s31_clock_support' into 'master'

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feat(clk): support for esp32s31 clock tree

Closes IDF-14696 and IDF-14871

See merge request espressif/esp-idf!47048
This commit is contained in:
Song Ruo Jing
2026-04-03 11:04:42 +08:00
parent b533c6750e 50051b74a5
commit 8f0e59fadf
54 changed files with 1241 additions and 658 deletions
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docs/en/api-reference/peripherals/clk_tree.rst
+2 -2
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@@ -63,11 +63,11 @@ Root clocks generate reliable clock signals. These clock signals then pass throu
The clock source for this ``XTAL32K_CLK`` can be either a 32 kHz crystal connecting to the ``32K_XP`` and ``32K_XN`` pins or a 32 kHz clock signal generated by an external circuit. The external signal must be connected to the ``32K_XN`` pin. Additionally, a 1 nF capacitor must be placed between the ``32K_XP`` pin and ground. In this case, the ``32K_XP`` pin cannot be used as a GPIO pin.
.. only:: esp32p4
.. only:: esp32p4 or esp32s31
The clock source for this ``XTAL32K_CLK`` is a 32 kHz crystal connecting to the ``XTAL_32K_P`` and ``XTAL_32K_N`` pins.
.. only:: not esp32 and not esp32p4
.. only:: not esp32 and not esp32p4 and not esp32s31
The clock source for this ``XTAL32K_CLK`` can be either a 32 kHz crystal connecting to the ``XTAL_32K_P`` and ``XTAL_32K_N`` pins or a 32 kHz clock signal generated by an external circuit. The external signal must be connected to the ``XTAL_32K_P`` pin.
docs/zh_CN/api-reference/peripherals/clk_tree.rst
+2 -2
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@@ -63,11 +63,11 @@
``XTAL32K_CLK`` 的时钟源可以是连接到 ``32K_XP`` 和 ``32K_XN`` 管脚的 32 kHz 晶振，也可以是外部电路生成的 32 kHz 时钟信号。如果使用外部电路生成的时钟信号，该信号必须连接到 ``32K_XN`` 管脚，并且在 ``32K_XP`` 管脚和地之间连接一个 1 nF 的电容。此时，``32K_XP`` 管脚不能用作 GPIO 管脚。
.. only:: esp32p4
.. only:: esp32p4 or esp32s31
``XTAL32K_CLK`` 的时钟源是连接到 ``XTAL_32K_P`` 和 ``XTAL_32K_N`` 管脚的 32 kHz 晶振。
.. only:: not esp32 and not esp32p4
.. only:: not esp32 and not esp32p4 and not esp32s31
``XTAL32K_CLK`` 的时钟源可以是连接到 ``XTAL_32K_P`` 和 ``XTAL_32K_N`` 管脚的 32 kHz 晶振，也可以是外部电路生成的 32 kHZ 时钟信号。如果使用外部电路生成的时钟信号，该信号必须连接到 ``XTAL_32K_P`` 管脚。