fix(lp-core): fixed rtc mem conflict on p4 eco5 between app and ULP

components/esp_system/ld/esp32p4/memory.ld.in

@@ -32,12 +32,6 @@
 #define SRAM_HIGH_END      SRAM_HIGH_START + SRAM_HIGH_SIZE
 #endif
 
-#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
-#define MSPI_WORKAROUND_SIZE   CONFIG_P4_REV3_MSPI_WORKAROUND_SIZE
-#else
-#define MSPI_WORKAROUND_SIZE   0x0
-#endif
-
 #define IDROM_SEG_SIZE   (CONFIG_MMU_PAGE_SIZE << 10)
 
 #define LP_ROM_DRAM_START 0x5010fa80 // Value taken from ROM elf, includes LP ROM stack

components/esp_system/ld/ld.common

@@ -74,6 +74,12 @@
         #define RESERVE_RTC_MEM (ESP_BOOTLOADER_RESERVE_RTC + RTC_TIMER_RESERVE_RTC)
     #endif
 
+    #if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
+        #define MSPI_WORKAROUND_SIZE   CONFIG_P4_REV3_MSPI_WORKAROUND_SIZE
+    #else
+        #define MSPI_WORKAROUND_SIZE   0x0
+    #endif
+
 #endif // SOC_RTC_MEM_SUPPORTED
 
 #define QUOTED_STRING(STRING) #STRING

components/ulp/ld/lp_core_riscv.ld

@@ -9,11 +9,13 @@
 
 #if CONFIG_ESP_ROM_HAS_LP_ROM
 /* With LP-ROM memory layout is different due to LP ROM stack/data */
-#define ULP_MEM_START_ADDRESS SOC_RTC_DRAM_LOW + RESERVE_RTC_MEM
+/* For P4 ECO5 we also reserve some RTC MEM at the first for MSPI workaround */
+#define ULP_MEM_START_ADDRESS SOC_RTC_DRAM_LOW + RESERVE_RTC_MEM + MSPI_WORKAROUND_SIZE
 #else
 #define ULP_MEM_START_ADDRESS (SOC_RTC_DRAM_LOW)
 #endif
 
+
 #define ALIGN_DOWN(SIZE, AL)   (SIZE & ~(AL - 1))
 /* Ensure the end where the shared memory starts is aligned to 8 bytes
    if updating this also update the same in ulp_lp_core_memory_shared.c