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Merge branch 'fix/fix_p4_lp_adc_unavailable_in_sleep_v6.0' into 'release/v6.0'

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feat(esp_hw_support): support ESP_SLEEP_USE_ADC_TSEN_MONITOR_MODE for esp32p4 (v6.0)

See merge request espressif/esp-idf!45197
This commit is contained in:
Jiang Jiang Jian
2026-01-29 14:11:53 +08:00
parent 9d317f2cb8 a0e94d7f24
commit 9ed8ae514a
3 changed files with 12 additions and 9 deletions
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components/esp_hal_uart/esp32p4/include/hal/uart_ll.h
+2 -2
View File
@@ -101,7 +101,7 @@ FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *sou
switch (LPPERI.core_clk_sel.lp_uart_clk_sel) {
default:
case 0:
*source_clk = (soc_module_clk_t)LP_UART_SCLK_LP_FAST;
*source_clk = (soc_module_clk_t)LP_UART_SCLK_RC_FAST;
break;
case 1:
*source_clk = (soc_module_clk_t)LP_UART_SCLK_XTAL_D2;
@@ -123,7 +123,7 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_
{
(void)hw;
switch (src_clk) {
case LP_UART_SCLK_LP_FAST:
case LP_UART_SCLK_RC_FAST:
LPPERI.core_clk_sel.lp_uart_clk_sel = 0;
break;
case LP_UART_SCLK_XTAL_D2:
components/esp_hw_support/port/esp32p4/pmu_sleep.c
+6 -3
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -220,11 +220,14 @@ const pmu_sleep_config_t* pmu_sleep_config_default(
config->analog = analog_default;
}
if ((sleep_flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) || (sleep_flags & RTC_SLEEP_XTAL_AS_RTC_FAST)) {
config->analog.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
config->analog.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
}
if (sleep_flags & RTC_SLEEP_XTAL_AS_RTC_FAST) {
// Keep XTAL on in HP_SLEEP state if it is the clock source of RTC_FAST
power_default.hp_sys.xtal.xpd_xtal = 1;
config->analog.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
config->analog.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
config->analog.hp_sys.analog.dbg_atten = PMU_DBG_ATTEN_ACTIVE_DEFAULT;
config->analog.hp_sys.analog.dbias = HP_CALI_ACTIVE_DBIAS_DEFAULT;
}
components/soc/esp32p4/include/soc/clk_tree_defs.h
+4 -4
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -284,16 +284,16 @@ typedef enum {
/**
* @brief Array initializer for all supported clock sources of LP_UART
*/
#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2}
#define SOC_LP_UART_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_D2}
/**
* @brief Type of LP_UART clock source
*/
typedef enum {
LP_UART_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock is LP(RTC)_FAST */
LP_UART_SCLK_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< LP_UART source clock is FOSC */
LP_UART_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_UART source clock is XTAL_D2 */
// LP_UART_SCLK_LP_PLL = SOC_MOD_CLK_LP_PLL, /*!< LP_UART source clock is LP_PLL (8M PLL) */ TODO: IDF-9581
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_UART source clock default choice is LP(RTC)_FAST */
LP_UART_SCLK_DEFAULT = SOC_MOD_CLK_RC_FAST, /*!< LP_UART source clock default choice is FOSC */
} soc_periph_lp_uart_clk_src_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////