feat(cache): use icache memroy as diram when single core

components/bootloader_support/src/esp32h4/bootloader_esp32h4.c

@@ -108,7 +108,6 @@ static inline void bootloader_config_dcache(void)
 
 static inline void bootloader_config_icache1(void)
 {
-    // TODO: [ESP32H4] IDF-12289
 #if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
     REG_CLR_BIT(LP_AON_SRAM_USAGE_CONF_REG, LP_AON_ICACHE1_USAGE);
 #else

components/esp_rom/esp32h4/include/esp32h4/rom/cache.h

@@ -13,8 +13,6 @@
 extern "C" {
 #endif
 
-//TODO: [ESP32H4] IDF-12289 inherit from verification branch, need check
-
 /** \defgroup cache_apis, cache operation related apis
   * @brief cache apis
   */

components/esp_system/port/cpu_start.c

@@ -321,7 +321,7 @@ static void start_other_core(void)
     }
 }
 
-#if !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE && !CONFIG_IDF_TARGET_ESP32H4 // TODO IDF-12289
+#if !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
 #if CONFIG_IDF_TARGET_ESP32
 static void restore_app_mmu_from_pro_mmu(void)
 {
@@ -466,7 +466,7 @@ FORCE_INLINE_ATTR IRAM_ATTR void ram_app_init(void)
 //Keep this static, the compiler will check output parameters are initialized.
 FORCE_INLINE_ATTR IRAM_ATTR void ext_mem_init(void)
 {
-#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE && !CONFIG_IDF_TARGET_ESP32H4 // TODO IDF-12289
+#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE && !SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
     // It helps to fix missed cache settings for other cores. It happens when bootloader is unicore.
     do_multicore_settings();
 #endif

components/hal/esp32h4/include/hal/cache_ll.h

@@ -758,6 +758,35 @@ static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask
     REG_CLR_BIT(CACHE_L1_DCACHE_CTRL_REG, dbus_mask);
 }
 
+/**
+ * Returns enabled buses for a given core
+ *
+ * @param cache_id    cache ID (when l1 cache is per core)
+ *
+ * @return State of enabled buses
+ */
+__attribute__((always_inline))
+static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
+{
+    cache_bus_mask_t mask = (cache_bus_mask_t)0;
+
+    uint32_t ibus_mask = REG_READ(CACHE_L1_ICACHE_CTRL_REG);
+    if (cache_id == 0) {
+        mask = (cache_bus_mask_t)(mask | ((!(ibus_mask & CACHE_L1_ICACHE_SHUT_IBUS0)) ? CACHE_BUS_IBUS0 : 0));
+    } else if (cache_id == 1) {
+        mask = (cache_bus_mask_t)(mask | ((!(ibus_mask & CACHE_L1_ICACHE_SHUT_IBUS1)) ? CACHE_BUS_IBUS0 : 0));
+    }
+
+    uint32_t dbus_mask = REG_READ(CACHE_L1_DCACHE_CTRL_REG);
+    if (cache_id == 0) {
+        mask = (cache_bus_mask_t)(mask | ((!(dbus_mask & CACHE_L1_DCACHE_SHUT_DBUS0)) ? CACHE_BUS_DBUS0 : 0));
+    } else if (cache_id == 1) {
+        mask = (cache_bus_mask_t)(mask | ((!(dbus_mask & CACHE_L1_DCACHE_SHUT_DBUS1)) ? CACHE_BUS_DBUS0 : 0));
+    }
+
+    return mask;
+}
+
 /**
  * Disable the Cache Buses
  *

components/heap/port/esp32h4/memory_layout.c

@@ -69,8 +69,11 @@ const size_t soc_memory_type_count = sizeof(soc_memory_types) / sizeof(soc_memor
 #define APP_USABLE_DIRAM_END           (SOC_ROM_STACK_START - SOC_ROM_STACK_SIZE)
 
 const soc_memory_region_t soc_memory_regions[] = {
+#if CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
+    { SOC_RAM_ICACHE1_LOW,  (SOC_RAM_ICACHE1_HIGH - SOC_RAM_ICACHE1_LOW), SOC_MEMORY_TYPE_RAM,     SOC_RAM_ICACHE1_LOW,    true}, //ICache1, when in single core mode, ICache1 is used as RAM
+#endif
     { SOC_DIRAM_DRAM_LOW,   (APP_USABLE_DIRAM_END - SOC_DIRAM_DRAM_LOW),  SOC_MEMORY_TYPE_RAM,     SOC_DIRAM_IRAM_LOW,     false}, //D/IRAM, can be used as trace memory
-    { APP_USABLE_DIRAM_END, (SOC_DIRAM_DRAM_HIGH - APP_USABLE_DIRAM_END), SOC_MEMORY_TYPE_RAM,     APP_USABLE_DIRAM_END,    true}, //D/IRAM, can be used as trace memory (ROM reserved area)
+    { APP_USABLE_DIRAM_END, (SOC_DIRAM_DRAM_HIGH - APP_USABLE_DIRAM_END), SOC_MEMORY_TYPE_RAM,     APP_USABLE_DIRAM_END,   true}, //D/IRAM, can be used as trace memory (ROM reserved area)
 };
 
 const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);

components/soc/esp32h4/include/soc/soc.h

@@ -195,6 +195,10 @@
 #define SOC_ROM_STACK_START         0x4085d350
 #define SOC_ROM_STACK_SIZE          0x2000
 
+//ICache1 region
+#define SOC_RAM_ICACHE1_LOW    0x40860000
+#define SOC_RAM_ICACHE1_HIGH   0x40867fff
+
 //On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.
 //There is no HW NMI conception. SW should controlled the masked levels through INT_THRESH_REG.