Merge branch 'refactor/create_esp_hal_security' into 'master'

refactor: Created esp_hal_security component

Closes IDF-14086

See merge request espressif/esp-idf!44253

.gitlab/CODEOWNERS

@@ -98,6 +98,7 @@
 /components/esp_hal_ieee802154/       @esp-idf-codeowners/ieee802154
 /components/esp_hal_pmu/              @esp-idf-codeowners/power-management @esp-idf-codeowners/peripherals
 /components/esp_hal_rtc_timer/        @esp-idf-codeowners/power-management @esp-idf-codeowners/peripherals
+/components/esp_hal_security/         @esp-idf-codeowners/security @esp-idf-codeowners/peripherals
 /components/esp_hid/                  @esp-idf-codeowners/bluetooth
 /components/esp_http_client/          @esp-idf-codeowners/app-utilities
 /components/esp_http_server/          @esp-idf-codeowners/app-utilities
@@ -133,8 +134,6 @@
 /components/fatfs/                    @esp-idf-codeowners/storage
 /components/freertos/                 @esp-idf-codeowners/system
 /components/hal/                      @esp-idf-codeowners/peripherals
-/components/hal/test_apps/crypto/     @esp-idf-codeowners/peripherals @esp-idf-codeowners/security
-/components/hal/test_apps/tee/        @esp-idf-codeowners/peripherals @esp-idf-codeowners/security
 /components/heap/                     @esp-idf-codeowners/system
 /components/http_parser/              @esp-idf-codeowners/app-utilities
 /components/ieee802154/               @esp-idf-codeowners/ieee802154

components/bootloader/subproject/CMakeLists.txt

@@ -20,6 +20,7 @@ set(COMPONENTS
     bootloader
     esptool_py
     esp_hw_support
+    esp_hal_security
     esp_system
     freertos
     hal

components/bootloader/subproject/main/ld/esp32c5/bootloader.ld.in

@@ -91,8 +91,8 @@ SECTIONS
     *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
     *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
     *libesp_hal_wdt.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
-    *libhal.a:huk_hal.*(.literal .text .literal.* .text.*)
-    *libhal.a:key_mgr_hal.*(.literal .text .literal.* .text.*)
+    *libesp_hal_security.a:huk_hal.*(.literal .text .literal.* .text.*)
+    *libesp_hal_security.a:key_mgr_hal.*(.literal .text .literal.* .text.*)
     *libesp_security.a:esp_key_mgr.*(.literal .text .literal.* .text.*)
     *libesp_security.a:esp_crypto_periph_clk.*(.literal .text .literal.* .text.*)
     *libesp_security.a:esp_crypto_lock.*(.literal .text .literal.* .text.*)

components/bootloader/subproject/main/ld/esp32p4/bootloader.ld.in

@@ -89,7 +89,8 @@ SECTIONS
     *libhal.a:mmu_hal.*(.literal .text .literal.* .text.*)
     *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
     *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
-    *libhal.a:key_mgr_hal.*(.literal.key_mgr_hal_set_key_usage .text.key_mgr_hal_set_key_usage)
+    *libesp_hal_security.a:huk_hal.*(.literal .text .literal.* .text.*)
+    *libesp_hal_security.a:key_mgr_hal.*(.literal .text .literal.* .text.*)
     *libesp_security.a:esp_crypto_periph_clk.*(.literal .text .literal.* .text.*)
     *libesp_hal_wdt.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
     *libesp_hw_support.a:rtc_clk.*(.literal .text .literal.* .text.*)

components/bootloader/subproject/main/ld/esp32p4/bootloader.rev3.ld.in

@@ -90,8 +90,8 @@ SECTIONS
     *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
     *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
     *libesp_hal_wdt.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
-    *libhal.a:huk_hal.*(.literal .text .literal.* .text.*)
-    *libhal.a:key_mgr_hal.*(.literal .text .literal.* .text.*)
+    *libesp_hal_security.a:huk_hal.*(.literal .text .literal.* .text.*)
+    *libesp_hal_security.a:key_mgr_hal.*(.literal .text .literal.* .text.*)
     *libesp_security.a:esp_key_mgr.*(.literal .text .literal.* .text.*)
     *libesp_security.a:esp_crypto_periph_clk.*(.literal .text .literal.* .text.*)
     *libesp_security.a:esp_crypto_lock.*(.literal .text .literal.* .text.*)

components/bootloader/subproject/main/ld/esp32s31/bootloader.ld.in

@@ -90,8 +90,8 @@ SECTIONS
     *libhal.a:cache_hal.*(.literal .text .literal.* .text.*)
     *libhal.a:efuse_hal.*(.literal .text .literal.* .text.*)
     *libesp_hal_wdt.a:wdt_hal_iram.*(.literal .text .literal.* .text.*)
-    *libhal.a:huk_hal.*(.literal .text .literal.* .text.*)
-    *libhal.a:key_mgr_hal.*(.literal .text .literal.* .text.*)
+    *libesp_hal_security.a:huk_hal.*(.literal .text .literal.* .text.*)
+    *libesp_hal_security.a:key_mgr_hal.*(.literal .text .literal.* .text.*)
     *libesp_security.a:esp_key_mgr.*(.literal .text .literal.* .text.*)
     *libesp_security.a:esp_crypto_periph_clk.*(.literal .text .literal.* .text.*)
     *libesp_security.a:esp_crypto_lock.*(.literal .text .literal.* .text.*)

components/bootloader_support/CMakeLists.txt

@@ -28,7 +28,7 @@ if(esp_tee_build)
 
     idf_component_register(SRCS ${tee_srcs}
                            INCLUDE_DIRS ${tee_inc_dirs}
-                           PRIV_REQUIRES efuse esp_app_format esptool_py)
+                           PRIV_REQUIRES efuse esp_app_format esptool_py esp_hal_security)
     return()
 endif()
 
@@ -74,7 +74,8 @@ if(BOOTLOADER_BUILD OR CONFIG_APP_BUILD_TYPE_RAM)
         "private_include")
     set(priv_requires micro-ecc spi_flash efuse esp_bootloader_format esp_app_format esptool_py)
     # `esp_hal_ana_conv` is required by bootloader_random_esp32xx.c
-    list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_uart esp_hal_ana_conv esp_hal_rtc_timer esp_hal_clock)
+    list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_uart esp_hal_ana_conv esp_hal_rtc_timer
+         esp_hal_clock esp_hal_security)
     list(APPEND srcs
     "src/bootloader_init.c"
     "src/bootloader_clock_loader.c"
@@ -92,7 +93,8 @@ else()
     # heap is required for `heap_memory_layout.h` header
     set(priv_requires spi_flash mbedtls efuse heap esp_bootloader_format esp_app_format esptool_py)
     # `esp_hal_ana_conv` is required by bootloader_random_esp32xx.c
-    list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_uart esp_hal_ana_conv esp_hal_rtc_timer esp_hal_clock)
+    list(APPEND priv_requires esp_hal_wdt esp_hal_gpio esp_hal_uart esp_hal_ana_conv esp_hal_rtc_timer
+        esp_hal_clock esp_hal_security)
 endif()
 
 if(BOOTLOADER_BUILD)

components/bootloader_support/src/bootloader_mem.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/efuse/CMakeLists.txt

@@ -31,15 +31,15 @@ list(APPEND srcs "src/esp_efuse_api.c"
 
 if(non_os_build)
     idf_component_register(SRCS "${srcs}"
-                    PRIV_REQUIRES bootloader_support soc spi_flash
+                    PRIV_REQUIRES bootloader_support soc spi_flash esp_hal_security
                     INCLUDE_DIRS "${include_dirs}"
                     PRIV_INCLUDE_DIRS "${private_include}")
 else()
     list(APPEND srcs "src/esp_efuse_startup.c")
     if(${target} STREQUAL "linux")
-        set(priv_requires soc spi_flash esp_system esp_partition)
+        set(priv_requires soc spi_flash esp_system esp_partition esp_hal_security)
     else()
-        set(priv_requires bootloader_support soc spi_flash esp_system esp_partition esp_app_format)
+        set(priv_requires bootloader_support soc spi_flash esp_system esp_partition esp_app_format esp_hal_security)
     endif()
     idf_component_register(SRCS "${srcs}"
                     PRIV_REQUIRES "${priv_requires}"

components/esp_hal_security/.build-test-rules.yml

@@ -0,0 +1,11 @@
+# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
+
+components/esp_hal_security/test_apps/crypto:
+  depends_components:
+    - efuse
+    - mbedtls
+    - esp_security
+
+components/esp_hal_security/test_apps/tee:
+  disable:
+    - if: IDF_TARGET not in ["esp32c6", "esp32h2", "esp32c5", "esp32c61"]

components/esp_hal_security/CMakeLists.txt

@@ -0,0 +1,87 @@
+idf_build_get_property(target IDF_TARGET)
+idf_build_get_property(esp_tee_build ESP_TEE_BUILD)
+
+set(srcs)
+set(includes)
+
+# target specific include must be added before the generic one
+if(EXISTS "${CMAKE_CURRENT_LIST_DIR}/${target}/include")
+    list(APPEND includes "${target}/include")
+endif()
+list(APPEND includes "include")
+
+# Security HAL source files
+if(esp_tee_build)
+    if(CONFIG_SOC_AES_SUPPORTED)
+        list(APPEND srcs "aes_hal.c")
+    endif()
+
+    if(CONFIG_SOC_SHA_SUPPORTED)
+        list(APPEND srcs "sha_hal.c")
+    endif()
+
+    if(CONFIG_SOC_HMAC_SUPPORTED)
+        list(APPEND srcs "hmac_hal.c")
+    endif()
+
+    if(CONFIG_SOC_DIG_SIGN_SUPPORTED)
+        list(APPEND srcs "ds_hal.c")
+    endif()
+
+    if(CONFIG_SOC_ECC_SUPPORTED)
+        list(APPEND srcs "ecc_hal.c")
+    endif()
+
+    if(CONFIG_SOC_APM_SUPPORTED)
+        list(APPEND srcs "apm_hal.c")
+    endif()
+elseif(NOT BOOTLOADER_BUILD)
+    if(CONFIG_SOC_ECC_SUPPORTED)
+        list(APPEND srcs "ecc_hal.c")
+    endif()
+
+    if(CONFIG_SOC_ECDSA_SUPPORTED)
+        list(APPEND srcs "ecdsa_hal.c")
+    endif()
+
+    if(CONFIG_SOC_MPI_SUPPORTED)
+        list(APPEND srcs "mpi_hal.c")
+    endif()
+
+    if(CONFIG_SOC_SHA_SUPPORTED)
+        list(APPEND srcs "sha_hal.c")
+    endif()
+
+    if(CONFIG_SOC_AES_SUPPORTED)
+        list(APPEND srcs "aes_hal.c")
+    endif()
+
+    if(CONFIG_SOC_HMAC_SUPPORTED AND NOT CONFIG_IDF_TARGET_ESP32S2)
+        # For ESP32-S2 we do not have HMAC HAL layer implementation yet
+        list(APPEND srcs "hmac_hal.c")
+    endif()
+
+    if(CONFIG_SOC_DIG_SIGN_SUPPORTED AND NOT CONFIG_IDF_TARGET_ESP32S2)
+        # For ESP32-S2 we do not have DS HAL layer implementation yet
+        list(APPEND srcs "ds_hal.c")
+    endif()
+
+    if(CONFIG_SOC_APM_SUPPORTED)
+        list(APPEND srcs "apm_hal.c")
+    endif()
+endif()
+
+# Key Manager and HUK HAL (available in both bootloader and app builds)
+if(CONFIG_SOC_KEY_MANAGER_SUPPORTED)
+    list(APPEND srcs "key_mgr_hal.c")
+    list(APPEND srcs "huk_hal.c")
+endif()
+
+# MPU HAL (available in both bootloader and app builds)
+if(CONFIG_SOC_MPU_SUPPORTED)
+    list(APPEND srcs "mpu_hal.c")
+endif()
+
+idf_component_register(SRCS ${srcs}
+                       INCLUDE_DIRS ${includes}
+                       REQUIRES soc hal)

components/esp_hal_security/Kconfig.hal_security

@@ -0,0 +1,9 @@
+config HAL_ECDSA_GEN_SIG_CM
+    bool "Enable countermeasure for ECDSA signature generation"
+    depends on IDF_TARGET_ESP32H2
+    default n
+    help
+        Enable this option to apply the countermeasure for ECDSA signature operation
+        This countermeasure masks the real ECDSA sign operation
+        under dummy sign operations to add randomness in the generated power signature.
+        This countermeasure is only necessary for ESP32-H2 < v1.2.

components/esp_hal_security/README.md

@@ -0,0 +1,39 @@
+# `esp_hal_security` (G1 component)
+
+The `esp_hal_security` component provides a **Hardware Abstraction Layer** for security-related peripherals across all targets supported by ESP-IDF.
+
+This component contains HAL implementations for the following security peripherals:
+
+- **AES** (Advanced Encryption Standard)
+- **SHA** (Secure Hash Algorithm)
+- **HMAC** (Hash-based Message Authentication Code)
+- **MPI** (Modular Polynomial Integer - RSA operations)
+- **ECC** (Elliptic Curve Cryptography)
+- **ECDSA** (Elliptic Curve Digital Signature Algorithm)
+- **DS** (Digital Signature)
+- **Key Manager** (Hardware key management)
+- **HUK** (Hardware Unique Key)
+- **APM** (Access Permission Manager)
+- **MPU** (Memory Protection Unit)
+
+## Structure
+
+Similar to the main `hal` component, this component follows the same structure:
+
+- **HAL layer** (`include/esp_hal_security/<periph>_hal.h`): High-level abstraction for peripheral operations
+- **LL layer** (`<target>/include/esp_hal_security/<periph>_ll.h`): Low-level register access functions
+- **Types** (`include/esp_hal_security/<periph>_types.h`): Type definitions and constants shared across layers
+
+## Usage
+
+This component is automatically included when you depend on components that use security peripherals, such as:
+- `esp_security`
+- `mbedtls`
+- `bootloader_support` (for secure boot and flash encryption)
+
+You typically don't need to explicitly add this component to your `CMakeLists.txt` unless you're directly using security HAL APIs.
+
+## Note
+
+This component was split from the main `hal` component to better organize security-related functionality and manage dependencies. Components that previously depended on `hal` for security features should now depend on `esp_hal_security` instead.
+

components/esp_hal_security/aes_hal.c

@@ -39,7 +39,6 @@ void aes_hal_transform_block(const void *input_block, void *output_block)
     aes_ll_read_block(output_block);
 }
 
-
 #ifdef SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION
 void aes_hal_enable_pseudo_rounds(bool enable, uint8_t base, uint8_t increment, uint8_t key_rng_cnt)
 {
@@ -129,5 +128,4 @@ void aes_hal_gcm_read_tag(uint8_t *tag, size_t tag_len)
     memcpy(tag, tag_res, tag_len);
 }
 
-
 #endif //SOC_AES_SUPPORT_GCM

components/esp_hal_security/apm_hal.c

@@ -0,0 +1,526 @@
+/*
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <stdbool.h>
+#include "soc/soc_caps.h"
+#include "hal/assert.h"
+#include "hal/apm_hal.h"
+#include "hal/apm_ll.h"
+#include "hal/log.h"
+
+#if SOC_IS(ESP32P4)
+void apm_hal_hp_peri_access_enable(apm_ll_master_id_t master_id, apm_ll_hp_peri_t hp_peri,
+                                   apm_ll_secure_mode_t sec_mode, bool enable)
+{
+    apm_ll_hp_peri_access_enable(master_id, hp_peri, sec_mode, enable);
+}
+
+void apm_hal_lp_peri_access_enable(apm_ll_lp_peri_t lp_peri, bool enable)
+{
+    apm_ll_lp_peri_access_enable(lp_peri, enable);
+}
+
+void apm_hal_peri_region_config(uint32_t regn_num, uint32_t regn_low_addr, uint32_t regn_high_addr)
+{
+    apm_ll_peri_region_config(regn_num, regn_low_addr, regn_high_addr);
+}
+
+int apm_hal_peri_region_pms(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode,
+                            uint32_t regn_num, uint32_t regn_pms)
+{
+    return apm_ll_peri_region_pms(master_id, sec_mode, regn_num, regn_pms);
+}
+
+int apm_hal_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl, bool enable)
+{
+    return apm_ll_apm_ctrl_clk_gating_enable(apm_ctrl, enable);
+}
+
+void apm_hal_dma_region_config(uint32_t regn_num, uint32_t regn_low_addr, uint32_t regn_high_addr)
+{
+    apm_ll_dma_region_set_low_address(regn_num, regn_low_addr);
+    apm_ll_dma_region_set_high_address(regn_num, regn_high_addr);
+}
+
+void apm_hal_dma_region_pms(apm_hal_dma_region_config_data_t *pms_data)
+{
+    HAL_ASSERT(pms_data);
+
+    apm_ll_dma_region_r_pms(pms_data->dma_master, pms_data->pms_r_mask);
+    apm_ll_dma_region_w_pms(pms_data->dma_master, pms_data->pms_w_mask);
+}
+#else
+
+void apm_hal_set_master_sec_mode(uint32_t master_mask, apm_security_mode_t mode)
+{
+    master_mask &= APM_MASTER_MASK_ALL;
+    while (master_mask) {
+        uint32_t master = __builtin_ctz(master_mask);
+        master_mask &= ~(1U << master);
+        apm_ll_hp_tee_set_master_sec_mode(master, mode);
+#if SOC_APM_SUPPORT_LP_TEE_CTRL
+        if (master == APM_MASTER_LPCORE) {
+            apm_ll_lp_tee_set_master_sec_mode(master, mode);
+        }
+#endif
+    }
+}
+
+void apm_hal_set_master_sec_mode_all(apm_security_mode_t mode)
+{
+    apm_hal_set_master_sec_mode(APM_MASTER_MASK_ALL, mode);
+}
+
+#if SOC_APM_SUPPORT_CTRL_CFG_LOCK
+void apm_hal_lock_master_sec_mode(uint32_t master_mask)
+{
+    master_mask &= APM_MASTER_MASK_ALL;
+    while (master_mask) {
+        uint32_t master = __builtin_ctz(master_mask);
+        master_mask &= ~(1U << master);
+        apm_ll_hp_tee_lock_master_sec_mode(master);
+#if SOC_APM_SUPPORT_LP_TEE_CTRL
+        if (master == APM_MASTER_LPCORE) {
+            apm_ll_lp_tee_lock_master_sec_mode(master);
+        }
+#endif
+    }
+}
+
+void apm_hal_lock_master_sec_mode_all(void)
+{
+    apm_hal_lock_master_sec_mode(APM_MASTER_MASK_ALL);
+}
+#endif
+
+#if SOC_APM_SUPPORT_TEE_PERI_ACCESS_CTRL
+void apm_hal_tee_set_peri_access(apm_tee_ctrl_module_t ctrl_mod, uint64_t periph_mask, apm_security_mode_t mode, apm_perm_t pms)
+{
+    switch (ctrl_mod) {
+    case APM_TEE_CTRL_HP:
+        uint64_t hp_tee_peri_mask = periph_mask & APM_TEE_HP_PERIPH_MASK_ALL;
+        for (uint32_t periph = 0; periph < APM_TEE_HP_PERIPH_MAX; periph++) {
+            if (hp_tee_peri_mask & (1ULL << periph)) {
+                apm_ll_hp_tee_set_peri_access((apm_tee_hp_periph_t)periph, mode, pms);
+            }
+        }
+        apm_ll_hp_tee_enable_bus_err_resp(true);
+        break;
+#if SOC_APM_SUPPORT_LP_TEE_CTRL
+    case APM_TEE_CTRL_LP:
+        uint32_t lp_tee_peri_mask = (uint32_t)periph_mask & (uint32_t)APM_TEE_LP_PERIPH_MASK_ALL;
+        while (lp_tee_peri_mask) {
+            uint32_t periph = __builtin_ctz(lp_tee_peri_mask);
+            apm_ll_lp_tee_set_peri_access((apm_tee_lp_periph_t)periph, mode, pms);
+            lp_tee_peri_mask &= ~(1U << periph);
+        }
+        apm_ll_lp_tee_enable_bus_err_resp(true);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+
+void apm_hal_tee_set_peri_access_all(apm_tee_ctrl_module_t ctrl_mod, apm_security_mode_t mode, apm_perm_t pms)
+{
+    switch (ctrl_mod) {
+    case APM_TEE_CTRL_HP:
+        apm_hal_tee_set_peri_access(APM_TEE_CTRL_HP, (uint64_t)(APM_TEE_HP_PERIPH_MASK_ALL), mode, pms);
+        break;
+#if SOC_APM_SUPPORT_LP_TEE_CTRL
+    case APM_TEE_CTRL_LP:
+        apm_hal_tee_set_peri_access(APM_TEE_CTRL_LP, (uint64_t)(APM_TEE_LP_PERIPH_MASK_ALL), mode, pms);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+#endif
+
+void apm_hal_tee_enable_clk_gating(apm_tee_ctrl_module_t ctrl_mod, bool enable)
+{
+    switch (ctrl_mod) {
+    case APM_TEE_CTRL_HP:
+        apm_ll_hp_tee_enable_clk_gating(enable);
+        break;
+#if SOC_APM_SUPPORT_LP_TEE_CTRL
+    case APM_TEE_CTRL_LP:
+        apm_ll_lp_tee_enable_clk_gating(enable);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+
+void apm_hal_enable_ctrl_filter(apm_ctrl_module_t ctrl_mod, apm_ctrl_access_path_t path, bool enable)
+{
+    switch (ctrl_mod) {
+    case APM_CTRL_HP_APM:
+        apm_ll_hp_apm_enable_ctrl_filter(path, enable);
+        break;
+#if SOC_APM_LP_APM0_SUPPORTED
+    case APM_CTRL_LP_APM0:
+        apm_ll_lp_apm0_enable_ctrl_filter(path, enable);
+        break;
+#endif
+    case APM_CTRL_LP_APM:
+        apm_ll_lp_apm_enable_ctrl_filter(path, enable);
+        break;
+#if SOC_APM_CPU_APM_SUPPORTED
+    case APM_CTRL_CPU_APM:
+        apm_ll_cpu_apm_enable_ctrl_filter(path, enable);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+
+void apm_hal_enable_ctrl_filter_all(bool enable)
+{
+    apm_ll_hp_apm_enable_ctrl_filter_all(enable);
+#if SOC_APM_LP_APM0_SUPPORTED
+    apm_ll_lp_apm0_enable_ctrl_filter_all(enable);
+#endif
+    apm_ll_lp_apm_enable_ctrl_filter_all(enable);
+#if SOC_APM_CPU_APM_SUPPORTED
+    apm_ll_cpu_apm_enable_ctrl_filter_all(enable);
+#endif
+}
+
+void apm_hal_enable_region_filter(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, bool enable)
+{
+    switch (ctrl_mod) {
+    case APM_CTRL_HP_APM:
+        apm_ll_hp_apm_enable_region_filter(regn_num, enable);
+        break;
+#if SOC_APM_LP_APM0_SUPPORTED
+    case APM_CTRL_LP_APM0:
+        apm_ll_lp_apm0_enable_region_filter(regn_num, enable);
+        break;
+#endif
+    case APM_CTRL_LP_APM:
+        apm_ll_lp_apm_enable_region_filter(regn_num, enable);
+        break;
+#if SOC_APM_CPU_APM_SUPPORTED
+    case APM_CTRL_CPU_APM:
+        apm_ll_cpu_apm_enable_region_filter(regn_num, enable);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+
+void apm_hal_set_region_start_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr)
+{
+    switch (ctrl_mod) {
+    case APM_CTRL_HP_APM:
+        apm_ll_hp_apm_set_region_start_addr(regn_num, addr);
+        break;
+#if SOC_APM_LP_APM0_SUPPORTED
+    case APM_CTRL_LP_APM0:
+        apm_ll_lp_apm0_set_region_start_addr(regn_num, addr);
+        break;
+#endif
+    case APM_CTRL_LP_APM:
+        apm_ll_lp_apm_set_region_start_addr(regn_num, addr);
+        break;
+#if SOC_APM_CPU_APM_SUPPORTED
+    case APM_CTRL_CPU_APM:
+        apm_ll_cpu_apm_set_region_start_addr(regn_num, addr);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+
+void apm_hal_set_region_end_addr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, uint32_t addr)
+{
+    switch (ctrl_mod) {
+    case APM_CTRL_HP_APM:
+        apm_ll_hp_apm_set_region_end_addr(regn_num, addr);
+        break;
+#if SOC_APM_LP_APM0_SUPPORTED
+    case APM_CTRL_LP_APM0:
+        apm_ll_lp_apm0_set_region_end_addr(regn_num, addr);
+        break;
+#endif
+    case APM_CTRL_LP_APM:
+        apm_ll_lp_apm_set_region_end_addr(regn_num, addr);
+        break;
+#if SOC_APM_CPU_APM_SUPPORTED
+    case APM_CTRL_CPU_APM:
+        apm_ll_cpu_apm_set_region_end_addr(regn_num, addr);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+
+void apm_hal_set_sec_mode_region_attr(apm_ctrl_module_t ctrl_mod, uint32_t regn_num, apm_security_mode_t mode, uint32_t regn_pms)
+{
+    HAL_ASSERT(mode != APM_SEC_MODE_TEE);
+
+    switch (ctrl_mod) {
+    case APM_CTRL_HP_APM:
+        apm_ll_hp_apm_set_sec_mode_region_attr(regn_num, mode, regn_pms);
+        break;
+#if SOC_APM_LP_APM0_SUPPORTED
+    case APM_CTRL_LP_APM0:
+        apm_ll_lp_apm0_set_sec_mode_region_attr(regn_num, mode, regn_pms);
+        break;
+#endif
+    case APM_CTRL_LP_APM:
+        apm_ll_lp_apm_set_sec_mode_region_attr(regn_num, mode, regn_pms);
+        break;
+#if SOC_APM_CPU_APM_SUPPORTED
+    case APM_CTRL_CPU_APM:
+        apm_ll_cpu_apm_set_sec_mode_region_attr(regn_num, mode, regn_pms);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+
+void apm_hal_set_region_filter_cfg(apm_ctrl_module_t ctrl_mod, apm_security_mode_t mode, const apm_hal_ctrl_region_cfg_t *regn_cfg)
+{
+    HAL_ASSERT(regn_cfg);
+    HAL_ASSERT(mode != APM_SEC_MODE_TEE);
+
+    switch (ctrl_mod) {
+    case APM_CTRL_HP_APM:
+        apm_ll_hp_apm_set_region_start_addr(regn_cfg->regn_num, regn_cfg->regn_start_addr);
+        apm_ll_hp_apm_set_region_end_addr(regn_cfg->regn_num, regn_cfg->regn_end_addr);
+        apm_ll_hp_apm_set_sec_mode_region_attr(regn_cfg->regn_num, mode, regn_cfg->regn_pms);
+        break;
+#if SOC_APM_LP_APM0_SUPPORTED
+    case APM_CTRL_LP_APM0:
+        apm_ll_lp_apm0_set_region_start_addr(regn_cfg->regn_num, regn_cfg->regn_start_addr);
+        apm_ll_lp_apm0_set_region_end_addr(regn_cfg->regn_num, regn_cfg->regn_end_addr);
+        apm_ll_lp_apm0_set_sec_mode_region_attr(regn_cfg->regn_num, mode, regn_cfg->regn_pms);
+        break;
+#endif
+    case APM_CTRL_LP_APM:
+        apm_ll_lp_apm_set_region_start_addr(regn_cfg->regn_num, regn_cfg->regn_start_addr);
+        apm_ll_lp_apm_set_region_end_addr(regn_cfg->regn_num, regn_cfg->regn_end_addr);
+        apm_ll_lp_apm_set_sec_mode_region_attr(regn_cfg->regn_num, mode, regn_cfg->regn_pms);
+        break;
+#if SOC_APM_CPU_APM_SUPPORTED
+    case APM_CTRL_CPU_APM:
+        apm_ll_cpu_apm_set_region_start_addr(regn_cfg->regn_num, regn_cfg->regn_start_addr);
+        apm_ll_cpu_apm_set_region_end_addr(regn_cfg->regn_num, regn_cfg->regn_end_addr);
+        apm_ll_cpu_apm_set_sec_mode_region_attr(regn_cfg->regn_num, mode, regn_cfg->regn_pms);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+
+#if SOC_APM_SUPPORT_CTRL_CFG_LOCK
+void apm_hal_lock_region_filter_cfg(apm_ctrl_module_t ctrl_mod, uint32_t regn_num)
+{
+    switch (ctrl_mod) {
+    case APM_CTRL_HP_APM:
+        apm_ll_hp_apm_lock_sec_mode_region_attr(regn_num);
+        break;
+#if SOC_APM_LP_APM0_SUPPORTED
+    case APM_CTRL_LP_APM0:
+        apm_ll_lp_apm0_lock_sec_mode_region_attr(regn_num);
+        break;
+#endif
+    case APM_CTRL_LP_APM:
+        apm_ll_lp_apm_lock_sec_mode_region_attr(regn_num);
+        break;
+#if SOC_APM_CPU_APM_SUPPORTED
+    case APM_CTRL_CPU_APM:
+        apm_ll_cpu_apm_lock_sec_mode_region_attr(regn_num);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+#endif
+
+void apm_hal_set_ctrl_sec_mode_cfg(const apm_hal_ctrl_sec_mode_cfg_t *cfg)
+{
+    HAL_ASSERT(cfg);
+    HAL_ASSERT(cfg->regions);
+
+    for (uint32_t regn_idx = 0; regn_idx < cfg->regn_count; regn_idx++) {
+        const apm_hal_ctrl_region_cfg_t *region = &cfg->regions[regn_idx];
+        apm_hal_set_region_filter_cfg(cfg->ctrl_mod, cfg->mode, region);
+        apm_hal_enable_region_filter(cfg->ctrl_mod, region->regn_num, region->filter_en);
+#if SOC_APM_SUPPORT_CTRL_CFG_LOCK
+        if (region->lock_en) {
+            apm_hal_lock_region_filter_cfg(cfg->ctrl_mod, region->regn_num);
+        }
+#endif
+        apm_hal_enable_ctrl_filter(cfg->ctrl_mod, region->path_id, true);
+    }
+}
+
+uint32_t apm_hal_get_exception_type(apm_hal_ctrl_info_t *ctrl_info)
+{
+    HAL_ASSERT(ctrl_info);
+
+    switch (ctrl_info->ctrl_mod) {
+    case APM_CTRL_HP_APM:
+        return apm_ll_hp_apm_get_excp_type(ctrl_info->path);
+#if SOC_APM_LP_APM0_SUPPORTED
+    case APM_CTRL_LP_APM0:
+        return apm_ll_lp_apm0_get_excp_type(ctrl_info->path);
+#endif
+    case APM_CTRL_LP_APM:
+        return apm_ll_lp_apm_get_excp_type(ctrl_info->path);
+#if SOC_APM_CPU_APM_SUPPORTED
+    case APM_CTRL_CPU_APM:
+        return apm_ll_cpu_apm_get_excp_type(ctrl_info->path);
+#endif
+    default:
+        return UINT8_MAX;
+    }
+}
+
+void apm_hal_clear_exception_status(apm_hal_ctrl_info_t *ctrl_info)
+{
+    HAL_ASSERT(ctrl_info);
+
+    switch (ctrl_info->ctrl_mod) {
+    case APM_CTRL_HP_APM:
+        apm_ll_hp_apm_clear_ctrl_excp_status(ctrl_info->path);
+        break;
+#if SOC_APM_LP_APM0_SUPPORTED
+    case APM_CTRL_LP_APM0:
+        apm_ll_lp_apm0_clear_ctrl_excp_status(ctrl_info->path);
+        break;
+#endif
+    case APM_CTRL_LP_APM:
+        apm_ll_lp_apm_clear_ctrl_excp_status(ctrl_info->path);
+        break;
+#if SOC_APM_CPU_APM_SUPPORTED
+    case APM_CTRL_CPU_APM:
+        apm_ll_cpu_apm_clear_ctrl_excp_status(ctrl_info->path);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+
+void apm_hal_get_exception_info(apm_hal_ctrl_info_t *ctrl_info, apm_ctrl_exception_info_t *excp_info)
+{
+    HAL_ASSERT(ctrl_info);
+    HAL_ASSERT(excp_info);
+
+    switch (ctrl_info->ctrl_mod) {
+    case APM_CTRL_HP_APM:
+        apm_ll_hp_apm_get_excp_info(ctrl_info->path, excp_info);
+        break;
+#if SOC_APM_LP_APM0_SUPPORTED
+    case APM_CTRL_LP_APM0:
+        apm_ll_lp_apm0_get_excp_info(ctrl_info->path, excp_info);
+        break;
+#endif
+    case APM_CTRL_LP_APM:
+        apm_ll_lp_apm_get_excp_info(ctrl_info->path, excp_info);
+        break;
+#if SOC_APM_CPU_APM_SUPPORTED
+    case APM_CTRL_CPU_APM:
+        apm_ll_cpu_apm_get_excp_info(ctrl_info->path, excp_info);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+
+void apm_hal_enable_intr(apm_hal_ctrl_info_t *ctrl_info, bool enable)
+{
+    HAL_ASSERT(ctrl_info);
+
+    switch (ctrl_info->ctrl_mod) {
+    case APM_CTRL_HP_APM:
+        apm_ll_hp_apm_enable_ctrl_intr(ctrl_info->path, enable);
+        break;
+#if SOC_APM_LP_APM0_SUPPORTED
+    case APM_CTRL_LP_APM0:
+        apm_ll_lp_apm0_enable_ctrl_intr(ctrl_info->path, enable);
+        break;
+#endif
+    case APM_CTRL_LP_APM:
+        apm_ll_lp_apm_enable_ctrl_intr(ctrl_info->path, enable);
+        break;
+#if SOC_APM_CPU_APM_SUPPORTED
+    case APM_CTRL_CPU_APM:
+        apm_ll_cpu_apm_enable_ctrl_intr(ctrl_info->path, enable);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+
+int apm_hal_get_intr_src_num(apm_hal_ctrl_info_t *ctrl_info)
+{
+    HAL_ASSERT(ctrl_info);
+
+    switch (ctrl_info->ctrl_mod) {
+    case APM_CTRL_HP_APM:
+        return apm_ll_hp_apm_get_ctrl_intr_src(ctrl_info->path);
+#if SOC_APM_LP_APM0_SUPPORTED
+    case APM_CTRL_LP_APM0:
+        return apm_ll_lp_apm0_get_ctrl_intr_src(ctrl_info->path);
+#endif
+    case APM_CTRL_LP_APM:
+        return apm_ll_lp_apm_get_ctrl_intr_src(ctrl_info->path);
+#if SOC_APM_CPU_APM_SUPPORTED
+    case APM_CTRL_CPU_APM:
+        return apm_ll_cpu_apm_get_ctrl_intr_src(ctrl_info->path);
+#endif
+    default:
+        return -1;
+    }
+}
+
+void apm_hal_enable_reset_event_bypass(bool enable)
+{
+    apm_ll_enable_reset_event_bypass(enable);
+}
+
+void apm_hal_enable_ctrl_clk_gating(apm_ctrl_module_t ctrl_mod, bool enable)
+{
+    switch (ctrl_mod) {
+    case APM_CTRL_HP_APM:
+        apm_ll_hp_apm_enable_ctrl_clk_gating(enable);
+        break;
+#if SOC_APM_LP_APM0_SUPPORTED
+    case APM_CTRL_LP_APM0:
+        apm_ll_lp_apm0_enable_ctrl_clk_gating(enable);
+        break;
+#endif
+    case APM_CTRL_LP_APM:
+        apm_ll_lp_apm_enable_ctrl_clk_gating(enable);
+        break;
+#if SOC_APM_CPU_APM_SUPPORTED
+    case APM_CTRL_CPU_APM:
+        apm_ll_cpu_apm_enable_ctrl_clk_gating(enable);
+        break;
+#endif
+    default:
+        break;
+    }
+}
+
+#endif //SOC_IS(ESP32P4)

components/esp_hal_security/ecdsa_hal.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -85,11 +85,11 @@ bool ecdsa_hal_get_operation_result(void)
 }
 
 static void ecdsa_hal_gen_signature_inner(const uint8_t *hash, uint8_t *r_out,
-                              uint8_t *s_out, uint16_t len)
+                                          uint8_t *s_out, uint16_t len)
 {
     ecdsa_ll_set_stage(ECDSA_STAGE_START_CALC);
 
-    while(ecdsa_ll_get_state() != ECDSA_STATE_LOAD) {
+    while (ecdsa_ll_get_state() != ECDSA_STATE_LOAD) {
         ;
     }
 
@@ -113,7 +113,7 @@ static void ecdsa_hal_gen_signature_inner(const uint8_t *hash, uint8_t *r_out,
 
 #if HAL_CONFIG(ECDSA_GEN_SIG_CM)
 __attribute__((optimize("O0"))) static void ecdsa_hal_gen_signature_with_countermeasure(const uint8_t *hash, uint8_t *r_out,
-                       uint8_t *s_out, uint16_t len)
+                                                                                        uint8_t *s_out, uint16_t len)
 {
     uint8_t tmp_r_out[32] = {};
     uint8_t tmp_s_out[32] = {};
@@ -141,16 +141,14 @@ __attribute__((optimize("O0"))) static void ecdsa_hal_gen_signature_with_counter
 }
 #endif /* HAL_CONFIG_ECDSA_GEN_SIG_CM */
 
-
-
 void ecdsa_hal_gen_signature(ecdsa_hal_config_t *conf, const uint8_t *hash,
-                        uint8_t *r_out, uint8_t *s_out, uint16_t len)
+                             uint8_t *r_out, uint8_t *s_out, uint16_t len)
 {
     if (len != ECDSA_HAL_P192_COMPONENT_LEN && len != ECDSA_HAL_P256_COMPONENT_LEN
 #if SOC_ECDSA_SUPPORT_CURVE_P384
-    && len != ECDSA_HAL_P384_COMPONENT_LEN
+            && len != ECDSA_HAL_P384_COMPONENT_LEN
 #endif /* SOC_ECDSA_SUPPORT_CURVE_P384 */
-    ) {
+       ) {
         HAL_ASSERT(false && "Incorrect length");
     }
 
@@ -183,9 +181,9 @@ int ecdsa_hal_verify_signature(ecdsa_hal_config_t *conf, const uint8_t *hash, co
 {
     if (len != ECDSA_HAL_P192_COMPONENT_LEN && len != ECDSA_HAL_P256_COMPONENT_LEN
 #if SOC_ECDSA_SUPPORT_CURVE_P384
-    && len != ECDSA_HAL_P384_COMPONENT_LEN
+            && len != ECDSA_HAL_P384_COMPONENT_LEN
 #endif /* SOC_ECDSA_SUPPORT_CURVE_P384 */
-    ) {
+       ) {
         HAL_ASSERT(false && "Incorrect length");
     }
 
@@ -197,7 +195,7 @@ int ecdsa_hal_verify_signature(ecdsa_hal_config_t *conf, const uint8_t *hash, co
 
     ecdsa_ll_set_stage(ECDSA_STAGE_START_CALC);
 
-    while(ecdsa_ll_get_state() != ECDSA_STATE_LOAD) {
+    while (ecdsa_ll_get_state() != ECDSA_STATE_LOAD) {
         ;
     }
 
@@ -223,9 +221,9 @@ void ecdsa_hal_export_pubkey(ecdsa_hal_config_t *conf, uint8_t *pub_x, uint8_t *
 {
     if (len != ECDSA_HAL_P192_COMPONENT_LEN && len != ECDSA_HAL_P256_COMPONENT_LEN
 #if SOC_ECDSA_SUPPORT_CURVE_P384
-    && len != ECDSA_HAL_P384_COMPONENT_LEN
+            && len != ECDSA_HAL_P384_COMPONENT_LEN
 #endif /* SOC_ECDSA_SUPPORT_CURVE_P384 */
-    ) {
+       ) {
         HAL_ASSERT(false && "Incorrect length");
     }
 
@@ -237,7 +235,7 @@ void ecdsa_hal_export_pubkey(ecdsa_hal_config_t *conf, uint8_t *pub_x, uint8_t *
 
     ecdsa_ll_set_stage(ECDSA_STAGE_START_CALC);
 
-    while(ecdsa_ll_get_state() != ECDSA_STATE_LOAD) {
+    while (ecdsa_ll_get_state() != ECDSA_STATE_LOAD) {
         ;
     }
 

components/esp_hal_security/esp32/include/hal/aes_ll.h

@@ -17,7 +17,6 @@
 extern "C" {
 #endif
 
-
 /**
  * @brief State of AES accelerator, busy or idle
  *
@@ -149,7 +148,6 @@ static inline void aes_ll_read_block(void *output)
     esp_dport_access_read_buffer(output_words, AES_TEXT_BASE, AES_BLOCK_WORDS);
 }
 
-
 /**
  * @brief Starts block transform
  *
@@ -159,7 +157,6 @@ static inline void aes_ll_start_transform(void)
     DPORT_REG_WRITE(AES_START_REG, 1);
 }
 
-
 /**
  * @brief Read state of AES accelerator
  *

components/esp_hal_security/esp32/include/hal/mpi_ll.h

@@ -18,7 +18,6 @@
 extern "C" {
 #endif
 
-
 /**
  * @brief Enable the bus clock for MPI peripheral module
  *

components/esp_hal_security/esp32c2/include/hal/ecc_ll.h

@@ -75,34 +75,34 @@ static inline void ecc_ll_clear_interrupt(void)
 
 static inline void ecc_ll_set_mode(ecc_mode_t mode)
 {
-    switch(mode) {
-        case ECC_MODE_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
-            break;
-        case ECC_MODE_VERIFY:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
-            break;
-        case ECC_MODE_VERIFY_THEN_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported mode");
-            break;
+    switch (mode) {
+    case ECC_MODE_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
+        break;
+    case ECC_MODE_VERIFY:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
+        break;
+    case ECC_MODE_VERIFY_THEN_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported mode");
+        break;
     }
 }
 
 static inline void ecc_ll_set_curve(ecc_curve_t curve)
 {
-    switch(curve) {
-        case ECC_CURVE_SECP256R1:
-            REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
-            break;
-        case ECC_CURVE_SECP192R1:
-            REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    switch (curve) {
+    case ECC_CURVE_SECP256R1:
+        REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
+        break;
+    case ECC_CURVE_SECP192R1:
+        REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
@@ -111,18 +111,18 @@ static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf,
     uint32_t reg;
     uint32_t word;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_1_REG;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_1_REG;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_1_REG;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_1_REG;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_1_REG;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_1_REG;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     for (int i = 0; i < len; i += 4) {
@@ -160,18 +160,18 @@ static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_
 {
     uint32_t reg;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_1_REG;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_1_REG;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_1_REG;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_1_REG;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_1_REG;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_1_REG;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     memcpy(buf, (void *)reg, len);

components/esp_hal_security/esp32c2/include/hal/sha_ll.h

@@ -14,7 +14,6 @@
 extern "C" {
 #endif
 
-
 /**
  * @brief Enable the bus clock for SHA peripheral module
  *
@@ -181,7 +180,6 @@ static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state
     }
 }
 
-
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32c3/include/hal/aes_ll.h

@@ -127,7 +127,7 @@ static inline void aes_ll_read_block(void *output)
     for (size_t i = 0; i < AES_BLOCK_WORDS; i++) {
         output_word = REG_READ(AES_TEXT_OUT_BASE + (i * REG_WIDTH));
         /* Memcpy to avoid potential unaligned access */
-        memcpy( (uint8_t*)output + i * 4, &output_word, sizeof(output_word));
+        memcpy((uint8_t*)output + i * 4, &output_word, sizeof(output_word));
     }
 }
 
@@ -140,7 +140,6 @@ static inline void aes_ll_start_transform(void)
     REG_WRITE(AES_TRIGGER_REG, 1);
 }
 
-
 /**
  * @brief Read state of AES accelerator
  *
@@ -151,7 +150,6 @@ static inline esp_aes_state_t aes_ll_get_state(void)
     return (esp_aes_state_t)REG_READ(AES_STATE_REG);
 }
 
-
 /**
  * @brief Set mode of operation
  *
@@ -204,7 +202,7 @@ static inline void aes_ll_set_iv(const uint8_t *iv)
     uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_BASE);
     uint32_t iv_word;
 
-    for (int i = 0; i < IV_WORDS; i++ ) {
+    for (int i = 0; i < IV_WORDS; i++) {
         /* Memcpy to avoid potential unaligned access */
         memcpy(&iv_word, iv + 4 * i, sizeof(iv_word));
         REG_WRITE(&reg_addr_buf[i], iv_word);
@@ -255,7 +253,6 @@ static inline void aes_ll_interrupt_clear(void)
     REG_WRITE(AES_INT_CLEAR_REG, 1);
 }
 
-
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32c3/include/hal/ds_ll.h

@@ -97,7 +97,7 @@ static inline ds_key_check_t ds_ll_key_error_source(void)
 static inline void ds_ll_configure_iv(const uint32_t *iv)
 {
     for (size_t i = 0; i < (SOC_DS_KEY_PARAM_MD_IV_LENGTH / sizeof(uint32_t)); i++) {
-        REG_WRITE(DS_IV_BASE + (i * 4) , iv[i]);
+        REG_WRITE(DS_IV_BASE + (i * 4), iv[i]);
     }
 }
 
@@ -111,7 +111,7 @@ static inline void ds_ll_write_message(const uint8_t *msg, size_t size)
 {
     memcpy((uint8_t*) DS_X_BASE, msg, size);
     // Fence ensures all memory operations are completed before proceeding further
-    asm volatile ("fence");
+    asm volatile("fence");
 }
 
 /**
@@ -125,19 +125,22 @@ static inline void ds_ll_write_private_key_params(const uint8_t *encrypted_key_p
 
        (note if ETS_DS_MAX_BITS == 4096, this should be the same as copying data->c to hardware in one fragment)
     */
-    typedef struct { uint32_t addr; size_t len; } frag_t;
+    typedef struct {
+        uint32_t addr;
+        size_t len;
+    } frag_t;
     const frag_t frags[] = {
-                            {DS_C_Y_BASE,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_C_M_BASE,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_C_RB_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_C_BOX_BASE, DS_IV_BASE - DS_C_BOX_BASE},
+        {DS_C_Y_BASE,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_C_M_BASE,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_C_RB_BASE, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_C_BOX_BASE, DS_IV_BASE - DS_C_BOX_BASE},
     };
-    const size_t NUM_FRAGS = sizeof(frags)/sizeof(frag_t);
+    const size_t NUM_FRAGS = sizeof(frags) / sizeof(frag_t);
     const uint8_t *from = encrypted_key_params;
 
     for (int i = 0; i < NUM_FRAGS; i++) {
         memcpy((uint8_t *)frags[i].addr, from, frags[i].len);
-        asm volatile ("fence");
+        asm volatile("fence");
         // Fence ensures all memory operations are completed before proceeding further
         from += frags[i].len;
     }
@@ -164,7 +167,7 @@ static inline void ds_ll_start_sign(void)
 static inline ds_signature_check_t ds_ll_check_signature(void)
 {
     uint32_t result = REG_READ(DS_QUERY_CHECK_REG);
-    switch(result) {
+    switch (result) {
     case 0:
         return DS_SIGNATURE_OK;
     case 1:
@@ -186,7 +189,7 @@ static inline void ds_ll_read_result(uint8_t *result, size_t size)
 {
     memcpy(result, (uint8_t*) DS_Z_BASE, size);
     // Fence ensures all memory operations are completed before proceeding further
-    asm volatile ("fence");
+    asm volatile("fence");
 }
 
 /**

components/esp_hal_security/esp32c3/include/hal/hmac_ll.h

@@ -81,7 +81,7 @@ static inline void hmac_ll_start(void)
  */
 static inline void hmac_ll_config_output(hmac_hal_output_t config)
 {
-    switch(config) {
+    switch (config) {
     case HMAC_OUTPUT_USER:
         REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_UP);
         break;
@@ -138,7 +138,7 @@ static inline void hmac_ll_wait_idle(void)
     uint32_t query;
     do {
         query = REG_READ(HMAC_QUERY_BUSY_REG);
-    } while(query != 0);
+    } while (query != 0);
 }
 
 /**

components/esp_hal_security/esp32c3/include/hal/mpi_ll.h

@@ -19,7 +19,6 @@
 extern "C" {
 #endif
 
-
 /**
  * @brief Enable the bus clock for MPI peripheral module
  *

components/esp_hal_security/esp32c3/include/hal/sha_ll.h

@@ -184,7 +184,6 @@ static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state
     }
 }
 
-
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32c5/include/hal/aes_ll.h

@@ -113,7 +113,7 @@ static inline void aes_ll_read_block(void *output)
     for (size_t i = 0; i < AES_BLOCK_WORDS; i++) {
         output_word = REG_READ(AES_TEXT_OUT_0_REG + (i * REG_WIDTH));
         /* Memcpy to avoid potential unaligned access */
-        memcpy( (uint8_t*)output + i * 4, &output_word, sizeof(output_word));
+        memcpy((uint8_t*)output + i * 4, &output_word, sizeof(output_word));
     }
 }
 
@@ -126,7 +126,6 @@ static inline void aes_ll_start_transform(void)
     REG_WRITE(AES_TRIGGER_REG, 1);
 }
 
-
 /**
  * @brief Read state of AES accelerator
  *
@@ -137,7 +136,6 @@ static inline esp_aes_state_t aes_ll_get_state(void)
     return (esp_aes_state_t)REG_READ(AES_STATE_REG);
 }
 
-
 /**
  * @brief Set mode of operation
  *
@@ -190,7 +188,7 @@ static inline void aes_ll_set_iv(const uint8_t *iv)
     uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_MEM);
     uint32_t iv_word;
 
-    for (int i = 0; i < IV_WORDS; i++ ) {
+    for (int i = 0; i < IV_WORDS; i++) {
         /* Memcpy to avoid potential unaligned access */
         memcpy(&iv_word, iv + 4 * i, sizeof(iv_word));
         REG_WRITE(&reg_addr_buf[i], iv_word);

components/esp_hal_security/esp32c5/include/hal/ds_ll.h

@@ -20,7 +20,6 @@
 #include "soc/pcr_struct.h"
 #include "hal/ds_types.h"
 
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -92,7 +91,7 @@ static inline void ds_ll_set_key_source(ds_key_source_t key_source)
 static inline void ds_ll_configure_iv(const uint32_t *iv)
 {
     for (size_t i = 0; i < (SOC_DS_KEY_PARAM_MD_IV_LENGTH / sizeof(uint32_t)); i++) {
-        REG_WRITE(DS_IV_MEM + (i * 4) , iv[i]);
+        REG_WRITE(DS_IV_MEM + (i * 4), iv[i]);
     }
 }
 
@@ -106,7 +105,7 @@ static inline void ds_ll_write_message(const uint8_t *msg, size_t size)
 {
     memcpy((uint8_t*) DS_X_MEM, msg, size);
     // Fence ensures all memory operations are completed before proceeding further
-    asm volatile ("fence");
+    asm volatile("fence");
 }
 
 /**
@@ -120,20 +119,23 @@ static inline void ds_ll_write_private_key_params(const uint8_t *encrypted_key_p
 
        (note if ETS_DS_MAX_BITS == 4096, this should be the same as copying data->c to hardware in one fragment)
     */
-    typedef struct { uint32_t addr; size_t len; } frag_t;
+    typedef struct {
+        uint32_t addr;
+        size_t len;
+    } frag_t;
     const frag_t frags[] = {
-                            {DS_Y_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_M_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_RB_MEM, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_BOX_MEM, DS_IV_MEM - DS_BOX_MEM},
+        {DS_Y_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_M_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_RB_MEM, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_BOX_MEM, DS_IV_MEM - DS_BOX_MEM},
     };
-    const size_t NUM_FRAGS = sizeof(frags)/sizeof(frag_t);
+    const size_t NUM_FRAGS = sizeof(frags) / sizeof(frag_t);
     const uint8_t *from = encrypted_key_params;
 
     for (int i = 0; i < NUM_FRAGS; i++) {
         memcpy((uint8_t *)frags[i].addr, from, frags[i].len);
         // Fence ensures all memory operations are completed before proceeding further
-        asm volatile ("fence");
+        asm volatile("fence");
         from += frags[i].len;
     }
 }
@@ -159,7 +161,7 @@ static inline void ds_ll_start_sign(void)
 static inline ds_signature_check_t ds_ll_check_signature(void)
 {
     uint32_t result = REG_READ(DS_QUERY_CHECK_REG);
-    switch(result) {
+    switch (result) {
     case 0:
         return DS_SIGNATURE_OK;
     case 1:
@@ -181,7 +183,7 @@ static inline void ds_ll_read_result(uint8_t *result, size_t size)
 {
     memcpy(result, (uint8_t*) DS_Z_MEM, size);
     // Fence ensures all memory operations are completed before proceeding further
-    asm volatile ("fence");
+    asm volatile("fence");
 }
 
 /**

components/esp_hal_security/esp32c5/include/hal/ecc_ll.h

@@ -78,73 +78,73 @@ static inline void ecc_ll_clear_interrupt(void)
 
 static inline void ecc_ll_set_mode(ecc_mode_t mode)
 {
-    switch(mode) {
-        case ECC_MODE_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
-            break;
-        case ECC_MODE_VERIFY:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
-            break;
-        case ECC_MODE_VERIFY_THEN_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
-            break;
-        case ECC_MODE_JACOBIAN_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
-            break;
-        case ECC_MODE_POINT_ADD:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5);
-            break;
-        case ECC_MODE_JACOBIAN_POINT_VERIFY:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6);
-            break;
-        case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7);
-            break;
-        case ECC_MODE_MOD_ADD:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8);
-            break;
-        case ECC_MODE_MOD_SUB:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9);
-            break;
-        case ECC_MODE_MOD_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10);
-            break;
-        case ECC_MODE_INVERSE_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported mode");
-            break;
+    switch (mode) {
+    case ECC_MODE_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
+        break;
+    case ECC_MODE_VERIFY:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
+        break;
+    case ECC_MODE_VERIFY_THEN_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
+        break;
+    case ECC_MODE_JACOBIAN_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
+        break;
+    case ECC_MODE_POINT_ADD:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5);
+        break;
+    case ECC_MODE_JACOBIAN_POINT_VERIFY:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6);
+        break;
+    case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7);
+        break;
+    case ECC_MODE_MOD_ADD:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8);
+        break;
+    case ECC_MODE_MOD_SUB:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9);
+        break;
+    case ECC_MODE_MOD_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10);
+        break;
+    case ECC_MODE_INVERSE_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported mode");
+        break;
     }
 }
 
 static inline void ecc_ll_set_curve(ecc_curve_t curve)
 {
-    switch(curve) {
-        case ECC_CURVE_SECP192R1:
-        case ECC_CURVE_SECP256R1:
-        case ECC_CURVE_SECP384R1:
-        case ECC_CURVE_SM2:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH, curve);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    switch (curve) {
+    case ECC_CURVE_SECP192R1:
+    case ECC_CURVE_SECP256R1:
+    case ECC_CURVE_SECP384R1:
+    case ECC_CURVE_SM2:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH, curve);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
 static inline void ecc_ll_set_mod_base(ecc_mod_base_t base)
 {
-    switch(base) {
-        case ECC_MOD_N:
-            REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
-            break;
-        case ECC_MOD_P:
-            REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    switch (base) {
+    case ECC_MOD_N:
+        REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
+        break;
+    case ECC_MOD_P:
+        REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
@@ -167,27 +167,27 @@ static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf,
     uint32_t reg;
     uint32_t word;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_MEM;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_MEM;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_MEM;
-            break;
-        case ECC_PARAM_QX:
-            reg = ECC_MULT_QX_MEM;
-            break;
-        case ECC_PARAM_QY:
-            reg = ECC_MULT_QY_MEM;
-            break;
-        case ECC_PARAM_QZ:
-            reg = ECC_MULT_QZ_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_MEM;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_MEM;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_MEM;
+        break;
+    case ECC_PARAM_QX:
+        reg = ECC_MULT_QX_MEM;
+        break;
+    case ECC_PARAM_QY:
+        reg = ECC_MULT_QY_MEM;
+        break;
+    case ECC_PARAM_QZ:
+        reg = ECC_MULT_QZ_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     for (int i = 0; i < len; i += 4) {
@@ -230,27 +230,27 @@ static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_
 {
     uint32_t reg;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_MEM;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_MEM;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_MEM;
-            break;
-        case ECC_PARAM_QX:
-            reg = ECC_MULT_QX_MEM;
-            break;
-        case ECC_PARAM_QY:
-            reg = ECC_MULT_QY_MEM;
-            break;
-        case ECC_PARAM_QZ:
-            reg = ECC_MULT_QZ_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_MEM;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_MEM;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_MEM;
+        break;
+    case ECC_PARAM_QX:
+        reg = ECC_MULT_QX_MEM;
+        break;
+    case ECC_PARAM_QY:
+        reg = ECC_MULT_QY_MEM;
+        break;
+    case ECC_PARAM_QZ:
+        reg = ECC_MULT_QZ_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     memcpy(buf, (void *)reg, len);

components/esp_hal_security/esp32c5/include/hal/ecdsa_ll.h

@@ -112,15 +112,15 @@ static inline void ecdsa_ll_reset_register(void)
 static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_CALC_DONE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 1);
-            break;
-        case ECDSA_INT_SHA_RELEASE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 1);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported interrupt type");
-            break;
+    case ECDSA_INT_CALC_DONE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 1);
+        break;
+    case ECDSA_INT_SHA_RELEASE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 1);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported interrupt type");
+        break;
     }
 }
 
@@ -132,15 +132,15 @@ static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_disable_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_CALC_DONE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 0);
-            break;
-        case ECDSA_INT_SHA_RELEASE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 0);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported interrupt type");
-            break;
+    case ECDSA_INT_CALC_DONE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 0);
+        break;
+    case ECDSA_INT_SHA_RELEASE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 0);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported interrupt type");
+        break;
     }
 }
 
@@ -152,15 +152,15 @@ static inline void ecdsa_ll_disable_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_clear_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_CALC_DONE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_CLR, 1);
-            break;
-        case ECDSA_INT_SHA_RELEASE:
-            REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_SHA_RELEASE_INT_CLR, 1);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported interrupt type");
-            break;
+    case ECDSA_INT_CALC_DONE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_CLR, 1);
+        break;
+    case ECDSA_INT_SHA_RELEASE:
+        REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_SHA_RELEASE_INT_CLR, 1);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported interrupt type");
+        break;
     }
 }
 
@@ -172,18 +172,18 @@ static inline void ecdsa_ll_clear_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_set_mode(ecdsa_mode_t mode)
 {
     switch (mode) {
-        case ECDSA_MODE_SIGN_VERIFY:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 0);
-            break;
-        case ECDSA_MODE_SIGN_GEN:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 1);
-            break;
-        case ECDSA_MODE_EXPORT_PUBKEY:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 2);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported mode");
-            break;
+    case ECDSA_MODE_SIGN_VERIFY:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 0);
+        break;
+    case ECDSA_MODE_SIGN_GEN:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 1);
+        break;
+    case ECDSA_MODE_EXPORT_PUBKEY:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 2);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported mode");
+        break;
     }
 }
 
@@ -195,15 +195,15 @@ static inline void ecdsa_ll_set_mode(ecdsa_mode_t mode)
 static inline void ecdsa_ll_set_curve(ecdsa_curve_t curve)
 {
     switch (curve) {
-        case ECDSA_CURVE_SECP192R1:
-        case ECDSA_CURVE_SECP256R1:
-        case ECDSA_CURVE_SECP384R1:
-        case ECDSA_CURVE_SM2:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_ECC_CURVE, curve);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    case ECDSA_CURVE_SECP192R1:
+    case ECDSA_CURVE_SECP256R1:
+    case ECDSA_CURVE_SECP384R1:
+    case ECDSA_CURVE_SM2:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_ECC_CURVE, curve);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
@@ -215,15 +215,15 @@ static inline void ecdsa_ll_set_curve(ecdsa_curve_t curve)
 static inline void ecdsa_ll_set_z_mode(ecdsa_ll_sha_mode_t mode)
 {
     switch (mode) {
-        case ECDSA_Z_USE_SHA_PERI:
-            REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
-            break;
-        case ECDSA_Z_USER_PROVIDED:
-            REG_SET_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            break;
+    case ECDSA_Z_USE_SHA_PERI:
+        REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
+        break;
+    case ECDSA_Z_USER_PROVIDED:
+        REG_SET_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        break;
     }
 }
 
@@ -235,17 +235,17 @@ static inline void ecdsa_ll_set_z_mode(ecdsa_ll_sha_mode_t mode)
 static inline void ecdsa_ll_set_k_type(ecdsa_sign_type_t type)
 {
     switch (type) {
-        case ECDSA_K_TYPE_TRNG:
-            REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
-            break;
+    case ECDSA_K_TYPE_TRNG:
+        REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
+        break;
 #ifdef SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE
-        case ECDSA_K_TYPE_DETERMINISITIC:
-            REG_SET_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
-            break;
+    case ECDSA_K_TYPE_DETERMINISITIC:
+        REG_SET_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
+        break;
 #endif
-        default:
-            HAL_ASSERT(false && "Unsupported K type");
-            break;
+    default:
+        HAL_ASSERT(false && "Unsupported K type");
+        break;
     }
 }
 
@@ -257,18 +257,18 @@ static inline void ecdsa_ll_set_k_type(ecdsa_sign_type_t type)
 static inline void ecdsa_ll_set_stage(ecdsa_ll_stage_t stage)
 {
     switch (stage) {
-        case ECDSA_STAGE_START_CALC:
-            REG_SET_BIT(ECDSA_START_REG, ECDSA_START);
-            break;
-        case ECDSA_STAGE_LOAD_DONE:
-            REG_SET_BIT(ECDSA_START_REG, ECDSA_LOAD_DONE);
-            break;
-        case ECDSA_STAGE_GET_DONE:
-            REG_SET_BIT(ECDSA_START_REG, ECDSA_GET_DONE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported state");
-            break;
+    case ECDSA_STAGE_START_CALC:
+        REG_SET_BIT(ECDSA_START_REG, ECDSA_START);
+        break;
+    case ECDSA_STAGE_LOAD_DONE:
+        REG_SET_BIT(ECDSA_START_REG, ECDSA_LOAD_DONE);
+        break;
+    case ECDSA_STAGE_GET_DONE:
+        REG_SET_BIT(ECDSA_START_REG, ECDSA_GET_DONE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported state");
+        break;
     }
 }
 
@@ -280,15 +280,15 @@ static inline void ecdsa_ll_set_stage(ecdsa_ll_stage_t stage)
 static inline void ecdsa_ll_sha_set_type(ecdsa_ll_sha_type_t type)
 {
     switch (type) {
-        case ECDSA_SHA_224:
-            REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 1);
-            break;
-        case ECDSA_SHA_256:
-            REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 2);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported type");
-            break;
+    case ECDSA_SHA_224:
+        REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 1);
+        break;
+    case ECDSA_SHA_256:
+        REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 2);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported type");
+        break;
     }
 }
 
@@ -300,15 +300,15 @@ static inline void ecdsa_ll_sha_set_type(ecdsa_ll_sha_type_t type)
 static inline void ecdsa_ll_sha_set_mode(ecdsa_ll_sha_mode_t mode)
 {
     switch (mode) {
-        case ECDSA_MODE_SHA_START:
-            REG_SET_BIT(ECDSA_SHA_START_REG, ECDSA_SHA_START);
-            break;
-        case ECDSA_MODE_SHA_CONTINUE:
-            REG_SET_BIT(ECDSA_SHA_CONTINUE_REG, ECDSA_SHA_CONTINUE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported type");
-            break;
+    case ECDSA_MODE_SHA_START:
+        REG_SET_BIT(ECDSA_SHA_START_REG, ECDSA_SHA_START);
+        break;
+    case ECDSA_MODE_SHA_CONTINUE:
+        REG_SET_BIT(ECDSA_SHA_CONTINUE_REG, ECDSA_SHA_CONTINUE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported type");
+        break;
     }
 }
 
@@ -335,24 +335,24 @@ static inline void ecdsa_ll_write_param(ecdsa_ll_param_t param, const uint8_t *b
     uint32_t reg;
     uint32_t word;
     switch (param) {
-        case ECDSA_PARAM_R:
-            reg = ECDSA_R_MEM;
-            break;
-        case ECDSA_PARAM_S:
-            reg = ECDSA_S_MEM;
-            break;
-        case ECDSA_PARAM_Z:
-            reg = ECDSA_Z_MEM;
-            break;
-        case ECDSA_PARAM_QAX:
-            reg = ECDSA_QAX_MEM;
-            break;
-        case ECDSA_PARAM_QAY:
-            reg = ECDSA_QAY_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECDSA_PARAM_R:
+        reg = ECDSA_R_MEM;
+        break;
+    case ECDSA_PARAM_S:
+        reg = ECDSA_S_MEM;
+        break;
+    case ECDSA_PARAM_Z:
+        reg = ECDSA_Z_MEM;
+        break;
+    case ECDSA_PARAM_QAX:
+        reg = ECDSA_QAX_MEM;
+        break;
+    case ECDSA_PARAM_QAY:
+        reg = ECDSA_QAY_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     for (int i = 0; i < len; i += 4) {
@@ -372,24 +372,24 @@ static inline void ecdsa_ll_read_param(ecdsa_ll_param_t param, uint8_t *buf, uin
 {
     uint32_t reg;
     switch (param) {
-        case ECDSA_PARAM_R:
-            reg = ECDSA_R_MEM;
-            break;
-        case ECDSA_PARAM_S:
-            reg = ECDSA_S_MEM;
-            break;
-        case ECDSA_PARAM_Z:
-            reg = ECDSA_Z_MEM;
-            break;
-        case ECDSA_PARAM_QAX:
-            reg = ECDSA_QAX_MEM;
-            break;
-        case ECDSA_PARAM_QAY:
-            reg = ECDSA_QAY_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECDSA_PARAM_R:
+        reg = ECDSA_R_MEM;
+        break;
+    case ECDSA_PARAM_S:
+        reg = ECDSA_S_MEM;
+        break;
+    case ECDSA_PARAM_Z:
+        reg = ECDSA_Z_MEM;
+        break;
+    case ECDSA_PARAM_QAX:
+        reg = ECDSA_QAX_MEM;
+        break;
+    case ECDSA_PARAM_QAY:
+        reg = ECDSA_QAY_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     memcpy(buf, (void *)reg, len);
@@ -426,22 +426,22 @@ __attribute__((always_inline)) static inline void ecdsa_ll_set_ecdsa_key_blk(ecd
     uint8_t efuse_blk_high = 0;
 
     switch (curve) {
-        case ECDSA_CURVE_SECP192R1:
-            EFUSE.ecdsa.cfg_ecdsa_p192_blk = efuse_blk;
-            break;
-        case ECDSA_CURVE_SECP256R1:
-            EFUSE.ecdsa.cfg_ecdsa_p256_blk = efuse_blk;
-            break;
-        case ECDSA_CURVE_SECP384R1:
-            // ECDSA-p384 uses two efuse blocks to store the key. These two blocks are stored in a single integer
-            // where the least significant 4 bits store the low key block number and the next 4 more significant bits store the high key block number.
-            HAL_ECDSA_EXTRACT_KEY_BLOCKS(efuse_blk, efuse_blk_high, efuse_blk_low);
-            EFUSE.ecdsa.cfg_ecdsa_p384_h_blk = efuse_blk_high;
-            EFUSE.ecdsa.cfg_ecdsa_p384_l_blk = efuse_blk_low;
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            break;
+    case ECDSA_CURVE_SECP192R1:
+        EFUSE.ecdsa.cfg_ecdsa_p192_blk = efuse_blk;
+        break;
+    case ECDSA_CURVE_SECP256R1:
+        EFUSE.ecdsa.cfg_ecdsa_p256_blk = efuse_blk;
+        break;
+    case ECDSA_CURVE_SECP384R1:
+        // ECDSA-p384 uses two efuse blocks to store the key. These two blocks are stored in a single integer
+        // where the least significant 4 bits store the low key block number and the next 4 more significant bits store the high key block number.
+        HAL_ECDSA_EXTRACT_KEY_BLOCKS(efuse_blk, efuse_blk_high, efuse_blk_low);
+        EFUSE.ecdsa.cfg_ecdsa_p384_h_blk = efuse_blk_high;
+        EFUSE.ecdsa.cfg_ecdsa_p384_l_blk = efuse_blk_low;
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        break;
     }
 }
 
@@ -454,7 +454,6 @@ static inline bool ecdsa_ll_is_supported(void)
     return true;
 }
 
-
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32c5/include/hal/hmac_ll.h

@@ -67,7 +67,7 @@ static inline void hmac_ll_start(void)
  */
 static inline void hmac_ll_config_output(hmac_hal_output_t config)
 {
-    switch(config) {
+    switch (config) {
     case HMAC_OUTPUT_USER:
         REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_UP);
         break;
@@ -124,7 +124,7 @@ static inline void hmac_ll_wait_idle(void)
     uint32_t query;
     do {
         query = REG_READ(HMAC_QUERY_BUSY_REG);
-    } while(query != 0);
+    } while (query != 0);
 }
 
 /**

components/esp_hal_security/esp32c5/include/hal/huk_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -68,30 +68,36 @@ static inline void huk_ll_continue(void)
 /* @bried Enable or Disable the HUK interrupts */
 static inline void huk_ll_configure_interrupt(const esp_huk_interrupt_type_t intr, const bool en)
 {
-    switch(intr) {
-        case ESP_HUK_INT_PREP_DONE:
-                REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PREP_DONE_INT_ENA, en);
-        case ESP_HUK_INT_PROC_DONE:
-                REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PROC_DONE_INT_ENA, en);
-        case ESP_HUK_INT_POST_DONE:
-                REG_SET_FIELD(HUK_INT_ENA_REG, HUK_POST_DONE_INT_ENA, en);
-        default:
-            return;
+    switch (intr) {
+    case ESP_HUK_INT_PREP_DONE:
+        REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PREP_DONE_INT_ENA, en);
+        break;
+    case ESP_HUK_INT_PROC_DONE:
+        REG_SET_FIELD(HUK_INT_ENA_REG, HUK_PROC_DONE_INT_ENA, en);
+        break;
+    case ESP_HUK_INT_POST_DONE:
+        REG_SET_FIELD(HUK_INT_ENA_REG, HUK_POST_DONE_INT_ENA, en);
+        break;
+    default:
+        return;
     }
 }
 
 /* @bried Clear the HUK interrupts */
 static inline void huk_ll_clear_int(const esp_huk_interrupt_type_t intr)
 {
-    switch(intr) {
-        case ESP_HUK_INT_PREP_DONE:
-            REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PREP_DONE_INT_CLR, 1);
-        case ESP_HUK_INT_PROC_DONE:
-            REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PROC_DONE_INT_CLR, 1);
-        case ESP_HUK_INT_POST_DONE:
-            REG_SET_FIELD(HUK_INT_CLR_REG, HUK_POST_DONE_INT_CLR, 1);
-        default:
-            return;
+    switch (intr) {
+    case ESP_HUK_INT_PREP_DONE:
+        REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PREP_DONE_INT_CLR, 1);
+        break;
+    case ESP_HUK_INT_PROC_DONE:
+        REG_SET_FIELD(HUK_INT_CLR_REG, HUK_PROC_DONE_INT_CLR, 1);
+        break;
+    case ESP_HUK_INT_POST_DONE:
+        REG_SET_FIELD(HUK_INT_CLR_REG, HUK_POST_DONE_INT_CLR, 1);
+        break;
+    default:
+        return;
     }
 }
 
@@ -113,7 +119,6 @@ static inline esp_huk_gen_status_t huk_ll_get_gen_status(void)
     return (esp_huk_gen_status_t) REG_GET_FIELD(HUK_STATUS_REG, HUK_STATUS);
 }
 
-
 static inline void __attribute__((always_inline)) huk_ll_recharge_huk_memory(void)
 {
     REG_CLR_BIT(LP_AON_MEM_CTRL_REG, LP_AON_HUK_MEM_FORCE_PD);

components/esp_hal_security/esp32c5/include/hal/key_mgr_ll.h

@@ -115,36 +115,36 @@ static inline void key_mgr_ll_continue(void)
 /* @brief Enable or Disable the KEY_MGR interrupts */
 static inline void key_mgr_ll_configure_interrupt(const esp_key_mgr_interrupt_type_t intr, bool en)
 {
-    switch(intr) {
-        case ESP_KEY_MGR_INT_PREP_DONE:
-            REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_PREP_DONE_INT_ENA, en);
-            break;
-        case ESP_KEY_MGR_INT_PROC_DONE:
-            REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_PROC_DONE_INT_ENA, en);
-            break;
-        case ESP_KEY_MGR_INT_POST_DONE:
-            REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_POST_DONE_INT_ENA, en);
-            break;
-        default:
-            return;
+    switch (intr) {
+    case ESP_KEY_MGR_INT_PREP_DONE:
+        REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_PREP_DONE_INT_ENA, en);
+        break;
+    case ESP_KEY_MGR_INT_PROC_DONE:
+        REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_PROC_DONE_INT_ENA, en);
+        break;
+    case ESP_KEY_MGR_INT_POST_DONE:
+        REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_POST_DONE_INT_ENA, en);
+        break;
+    default:
+        return;
     }
 }
 
 /* @brief Clear the KEY_MGR interrupts */
 static inline void key_mgr_ll_clear_int(const esp_key_mgr_interrupt_type_t intr)
 {
-    switch(intr) {
-        case ESP_KEY_MGR_INT_PREP_DONE:
-            REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_PREP_DONE_INT_CLR, 1);
-            break;
-        case ESP_KEY_MGR_INT_PROC_DONE:
-            REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_PROC_DONE_INT_CLR, 1);
-            break;
-        case ESP_KEY_MGR_INT_POST_DONE:
-            REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_POST_DONE_INT_CLR, 1);
-            break;
-        default:
-            return;
+    switch (intr) {
+    case ESP_KEY_MGR_INT_PREP_DONE:
+        REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_PREP_DONE_INT_CLR, 1);
+        break;
+    case ESP_KEY_MGR_INT_PROC_DONE:
+        REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_PROC_DONE_INT_CLR, 1);
+        break;
+    case ESP_KEY_MGR_INT_POST_DONE:
+        REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_POST_DONE_INT_CLR, 1);
+        break;
+    default:
+        return;
     }
 }
 
@@ -163,72 +163,72 @@ static inline void key_mgr_ll_use_sw_init_key(void)
 static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_usage_t key_usage)
 {
     switch (key_type) {
-        case ESP_KEY_MGR_ECDSA_KEY:
-            if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
-                REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
-            } else {
-                REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
-            }
-            break;
+    case ESP_KEY_MGR_ECDSA_KEY:
+        if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
+            REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
+        } else {
+            REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
+        }
+        break;
 
-        case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
-            if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
-                REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
-            } else {
-                REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
-            }
-            break;
+    case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
+        if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
+            REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
+        } else {
+            REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
+        }
+        break;
 
-        case ESP_KEY_MGR_HMAC_KEY:
-            if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
-                REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
-            } else {
-                REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
-            }
-            break;
+    case ESP_KEY_MGR_HMAC_KEY:
+        if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
+            REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
+        } else {
+            REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
+        }
+        break;
 
-        case ESP_KEY_MGR_DS_KEY:
-            if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
-                REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
-            } else {
-                REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
-            }
-            break;
+    case ESP_KEY_MGR_DS_KEY:
+        if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
+            REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
+        } else {
+            REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
+        }
+        break;
 
-        case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
-            if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
-                REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
-            } else {
-                REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
-            }
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported key type");
-            return;
+    case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
+        if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
+            REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
+        } else {
+            REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
+        }
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported key type");
+        return;
     }
 }
 
 static inline esp_key_mgr_key_usage_t key_mgr_ll_get_key_usage(esp_key_mgr_key_type_t key_type)
 {
     switch (key_type) {
-        case ESP_KEY_MGR_ECDSA_KEY:
-            return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA));
+    case ESP_KEY_MGR_ECDSA_KEY:
+        return (esp_key_mgr_key_usage_t)(REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA));
 
-        case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
-            return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH));
+    case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
+        return (esp_key_mgr_key_usage_t)(REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH));
 
-        case ESP_KEY_MGR_HMAC_KEY:
-            return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC));
+    case ESP_KEY_MGR_HMAC_KEY:
+        return (esp_key_mgr_key_usage_t)(REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC));
 
-        case ESP_KEY_MGR_DS_KEY:
-            return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS));
+    case ESP_KEY_MGR_DS_KEY:
+        return (esp_key_mgr_key_usage_t)(REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS));
 
-        case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
-            return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM));
+    case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
+        return (esp_key_mgr_key_usage_t)(REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM));
 
-        default:
-            HAL_ASSERT(false && "Unsupported key type");
-            return ESP_KEY_MGR_USAGE_INVALID;
+    default:
+        HAL_ASSERT(false && "Unsupported key type");
+        return ESP_KEY_MGR_USAGE_INVALID;
     }
 }
 
@@ -249,30 +249,30 @@ static inline void key_mgr_ll_lock_use_sw_init_key_reg(void)
  */
 static inline void key_mgr_ll_lock_use_efuse_key_reg(esp_key_mgr_key_type_t key_type)
 {
-    switch(key_type) {
-        case ESP_KEY_MGR_ECDSA_KEY:
-            REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA);
-            break;
+    switch (key_type) {
+    case ESP_KEY_MGR_ECDSA_KEY:
+        REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA);
+        break;
 
-        case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
-            REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_FLASH);
-            break;
+    case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
+        REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_FLASH);
+        break;
 
-        case ESP_KEY_MGR_HMAC_KEY:
-            REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_HMAC);
-            break;
+    case ESP_KEY_MGR_HMAC_KEY:
+        REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_HMAC);
+        break;
 
-        case ESP_KEY_MGR_DS_KEY:
-            REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_DS);
-            break;
+    case ESP_KEY_MGR_DS_KEY:
+        REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_DS);
+        break;
 
-        case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
-            REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM);
-            break;
+    case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
+        REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM);
+        break;
 
-        default:
-            HAL_ASSERT(false && "Unsupported key type");
-            return;
+    default:
+        HAL_ASSERT(false && "Unsupported key type");
+        return;
     }
 }
 
@@ -308,47 +308,47 @@ static inline bool key_mgr_ll_is_result_success(void)
 static inline bool key_mgr_ll_is_key_deployment_valid(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_len_t key_len)
 {
     switch (key_type) {
-        case ESP_KEY_MGR_ECDSA_KEY:
-            switch (key_len) {
-                case ESP_KEY_MGR_ECDSA_LEN_192:
-                    return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_192_VLD);
-                case ESP_KEY_MGR_ECDSA_LEN_256:
-                    return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_256_VLD);
-                case ESP_KEY_MGR_ECDSA_LEN_384:
-                    return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_384_VLD);
-                default:
-                    HAL_ASSERT(false && "Unsupported key type");
-                    return 0;
-            }
-        case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
-            switch (key_len) {
-                case ESP_KEY_MGR_XTS_AES_LEN_128:
-                case ESP_KEY_MGR_XTS_AES_LEN_256:
-                    return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_FLASH_VLD);
-                default:
-                    HAL_ASSERT(false && "Unsupported key type");
-                    return 0;
-            }
-
-        case ESP_KEY_MGR_HMAC_KEY:
-            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_HMAC_VLD);
-
-        case ESP_KEY_MGR_DS_KEY:
-            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_DS_VLD);
-
-        case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
-            switch (key_len) {
-                case ESP_KEY_MGR_XTS_AES_LEN_128:
-                case ESP_KEY_MGR_XTS_AES_LEN_256:
-                    return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_PSRAM_VLD);
-                default:
-                    HAL_ASSERT(false && "Unsupported key type");
-                    return 0;
-            }
-
+    case ESP_KEY_MGR_ECDSA_KEY:
+        switch (key_len) {
+        case ESP_KEY_MGR_ECDSA_LEN_192:
+            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_192_VLD);
+        case ESP_KEY_MGR_ECDSA_LEN_256:
+            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_256_VLD);
+        case ESP_KEY_MGR_ECDSA_LEN_384:
+            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_384_VLD);
         default:
-            HAL_ASSERT(false && "Unsupported mode");
+            HAL_ASSERT(false && "Unsupported key type");
             return 0;
+        }
+    case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
+        switch (key_len) {
+        case ESP_KEY_MGR_XTS_AES_LEN_128:
+        case ESP_KEY_MGR_XTS_AES_LEN_256:
+            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_FLASH_VLD);
+        default:
+            HAL_ASSERT(false && "Unsupported key type");
+            return 0;
+        }
+
+    case ESP_KEY_MGR_HMAC_KEY:
+        return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_HMAC_VLD);
+
+    case ESP_KEY_MGR_DS_KEY:
+        return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_DS_VLD);
+
+    case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
+        switch (key_len) {
+        case ESP_KEY_MGR_XTS_AES_LEN_128:
+        case ESP_KEY_MGR_XTS_AES_LEN_256:
+            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_PSRAM_VLD);
+        default:
+            HAL_ASSERT(false && "Unsupported key type");
+            return 0;
+        }
+
+    default:
+        HAL_ASSERT(false && "Unsupported mode");
+        return 0;
     }
 }
 
@@ -382,7 +382,7 @@ static inline void key_mgr_ll_write_assist_info(const uint8_t *assist_info_buf,
  * @input
  * assist_info_buf      Assist info buffer, this should be a writable buffer of size KEY_MGR_ASSIST_INFO_LEN. The buffer must be 32 bit aligned
  */
-static inline void key_mgr_ll_read_assist_info( uint8_t *assist_info_buf)
+static inline void key_mgr_ll_read_assist_info(uint8_t *assist_info_buf)
 {
     memcpy(assist_info_buf, (uint8_t *)KEYMNG_ASSIST_INFO_MEM, KEY_MGR_ASSIST_INFO_LEN);
 }
@@ -429,15 +429,15 @@ static inline void key_mgr_ll_set_xts_aes_key_len(const esp_key_mgr_key_type_t k
     }
 
     switch (key_len) {
-        case ESP_KEY_MGR_XTS_AES_LEN_128:
-            REG_CLR_BIT(KEYMNG_STATIC_REG, key_len_bit_mask);
-            break;
-        case ESP_KEY_MGR_XTS_AES_LEN_256:
-            REG_SET_BIT(KEYMNG_STATIC_REG, key_len_bit_mask);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported key length");
-            return;
+    case ESP_KEY_MGR_XTS_AES_LEN_128:
+        REG_CLR_BIT(KEYMNG_STATIC_REG, key_len_bit_mask);
+        break;
+    case ESP_KEY_MGR_XTS_AES_LEN_256:
+        REG_SET_BIT(KEYMNG_STATIC_REG, key_len_bit_mask);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported key length");
+        return;
     }
 }
 
@@ -456,13 +456,13 @@ static inline esp_key_mgr_key_len_t key_mgr_ll_get_xts_aes_key_len(const esp_key
     }
 
     switch (key_len_bit) {
-        case 0:
-            return ESP_KEY_MGR_XTS_AES_LEN_128;
-        case 1:
-            return ESP_KEY_MGR_XTS_AES_LEN_256;
-        default:
-            HAL_ASSERT(false && "Unsupported key length");
-            return (esp_key_mgr_key_len_t) key_len_bit;
+    case 0:
+        return ESP_KEY_MGR_XTS_AES_LEN_128;
+    case 1:
+        return ESP_KEY_MGR_XTS_AES_LEN_256;
+    default:
+        HAL_ASSERT(false && "Unsupported key length");
+        return (esp_key_mgr_key_len_t) key_len_bit;
     }
 }
 

components/esp_hal_security/esp32c5/include/hal/mpi_ll.h

@@ -20,7 +20,6 @@
 extern "C" {
 #endif
 
-
 /**
  * @brief Enable the bus clock for MPI peripheral module
  *

components/esp_hal_security/esp32c5/include/hal/sha_ll.h

@@ -14,7 +14,6 @@
 extern "C" {
 #endif
 
-
 /**
  * @brief Enable the bus clock for SHA peripheral module
  *

components/esp_hal_security/esp32c6/include/hal/aes_ll.h

@@ -113,7 +113,7 @@ static inline void aes_ll_read_block(void *output)
     for (size_t i = 0; i < AES_BLOCK_WORDS; i++) {
         output_word = REG_READ(AES_TEXT_OUT_0_REG + (i * REG_WIDTH));
         /* Memcpy to avoid potential unaligned access */
-        memcpy( (uint8_t*)output + i * 4, &output_word, sizeof(output_word));
+        memcpy((uint8_t*)output + i * 4, &output_word, sizeof(output_word));
     }
 }
 
@@ -126,7 +126,6 @@ static inline void aes_ll_start_transform(void)
     REG_WRITE(AES_TRIGGER_REG, 1);
 }
 
-
 /**
  * @brief Read state of AES accelerator
  *
@@ -137,7 +136,6 @@ static inline esp_aes_state_t aes_ll_get_state(void)
     return (esp_aes_state_t)REG_READ(AES_STATE_REG);
 }
 
-
 /**
  * @brief Set mode of operation
  *
@@ -190,7 +188,7 @@ static inline void aes_ll_set_iv(const uint8_t *iv)
     uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_MEM);
     uint32_t iv_word;
 
-    for (int i = 0; i < IV_WORDS; i++ ) {
+    for (int i = 0; i < IV_WORDS; i++) {
         /* Memcpy to avoid potential unaligned access */
         memcpy(&iv_word, iv + 4 * i, sizeof(iv_word));
         REG_WRITE(&reg_addr_buf[i], iv_word);
@@ -241,7 +239,6 @@ static inline void aes_ll_interrupt_clear(void)
     REG_WRITE(AES_INT_CLEAR_REG, 1);
 }
 
-
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32c6/include/hal/ds_ll.h

@@ -83,7 +83,7 @@ static inline ds_key_check_t ds_ll_key_error_source(void)
 static inline void ds_ll_configure_iv(const uint32_t *iv)
 {
     for (size_t i = 0; i < (SOC_DS_KEY_PARAM_MD_IV_LENGTH / sizeof(uint32_t)); i++) {
-        REG_WRITE(DS_IV_MEM + (i * 4) , iv[i]);
+        REG_WRITE(DS_IV_MEM + (i * 4), iv[i]);
     }
 }
 
@@ -97,7 +97,7 @@ static inline void ds_ll_write_message(const uint8_t *msg, size_t size)
 {
     memcpy((uint8_t*) DS_X_MEM, msg, size);
     // Fence ensures all memory operations are completed before proceeding further
-    asm volatile ("fence");
+    asm volatile("fence");
 }
 
 /**
@@ -111,20 +111,23 @@ static inline void ds_ll_write_private_key_params(const uint8_t *encrypted_key_p
 
        (note if ETS_DS_MAX_BITS == 4096, this should be the same as copying data->c to hardware in one fragment)
     */
-    typedef struct { uint32_t addr; size_t len; } frag_t;
+    typedef struct {
+        uint32_t addr;
+        size_t len;
+    } frag_t;
     const frag_t frags[] = {
-                            {DS_Y_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_M_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_RB_MEM, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_BOX_MEM, DS_IV_MEM - DS_BOX_MEM},
+        {DS_Y_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_M_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_RB_MEM, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_BOX_MEM, DS_IV_MEM - DS_BOX_MEM},
     };
-    const size_t NUM_FRAGS = sizeof(frags)/sizeof(frag_t);
+    const size_t NUM_FRAGS = sizeof(frags) / sizeof(frag_t);
     const uint8_t *from = encrypted_key_params;
 
     for (int i = 0; i < NUM_FRAGS; i++) {
         memcpy((uint8_t *)frags[i].addr, from, frags[i].len);
         // Fence ensures all memory operations are completed before proceeding further
-        asm volatile ("fence");
+        asm volatile("fence");
         from += frags[i].len;
     }
 }
@@ -150,7 +153,7 @@ static inline void ds_ll_start_sign(void)
 static inline ds_signature_check_t ds_ll_check_signature(void)
 {
     uint32_t result = REG_READ(DS_QUERY_CHECK_REG);
-    switch(result) {
+    switch (result) {
     case 0:
         return DS_SIGNATURE_OK;
     case 1:
@@ -172,7 +175,7 @@ static inline void ds_ll_read_result(uint8_t *result, size_t size)
 {
     memcpy(result, (uint8_t*) DS_Z_MEM, size);
     // Fence ensures all memory operations are completed before proceeding further
-    asm volatile ("fence");
+    asm volatile("fence");
 }
 
 /**

components/esp_hal_security/esp32c6/include/hal/ecc_ll.h

@@ -71,34 +71,34 @@ static inline void ecc_ll_clear_interrupt(void)
 
 static inline void ecc_ll_set_mode(ecc_mode_t mode)
 {
-    switch(mode) {
-        case ECC_MODE_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
-            break;
-        case ECC_MODE_VERIFY:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
-            break;
-        case ECC_MODE_VERIFY_THEN_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported mode");
-            break;
+    switch (mode) {
+    case ECC_MODE_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
+        break;
+    case ECC_MODE_VERIFY:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
+        break;
+    case ECC_MODE_VERIFY_THEN_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported mode");
+        break;
     }
 }
 
 static inline void ecc_ll_set_curve(ecc_curve_t curve)
 {
-    switch(curve) {
-        case ECC_CURVE_SECP256R1:
-            REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
-            break;
-        case ECC_CURVE_SECP192R1:
-            REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    switch (curve) {
+    case ECC_CURVE_SECP256R1:
+        REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
+        break;
+    case ECC_CURVE_SECP192R1:
+        REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
@@ -107,18 +107,18 @@ static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf,
     uint32_t reg;
     uint32_t word;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_MEM;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_MEM;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_MEM;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_MEM;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     for (int i = 0; i < len; i += 4) {
@@ -156,18 +156,18 @@ static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_
 {
     uint32_t reg;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_MEM;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_MEM;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_MEM;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_MEM;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     memcpy(buf, (void *)reg, len);

components/esp_hal_security/esp32c6/include/hal/hmac_ll.h

@@ -67,7 +67,7 @@ static inline void hmac_ll_start(void)
  */
 static inline void hmac_ll_config_output(hmac_hal_output_t config)
 {
-    switch(config) {
+    switch (config) {
     case HMAC_OUTPUT_USER:
         REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_UP);
         break;
@@ -124,7 +124,7 @@ static inline void hmac_ll_wait_idle(void)
     uint32_t query;
     do {
         query = REG_READ(HMAC_QUERY_BUSY_REG);
-    } while(query != 0);
+    } while (query != 0);
 }
 
 /**

components/esp_hal_security/esp32c6/include/hal/mpi_ll.h

@@ -19,7 +19,6 @@
 extern "C" {
 #endif
 
-
 /**
  * @brief Enable the bus clock for MPI peripheral module
  *

components/esp_hal_security/esp32c6/include/hal/sha_ll.h

@@ -170,7 +170,6 @@ static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state
     }
 }
 
-
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32c61/include/hal/ecc_ll.h

@@ -78,73 +78,73 @@ static inline void ecc_ll_clear_interrupt(void)
 
 static inline void ecc_ll_set_mode(ecc_mode_t mode)
 {
-    switch(mode) {
-        case ECC_MODE_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
-            break;
-        case ECC_MODE_VERIFY:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
-            break;
-        case ECC_MODE_VERIFY_THEN_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
-            break;
-        case ECC_MODE_JACOBIAN_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
-            break;
-        case ECC_MODE_POINT_ADD:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5);
-            break;
-        case ECC_MODE_JACOBIAN_POINT_VERIFY:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6);
-            break;
-        case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7);
-            break;
-        case ECC_MODE_MOD_ADD:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8);
-            break;
-        case ECC_MODE_MOD_SUB:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9);
-            break;
-        case ECC_MODE_MOD_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10);
-            break;
-        case ECC_MODE_INVERSE_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported mode");
-            break;
+    switch (mode) {
+    case ECC_MODE_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
+        break;
+    case ECC_MODE_VERIFY:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
+        break;
+    case ECC_MODE_VERIFY_THEN_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
+        break;
+    case ECC_MODE_JACOBIAN_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
+        break;
+    case ECC_MODE_POINT_ADD:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5);
+        break;
+    case ECC_MODE_JACOBIAN_POINT_VERIFY:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6);
+        break;
+    case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7);
+        break;
+    case ECC_MODE_MOD_ADD:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8);
+        break;
+    case ECC_MODE_MOD_SUB:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9);
+        break;
+    case ECC_MODE_MOD_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10);
+        break;
+    case ECC_MODE_INVERSE_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported mode");
+        break;
     }
 }
 
 static inline void ecc_ll_set_curve(ecc_curve_t curve)
 {
-    switch(curve) {
-        case ECC_CURVE_SECP256R1:
-            REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
-            break;
-        case ECC_CURVE_SECP192R1:
-            REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    switch (curve) {
+    case ECC_CURVE_SECP256R1:
+        REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
+        break;
+    case ECC_CURVE_SECP192R1:
+        REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
 static inline void ecc_ll_set_mod_base(ecc_mod_base_t base)
 {
-    switch(base) {
-        case ECC_MOD_N:
-            REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
-            break;
-        case ECC_MOD_P:
-            REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    switch (base) {
+    case ECC_MOD_N:
+        REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
+        break;
+    case ECC_MOD_P:
+        REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
@@ -162,27 +162,27 @@ static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf,
     uint32_t reg;
     uint32_t word;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_MEM;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_MEM;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_MEM;
-            break;
-        case ECC_PARAM_QX:
-            reg = ECC_MULT_QX_MEM;
-            break;
-        case ECC_PARAM_QY:
-            reg = ECC_MULT_QY_MEM;
-            break;
-        case ECC_PARAM_QZ:
-            reg = ECC_MULT_QZ_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_MEM;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_MEM;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_MEM;
+        break;
+    case ECC_PARAM_QX:
+        reg = ECC_MULT_QX_MEM;
+        break;
+    case ECC_PARAM_QY:
+        reg = ECC_MULT_QY_MEM;
+        break;
+    case ECC_PARAM_QZ:
+        reg = ECC_MULT_QZ_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     for (int i = 0; i < len; i += 4) {
@@ -225,27 +225,27 @@ static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_
 {
     uint32_t reg;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_MEM;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_MEM;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_MEM;
-            break;
-        case ECC_PARAM_QX:
-            reg = ECC_MULT_QX_MEM;
-            break;
-        case ECC_PARAM_QY:
-            reg = ECC_MULT_QY_MEM;
-            break;
-        case ECC_PARAM_QZ:
-            reg = ECC_MULT_QZ_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_MEM;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_MEM;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_MEM;
+        break;
+    case ECC_PARAM_QX:
+        reg = ECC_MULT_QX_MEM;
+        break;
+    case ECC_PARAM_QY:
+        reg = ECC_MULT_QY_MEM;
+        break;
+    case ECC_PARAM_QZ:
+        reg = ECC_MULT_QZ_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     memcpy(buf, (void *)reg, len);

components/esp_hal_security/esp32c61/include/hal/ecdsa_ll.h

@@ -112,15 +112,15 @@ static inline void ecdsa_ll_reset_register(void)
 static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_CALC_DONE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 1);
-            break;
-        case ECDSA_INT_SHA_RELEASE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 1);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported interrupt type");
-            break;
+    case ECDSA_INT_CALC_DONE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 1);
+        break;
+    case ECDSA_INT_SHA_RELEASE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 1);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported interrupt type");
+        break;
     }
 }
 
@@ -132,15 +132,15 @@ static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_disable_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_CALC_DONE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 0);
-            break;
-        case ECDSA_INT_SHA_RELEASE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 0);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported interrupt type");
-            break;
+    case ECDSA_INT_CALC_DONE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 0);
+        break;
+    case ECDSA_INT_SHA_RELEASE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 0);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported interrupt type");
+        break;
     }
 }
 
@@ -152,15 +152,15 @@ static inline void ecdsa_ll_disable_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_clear_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_CALC_DONE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_CLR, 1);
-            break;
-        case ECDSA_INT_SHA_RELEASE:
-            REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_SHA_RELEASE_INT_CLR, 1);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported interrupt type");
-            break;
+    case ECDSA_INT_CALC_DONE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_CLR, 1);
+        break;
+    case ECDSA_INT_SHA_RELEASE:
+        REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_SHA_RELEASE_INT_CLR, 1);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported interrupt type");
+        break;
     }
 }
 
@@ -172,18 +172,18 @@ static inline void ecdsa_ll_clear_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_set_mode(ecdsa_mode_t mode)
 {
     switch (mode) {
-        case ECDSA_MODE_SIGN_VERIFY:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 0);
-            break;
-        case ECDSA_MODE_SIGN_GEN:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 1);
-            break;
-        case ECDSA_MODE_EXPORT_PUBKEY:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 2);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported mode");
-            break;
+    case ECDSA_MODE_SIGN_VERIFY:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 0);
+        break;
+    case ECDSA_MODE_SIGN_GEN:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 1);
+        break;
+    case ECDSA_MODE_EXPORT_PUBKEY:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 2);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported mode");
+        break;
     }
 }
 
@@ -195,15 +195,15 @@ static inline void ecdsa_ll_set_mode(ecdsa_mode_t mode)
 static inline void ecdsa_ll_set_curve(ecdsa_curve_t curve)
 {
     switch (curve) {
-        case ECDSA_CURVE_SECP256R1:
-            REG_SET_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE);
-            break;
-        case ECDSA_CURVE_SECP192R1:
-            REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    case ECDSA_CURVE_SECP256R1:
+        REG_SET_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE);
+        break;
+    case ECDSA_CURVE_SECP192R1:
+        REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
@@ -215,15 +215,15 @@ static inline void ecdsa_ll_set_curve(ecdsa_curve_t curve)
 static inline void ecdsa_ll_set_z_mode(ecdsa_ll_sha_mode_t mode)
 {
     switch (mode) {
-        case ECDSA_Z_USE_SHA_PERI:
-            REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
-            break;
-        case ECDSA_Z_USER_PROVIDED:
-            REG_SET_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            break;
+    case ECDSA_Z_USE_SHA_PERI:
+        REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
+        break;
+    case ECDSA_Z_USER_PROVIDED:
+        REG_SET_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        break;
     }
 }
 
@@ -235,15 +235,15 @@ static inline void ecdsa_ll_set_z_mode(ecdsa_ll_sha_mode_t mode)
 static inline void ecdsa_ll_set_k_type(ecdsa_sign_type_t type)
 {
     switch (type) {
-        case ECDSA_K_TYPE_TRNG:
-            REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
-            break;
-        case ECDSA_K_TYPE_DETERMINISITIC:
-            REG_SET_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported K type");
-            break;
+    case ECDSA_K_TYPE_TRNG:
+        REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
+        break;
+    case ECDSA_K_TYPE_DETERMINISITIC:
+        REG_SET_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported K type");
+        break;
     }
 }
 
@@ -265,18 +265,18 @@ static inline void ecdsa_ll_set_deterministic_loop(uint16_t loop_number)
 static inline void ecdsa_ll_set_stage(ecdsa_ll_stage_t stage)
 {
     switch (stage) {
-        case ECDSA_STAGE_START_CALC:
-            REG_SET_BIT(ECDSA_START_REG, ECDSA_START);
-            break;
-        case ECDSA_STAGE_LOAD_DONE:
-            REG_SET_BIT(ECDSA_START_REG, ECDSA_LOAD_DONE);
-            break;
-        case ECDSA_STAGE_GET_DONE:
-            REG_SET_BIT(ECDSA_START_REG, ECDSA_GET_DONE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported state");
-            break;
+    case ECDSA_STAGE_START_CALC:
+        REG_SET_BIT(ECDSA_START_REG, ECDSA_START);
+        break;
+    case ECDSA_STAGE_LOAD_DONE:
+        REG_SET_BIT(ECDSA_START_REG, ECDSA_LOAD_DONE);
+        break;
+    case ECDSA_STAGE_GET_DONE:
+        REG_SET_BIT(ECDSA_START_REG, ECDSA_GET_DONE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported state");
+        break;
     }
 }
 
@@ -288,15 +288,15 @@ static inline void ecdsa_ll_set_stage(ecdsa_ll_stage_t stage)
 static inline void ecdsa_ll_sha_set_type(ecdsa_ll_sha_type_t type)
 {
     switch (type) {
-        case ECDSA_SHA_224:
-            REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 1);
-            break;
-        case ECDSA_SHA_256:
-            REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 2);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported type");
-            break;
+    case ECDSA_SHA_224:
+        REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 1);
+        break;
+    case ECDSA_SHA_256:
+        REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 2);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported type");
+        break;
     }
 }
 
@@ -308,15 +308,15 @@ static inline void ecdsa_ll_sha_set_type(ecdsa_ll_sha_type_t type)
 static inline void ecdsa_ll_sha_set_mode(ecdsa_ll_sha_mode_t mode)
 {
     switch (mode) {
-        case ECDSA_MODE_SHA_START:
-            REG_SET_BIT(ECDSA_SHA_START_REG, ECDSA_SHA_START);
-            break;
-        case ECDSA_MODE_SHA_CONTINUE:
-            REG_SET_BIT(ECDSA_SHA_CONTINUE_REG, ECDSA_SHA_CONTINUE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported type");
-            break;
+    case ECDSA_MODE_SHA_START:
+        REG_SET_BIT(ECDSA_SHA_START_REG, ECDSA_SHA_START);
+        break;
+    case ECDSA_MODE_SHA_CONTINUE:
+        REG_SET_BIT(ECDSA_SHA_CONTINUE_REG, ECDSA_SHA_CONTINUE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported type");
+        break;
     }
 }
 
@@ -343,24 +343,24 @@ static inline void ecdsa_ll_write_param(ecdsa_ll_param_t param, const uint8_t *b
     uint32_t reg;
     uint32_t word;
     switch (param) {
-        case ECDSA_PARAM_R:
-            reg = ECDSA_R_MEM;
-            break;
-        case ECDSA_PARAM_S:
-            reg = ECDSA_S_MEM;
-            break;
-        case ECDSA_PARAM_Z:
-            reg = ECDSA_Z_MEM;
-            break;
-        case ECDSA_PARAM_QAX:
-            reg = ECDSA_QAX_MEM;
-            break;
-        case ECDSA_PARAM_QAY:
-            reg = ECDSA_QAY_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECDSA_PARAM_R:
+        reg = ECDSA_R_MEM;
+        break;
+    case ECDSA_PARAM_S:
+        reg = ECDSA_S_MEM;
+        break;
+    case ECDSA_PARAM_Z:
+        reg = ECDSA_Z_MEM;
+        break;
+    case ECDSA_PARAM_QAX:
+        reg = ECDSA_QAX_MEM;
+        break;
+    case ECDSA_PARAM_QAY:
+        reg = ECDSA_QAY_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     for (int i = 0; i < len; i += 4) {
@@ -380,24 +380,24 @@ static inline void ecdsa_ll_read_param(ecdsa_ll_param_t param, uint8_t *buf, uin
 {
     uint32_t reg;
     switch (param) {
-        case ECDSA_PARAM_R:
-            reg = ECDSA_R_MEM;
-            break;
-        case ECDSA_PARAM_S:
-            reg = ECDSA_S_MEM;
-            break;
-        case ECDSA_PARAM_Z:
-            reg = ECDSA_Z_MEM;
-            break;
-        case ECDSA_PARAM_QAX:
-            reg = ECDSA_QAX_MEM;
-            break;
-        case ECDSA_PARAM_QAY:
-            reg = ECDSA_QAY_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECDSA_PARAM_R:
+        reg = ECDSA_R_MEM;
+        break;
+    case ECDSA_PARAM_S:
+        reg = ECDSA_S_MEM;
+        break;
+    case ECDSA_PARAM_Z:
+        reg = ECDSA_Z_MEM;
+        break;
+    case ECDSA_PARAM_QAX:
+        reg = ECDSA_QAX_MEM;
+        break;
+    case ECDSA_PARAM_QAY:
+        reg = ECDSA_QAY_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     memcpy(buf, (void *)reg, len);

components/esp_hal_security/esp32c61/include/hal/sha_ll.h

@@ -14,7 +14,6 @@
 extern "C" {
 #endif
 
-
 /**
  * @brief Enable the bus clock for SHA peripheral module
  *
@@ -172,7 +171,6 @@ static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state
     }
 }
 
-
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32h2/include/hal/aes_ll.h

@@ -116,7 +116,7 @@ static inline void aes_ll_read_block(void *output)
     for (size_t i = 0; i < AES_BLOCK_WORDS; i++) {
         output_word = REG_READ(AES_TEXT_OUT_0_REG + (i * REG_WIDTH));
         /* Memcpy to avoid potential unaligned access */
-        memcpy( (uint8_t*)output + i * 4, &output_word, sizeof(output_word));
+        memcpy((uint8_t*)output + i * 4, &output_word, sizeof(output_word));
     }
 }
 
@@ -129,7 +129,6 @@ static inline void aes_ll_start_transform(void)
     REG_WRITE(AES_TRIGGER_REG, 1);
 }
 
-
 /**
  * @brief Read state of AES accelerator
  *
@@ -140,7 +139,6 @@ static inline esp_aes_state_t aes_ll_get_state(void)
     return (esp_aes_state_t)REG_READ(AES_STATE_REG);
 }
 
-
 /**
  * @brief Set mode of operation
  *
@@ -193,7 +191,7 @@ static inline void aes_ll_set_iv(const uint8_t *iv)
     uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_MEM);
     uint32_t iv_word;
 
-    for (int i = 0; i < IV_WORDS; i++ ) {
+    for (int i = 0; i < IV_WORDS; i++) {
         /* Memcpy to avoid potential unaligned access */
         memcpy(&iv_word, iv + 4 * i, sizeof(iv_word));
         REG_WRITE(&reg_addr_buf[i], iv_word);

components/esp_hal_security/esp32h2/include/hal/ds_ll.h

@@ -20,7 +20,6 @@
 #include "soc/pcr_struct.h"
 #include "hal/ds_types.h"
 
-
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -84,7 +83,7 @@ static inline ds_key_check_t ds_ll_key_error_source(void)
 static inline void ds_ll_configure_iv(const uint32_t *iv)
 {
     for (size_t i = 0; i < (SOC_DS_KEY_PARAM_MD_IV_LENGTH / sizeof(uint32_t)); i++) {
-        REG_WRITE(DS_IV_MEM + (i * 4) , iv[i]);
+        REG_WRITE(DS_IV_MEM + (i * 4), iv[i]);
     }
 }
 
@@ -98,7 +97,7 @@ static inline void ds_ll_write_message(const uint8_t *msg, size_t size)
 {
     memcpy((uint8_t*) DS_X_MEM, msg, size);
     // Fence ensures all memory operations are completed before proceeding further
-    asm volatile ("fence");
+    asm volatile("fence");
 }
 
 /**
@@ -112,20 +111,23 @@ static inline void ds_ll_write_private_key_params(const uint8_t *encrypted_key_p
 
        (note if ETS_DS_MAX_BITS == 4096, this should be the same as copying data->c to hardware in one fragment)
     */
-    typedef struct { uint32_t addr; size_t len; } frag_t;
+    typedef struct {
+        uint32_t addr;
+        size_t len;
+    } frag_t;
     const frag_t frags[] = {
-                            {DS_Y_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_M_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_RB_MEM, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_BOX_MEM, DS_IV_MEM - DS_BOX_MEM},
+        {DS_Y_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_M_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_RB_MEM, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_BOX_MEM, DS_IV_MEM - DS_BOX_MEM},
     };
-    const size_t NUM_FRAGS = sizeof(frags)/sizeof(frag_t);
+    const size_t NUM_FRAGS = sizeof(frags) / sizeof(frag_t);
     const uint8_t *from = encrypted_key_params;
 
     for (int i = 0; i < NUM_FRAGS; i++) {
         memcpy((uint8_t *)frags[i].addr, from, frags[i].len);
         // Fence ensures all memory operations are completed before proceeding further
-        asm volatile ("fence");
+        asm volatile("fence");
         from += frags[i].len;
     }
 }
@@ -151,7 +153,7 @@ static inline void ds_ll_start_sign(void)
 static inline ds_signature_check_t ds_ll_check_signature(void)
 {
     uint32_t result = REG_READ(DS_QUERY_CHECK_REG);
-    switch(result) {
+    switch (result) {
     case 0:
         return DS_SIGNATURE_OK;
     case 1:
@@ -173,7 +175,7 @@ static inline void ds_ll_read_result(uint8_t *result, size_t size)
 {
     memcpy(result, (uint8_t*) DS_Z_MEM, size);
     // Fence ensures all memory operations are completed before proceeding further
-    asm volatile ("fence");
+    asm volatile("fence");
 }
 
 /**

components/esp_hal_security/esp32h2/include/hal/ecc_ll.h

@@ -79,73 +79,73 @@ static inline void ecc_ll_clear_interrupt(void)
 
 static inline void ecc_ll_set_mode(ecc_mode_t mode)
 {
-    switch(mode) {
-        case ECC_MODE_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
-            break;
-        case ECC_MODE_VERIFY:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
-            break;
-        case ECC_MODE_VERIFY_THEN_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
-            break;
-        case ECC_MODE_JACOBIAN_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
-            break;
-        case ECC_MODE_POINT_ADD:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5);
-            break;
-        case ECC_MODE_JACOBIAN_POINT_VERIFY:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6);
-            break;
-        case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7);
-            break;
-        case ECC_MODE_MOD_ADD:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8);
-            break;
-        case ECC_MODE_MOD_SUB:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9);
-            break;
-        case ECC_MODE_MOD_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10);
-            break;
-        case ECC_MODE_INVERSE_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported mode");
-            break;
+    switch (mode) {
+    case ECC_MODE_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
+        break;
+    case ECC_MODE_VERIFY:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
+        break;
+    case ECC_MODE_VERIFY_THEN_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
+        break;
+    case ECC_MODE_JACOBIAN_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
+        break;
+    case ECC_MODE_POINT_ADD:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5);
+        break;
+    case ECC_MODE_JACOBIAN_POINT_VERIFY:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6);
+        break;
+    case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7);
+        break;
+    case ECC_MODE_MOD_ADD:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8);
+        break;
+    case ECC_MODE_MOD_SUB:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9);
+        break;
+    case ECC_MODE_MOD_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10);
+        break;
+    case ECC_MODE_INVERSE_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported mode");
+        break;
     }
 }
 
 static inline void ecc_ll_set_curve(ecc_curve_t curve)
 {
-    switch(curve) {
-        case ECC_CURVE_SECP256R1:
-            REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
-            break;
-        case ECC_CURVE_SECP192R1:
-            REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    switch (curve) {
+    case ECC_CURVE_SECP256R1:
+        REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
+        break;
+    case ECC_CURVE_SECP192R1:
+        REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
 static inline void ecc_ll_set_mod_base(ecc_mod_base_t base)
 {
-    switch(base) {
-        case ECC_MOD_N:
-            REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
-            break;
-        case ECC_MOD_P:
-            REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    switch (base) {
+    case ECC_MOD_N:
+        REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
+        break;
+    case ECC_MOD_P:
+        REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
@@ -154,27 +154,27 @@ static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf,
     uint32_t reg;
     uint32_t word;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_MEM;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_MEM;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_MEM;
-            break;
-        case ECC_PARAM_QX:
-            reg = ECC_MULT_QX_MEM;
-            break;
-        case ECC_PARAM_QY:
-            reg = ECC_MULT_QY_MEM;
-            break;
-        case ECC_PARAM_QZ:
-            reg = ECC_MULT_QZ_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_MEM;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_MEM;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_MEM;
+        break;
+    case ECC_PARAM_QX:
+        reg = ECC_MULT_QX_MEM;
+        break;
+    case ECC_PARAM_QY:
+        reg = ECC_MULT_QY_MEM;
+        break;
+    case ECC_PARAM_QZ:
+        reg = ECC_MULT_QZ_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     for (int i = 0; i < len; i += 4) {
@@ -216,7 +216,7 @@ static inline ecc_mod_base_t ecc_ll_get_mod_base(void)
 static inline void ecc_ll_enable_constant_time_point_mul(bool enable)
 {
     // ECC constant time point multiplication is supported only on rev 1.2 and above
-    if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102)){
+    if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102)) {
         if (enable) {
             REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_SECURITY_MODE);
         } else {
@@ -229,27 +229,27 @@ static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_
 {
     uint32_t reg;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_MEM;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_MEM;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_MEM;
-            break;
-        case ECC_PARAM_QX:
-            reg = ECC_MULT_QX_MEM;
-            break;
-        case ECC_PARAM_QY:
-            reg = ECC_MULT_QY_MEM;
-            break;
-        case ECC_PARAM_QZ:
-            reg = ECC_MULT_QZ_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_MEM;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_MEM;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_MEM;
+        break;
+    case ECC_PARAM_QX:
+        reg = ECC_MULT_QX_MEM;
+        break;
+    case ECC_PARAM_QY:
+        reg = ECC_MULT_QY_MEM;
+        break;
+    case ECC_PARAM_QZ:
+        reg = ECC_MULT_QZ_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     memcpy(buf, (void *)reg, len);

components/esp_hal_security/esp32h2/include/hal/ecdsa_ll.h

@@ -100,15 +100,15 @@ static inline void ecdsa_ll_reset_register(void)
 static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_PREP_DONE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 1);
-            break;
-        case ECDSA_INT_SHA_RELEASE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 1);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported interrupt type");
-            break;
+    case ECDSA_INT_PREP_DONE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 1);
+        break;
+    case ECDSA_INT_SHA_RELEASE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 1);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported interrupt type");
+        break;
     }
 }
 
@@ -120,15 +120,15 @@ static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_disable_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_PREP_DONE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 0);
-            break;
-        case ECDSA_INT_SHA_RELEASE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 0);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported interrupt type");
-            break;
+    case ECDSA_INT_PREP_DONE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 0);
+        break;
+    case ECDSA_INT_SHA_RELEASE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 0);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported interrupt type");
+        break;
     }
 }
 
@@ -140,15 +140,15 @@ static inline void ecdsa_ll_disable_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_clear_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_PREP_DONE:
-            REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_PREP_DONE_INT_CLR, 1);
-            break;
-        case ECDSA_INT_SHA_RELEASE:
-            REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_SHA_RELEASE_INT_CLR, 1);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported interrupt type");
-            break;
+    case ECDSA_INT_PREP_DONE:
+        REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_PREP_DONE_INT_CLR, 1);
+        break;
+    case ECDSA_INT_SHA_RELEASE:
+        REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_SHA_RELEASE_INT_CLR, 1);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported interrupt type");
+        break;
     }
 }
 
@@ -160,15 +160,15 @@ static inline void ecdsa_ll_clear_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_set_mode(ecdsa_mode_t mode)
 {
     switch (mode) {
-        case ECDSA_MODE_SIGN_VERIFY:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 0);
-            break;
-        case ECDSA_MODE_SIGN_GEN:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 1);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported mode");
-            break;
+    case ECDSA_MODE_SIGN_VERIFY:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 0);
+        break;
+    case ECDSA_MODE_SIGN_GEN:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 1);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported mode");
+        break;
     }
 }
 
@@ -180,15 +180,15 @@ static inline void ecdsa_ll_set_mode(ecdsa_mode_t mode)
 static inline void ecdsa_ll_set_curve(ecdsa_curve_t curve)
 {
     switch (curve) {
-        case ECDSA_CURVE_SECP256R1:
-            REG_SET_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE);
-            break;
-        case ECDSA_CURVE_SECP192R1:
-            REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    case ECDSA_CURVE_SECP256R1:
+        REG_SET_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE);
+        break;
+    case ECDSA_CURVE_SECP192R1:
+        REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
@@ -200,15 +200,15 @@ static inline void ecdsa_ll_set_curve(ecdsa_curve_t curve)
 static inline void ecdsa_ll_set_z_mode(ecdsa_ll_sha_mode_t mode)
 {
     switch (mode) {
-        case ECDSA_Z_USE_SHA_PERI:
-            REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
-            break;
-        case ECDSA_Z_USER_PROVIDED:
-            REG_SET_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            break;
+    case ECDSA_Z_USE_SHA_PERI:
+        REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
+        break;
+    case ECDSA_Z_USER_PROVIDED:
+        REG_SET_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        break;
     }
 }
 
@@ -220,15 +220,15 @@ static inline void ecdsa_ll_set_z_mode(ecdsa_ll_sha_mode_t mode)
 static inline void ecdsa_ll_set_k_type(ecdsa_sign_type_t type)
 {
     switch (type) {
-        case ECDSA_K_TYPE_TRNG:
-            REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
-            break;
-        case ECDSA_K_TYPE_DETERMINISITIC:
-            REG_SET_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported K type");
-            break;
+    case ECDSA_K_TYPE_TRNG:
+        REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
+        break;
+    case ECDSA_K_TYPE_DETERMINISITIC:
+        REG_SET_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported K type");
+        break;
     }
 }
 
@@ -240,18 +240,18 @@ static inline void ecdsa_ll_set_k_type(ecdsa_sign_type_t type)
 static inline void ecdsa_ll_set_stage(ecdsa_ll_stage_t stage)
 {
     switch (stage) {
-        case ECDSA_STAGE_START_CALC:
-            REG_SET_BIT(ECDSA_START_REG, ECDSA_START);
-            break;
-        case ECDSA_STAGE_LOAD_DONE:
-            REG_SET_BIT(ECDSA_START_REG, ECDSA_LOAD_DONE);
-            break;
-        case ECDSA_STAGE_GET_DONE:
-            REG_SET_BIT(ECDSA_START_REG, ECDSA_GET_DONE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported state");
-            break;
+    case ECDSA_STAGE_START_CALC:
+        REG_SET_BIT(ECDSA_START_REG, ECDSA_START);
+        break;
+    case ECDSA_STAGE_LOAD_DONE:
+        REG_SET_BIT(ECDSA_START_REG, ECDSA_LOAD_DONE);
+        break;
+    case ECDSA_STAGE_GET_DONE:
+        REG_SET_BIT(ECDSA_START_REG, ECDSA_GET_DONE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported state");
+        break;
     }
 }
 
@@ -273,15 +273,15 @@ static inline ecdsa_ll_state_t ecdsa_ll_get_state(void)
 static inline void ecdsa_ll_sha_set_type(ecdsa_ll_sha_type_t type)
 {
     switch (type) {
-        case ECDSA_SHA_224:
-            REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 1);
-            break;
-        case ECDSA_SHA_256:
-            REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 2);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported type");
-            break;
+    case ECDSA_SHA_224:
+        REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 1);
+        break;
+    case ECDSA_SHA_256:
+        REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 2);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported type");
+        break;
     }
 }
 
@@ -293,15 +293,15 @@ static inline void ecdsa_ll_sha_set_type(ecdsa_ll_sha_type_t type)
 static inline void ecdsa_ll_sha_set_mode(ecdsa_ll_sha_mode_t mode)
 {
     switch (mode) {
-        case ECDSA_MODE_SHA_START:
-            REG_SET_BIT(ECDSA_SHA_START_REG, ECDSA_SHA_START);
-            break;
-        case ECDSA_MODE_SHA_CONTINUE:
-            REG_SET_BIT(ECDSA_SHA_CONTINUE_REG, ECDSA_SHA_CONTINUE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported type");
-            break;
+    case ECDSA_MODE_SHA_START:
+        REG_SET_BIT(ECDSA_SHA_START_REG, ECDSA_SHA_START);
+        break;
+    case ECDSA_MODE_SHA_CONTINUE:
+        REG_SET_BIT(ECDSA_SHA_CONTINUE_REG, ECDSA_SHA_CONTINUE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported type");
+        break;
     }
 }
 
@@ -328,24 +328,24 @@ static inline void ecdsa_ll_write_param(ecdsa_ll_param_t param, const uint8_t *b
     uint32_t reg;
     uint32_t word;
     switch (param) {
-        case ECDSA_PARAM_R:
-            reg = ECDSA_R_MEM;
-            break;
-        case ECDSA_PARAM_S:
-            reg = ECDSA_S_MEM;
-            break;
-        case ECDSA_PARAM_Z:
-            reg = ECDSA_Z_MEM;
-            break;
-        case ECDSA_PARAM_QAX:
-            reg = ECDSA_QAX_MEM;
-            break;
-        case ECDSA_PARAM_QAY:
-            reg = ECDSA_QAY_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECDSA_PARAM_R:
+        reg = ECDSA_R_MEM;
+        break;
+    case ECDSA_PARAM_S:
+        reg = ECDSA_S_MEM;
+        break;
+    case ECDSA_PARAM_Z:
+        reg = ECDSA_Z_MEM;
+        break;
+    case ECDSA_PARAM_QAX:
+        reg = ECDSA_QAX_MEM;
+        break;
+    case ECDSA_PARAM_QAY:
+        reg = ECDSA_QAY_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     for (int i = 0; i < len; i += 4) {
@@ -365,24 +365,24 @@ static inline void ecdsa_ll_read_param(ecdsa_ll_param_t param, uint8_t *buf, uin
 {
     uint32_t reg;
     switch (param) {
-        case ECDSA_PARAM_R:
-            reg = ECDSA_R_MEM;
-            break;
-        case ECDSA_PARAM_S:
-            reg = ECDSA_S_MEM;
-            break;
-        case ECDSA_PARAM_Z:
-            reg = ECDSA_Z_MEM;
-            break;
-        case ECDSA_PARAM_QAX:
-            reg = ECDSA_QAX_MEM;
-            break;
-        case ECDSA_PARAM_QAY:
-            reg = ECDSA_QAY_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECDSA_PARAM_R:
+        reg = ECDSA_R_MEM;
+        break;
+    case ECDSA_PARAM_S:
+        reg = ECDSA_S_MEM;
+        break;
+    case ECDSA_PARAM_Z:
+        reg = ECDSA_Z_MEM;
+        break;
+    case ECDSA_PARAM_QAX:
+        reg = ECDSA_QAX_MEM;
+        break;
+    case ECDSA_PARAM_QAY:
+        reg = ECDSA_QAY_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     memcpy(buf, (void *)reg, len);

components/esp_hal_security/esp32h2/include/hal/hmac_ll.h

@@ -67,7 +67,7 @@ static inline void hmac_ll_start(void)
  */
 static inline void hmac_ll_config_output(hmac_hal_output_t config)
 {
-    switch(config) {
+    switch (config) {
     case HMAC_OUTPUT_USER:
         REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_UP);
         break;
@@ -124,7 +124,7 @@ static inline void hmac_ll_wait_idle(void)
     uint32_t query;
     do {
         query = REG_READ(HMAC_QUERY_BUSY_REG);
-    } while(query != 0);
+    } while (query != 0);
 }
 
 /**

components/esp_hal_security/esp32h2/include/hal/mpi_ll.h

@@ -19,7 +19,6 @@
 extern "C" {
 #endif
 
-
 /**
  * @brief Enable the bus clock for MPI peripheral module
  *

components/esp_hal_security/esp32h2/include/hal/sha_ll.h

@@ -171,7 +171,6 @@ static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state
     }
 }
 
-
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32h21/include/hal/aes_ll.h

@@ -113,7 +113,7 @@ static inline void aes_ll_read_block(void *output)
     for (size_t i = 0; i < AES_BLOCK_WORDS; i++) {
         output_word = REG_READ(AES_TEXT_OUT_0_REG + (i * REG_WIDTH));
         /* Memcpy to avoid potential unaligned access */
-        memcpy( (uint8_t*)output + i * 4, &output_word, sizeof(output_word));
+        memcpy((uint8_t*)output + i * 4, &output_word, sizeof(output_word));
     }
 }
 
@@ -126,7 +126,6 @@ static inline void aes_ll_start_transform(void)
     REG_WRITE(AES_TRIGGER_REG, 1);
 }
 
-
 /**
  * @brief Read state of AES accelerator
  *
@@ -137,7 +136,6 @@ static inline esp_aes_state_t aes_ll_get_state(void)
     return (esp_aes_state_t)REG_READ(AES_STATE_REG);
 }
 
-
 /**
  * @brief Set mode of operation
  *
@@ -190,7 +188,7 @@ static inline void aes_ll_set_iv(const uint8_t *iv)
     uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_MEM);
     uint32_t iv_word;
 
-    for (int i = 0; i < IV_WORDS; i++ ) {
+    for (int i = 0; i < IV_WORDS; i++) {
         /* Memcpy to avoid potential unaligned access */
         memcpy(&iv_word, iv + 4 * i, sizeof(iv_word));
         REG_WRITE(&reg_addr_buf[i], iv_word);

components/esp_hal_security/esp32h21/include/hal/ds_ll.h

@@ -83,7 +83,7 @@ static inline ds_key_check_t ds_ll_key_error_source(void)
 static inline void ds_ll_configure_iv(const uint32_t *iv)
 {
     for (size_t i = 0; i < (SOC_DS_KEY_PARAM_MD_IV_LENGTH / sizeof(uint32_t)); i++) {
-        REG_WRITE(DS_IV_MEM + (i * 4) , iv[i]);
+        REG_WRITE(DS_IV_MEM + (i * 4), iv[i]);
     }
 }
 
@@ -97,7 +97,7 @@ static inline void ds_ll_write_message(const uint8_t *msg, size_t size)
 {
     memcpy((uint8_t*) DS_X_MEM, msg, size);
     // Fence ensures all memory operations are completed before proceeding further
-    asm volatile ("fence");
+    asm volatile("fence");
 }
 
 /**
@@ -111,20 +111,23 @@ static inline void ds_ll_write_private_key_params(const uint8_t *encrypted_key_p
 
        (note if ETS_DS_MAX_BITS == 4096, this should be the same as copying data->c to hardware in one fragment)
     */
-    typedef struct { uint32_t addr; size_t len; } frag_t;
+    typedef struct {
+        uint32_t addr;
+        size_t len;
+    } frag_t;
     const frag_t frags[] = {
-                            {DS_Y_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_M_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_RB_MEM, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_BOX_MEM, DS_IV_MEM - DS_BOX_MEM},
+        {DS_Y_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_M_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_RB_MEM, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_BOX_MEM, DS_IV_MEM - DS_BOX_MEM},
     };
-    const size_t NUM_FRAGS = sizeof(frags)/sizeof(frag_t);
+    const size_t NUM_FRAGS = sizeof(frags) / sizeof(frag_t);
     const uint8_t *from = encrypted_key_params;
 
     for (int i = 0; i < NUM_FRAGS; i++) {
         memcpy((uint8_t *)frags[i].addr, from, frags[i].len);
         // Fence ensures all memory operations are completed before proceeding further
-        asm volatile ("fence");
+        asm volatile("fence");
         from += frags[i].len;
     }
 }
@@ -150,7 +153,7 @@ static inline void ds_ll_start_sign(void)
 static inline ds_signature_check_t ds_ll_check_signature(void)
 {
     uint32_t result = REG_READ(DS_QUERY_CHECK_REG);
-    switch(result) {
+    switch (result) {
     case 0:
         return DS_SIGNATURE_OK;
     case 1:
@@ -172,7 +175,7 @@ static inline void ds_ll_read_result(uint8_t *result, size_t size)
 {
     memcpy(result, (uint8_t*) DS_Z_MEM, size);
     // Fence ensures all memory operations are completed before proceeding further
-    asm volatile ("fence");
+    asm volatile("fence");
 }
 
 /**

components/esp_hal_security/esp32h21/include/hal/ecc_ll.h

@@ -77,73 +77,73 @@ static inline void ecc_ll_clear_interrupt(void)
 
 static inline void ecc_ll_set_mode(ecc_mode_t mode)
 {
-    switch(mode) {
-        case ECC_MODE_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
-            break;
-        case ECC_MODE_VERIFY:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
-            break;
-        case ECC_MODE_VERIFY_THEN_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
-            break;
-        case ECC_MODE_JACOBIAN_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
-            break;
-        case ECC_MODE_POINT_ADD:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5);
-            break;
-        case ECC_MODE_JACOBIAN_POINT_VERIFY:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6);
-            break;
-        case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7);
-            break;
-        case ECC_MODE_MOD_ADD:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8);
-            break;
-        case ECC_MODE_MOD_SUB:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9);
-            break;
-        case ECC_MODE_MOD_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10);
-            break;
-        case ECC_MODE_INVERSE_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported mode");
-            break;
+    switch (mode) {
+    case ECC_MODE_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
+        break;
+    case ECC_MODE_VERIFY:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
+        break;
+    case ECC_MODE_VERIFY_THEN_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
+        break;
+    case ECC_MODE_JACOBIAN_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
+        break;
+    case ECC_MODE_POINT_ADD:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5);
+        break;
+    case ECC_MODE_JACOBIAN_POINT_VERIFY:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6);
+        break;
+    case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7);
+        break;
+    case ECC_MODE_MOD_ADD:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8);
+        break;
+    case ECC_MODE_MOD_SUB:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9);
+        break;
+    case ECC_MODE_MOD_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10);
+        break;
+    case ECC_MODE_INVERSE_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported mode");
+        break;
     }
 }
 
 static inline void ecc_ll_set_curve(ecc_curve_t curve)
 {
-    switch(curve) {
-        case ECC_CURVE_SECP256R1:
-            REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
-            break;
-        case ECC_CURVE_SECP192R1:
-            REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    switch (curve) {
+    case ECC_CURVE_SECP256R1:
+        REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
+        break;
+    case ECC_CURVE_SECP192R1:
+        REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
 static inline void ecc_ll_set_mod_base(ecc_mod_base_t base)
 {
-    switch(base) {
-        case ECC_MOD_N:
-            REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
-            break;
-        case ECC_MOD_P:
-            REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    switch (base) {
+    case ECC_MOD_N:
+        REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
+        break;
+    case ECC_MOD_P:
+        REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
@@ -161,27 +161,27 @@ static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf,
     uint32_t reg;
     uint32_t word;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_MEM;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_MEM;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_MEM;
-            break;
-        case ECC_PARAM_QX:
-            reg = ECC_MULT_QX_MEM;
-            break;
-        case ECC_PARAM_QY:
-            reg = ECC_MULT_QY_MEM;
-            break;
-        case ECC_PARAM_QZ:
-            reg = ECC_MULT_QZ_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_MEM;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_MEM;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_MEM;
+        break;
+    case ECC_PARAM_QX:
+        reg = ECC_MULT_QX_MEM;
+        break;
+    case ECC_PARAM_QY:
+        reg = ECC_MULT_QY_MEM;
+        break;
+    case ECC_PARAM_QZ:
+        reg = ECC_MULT_QZ_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     for (int i = 0; i < len; i += 4) {
@@ -224,27 +224,27 @@ static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_
 {
     uint32_t reg;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_MEM;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_MEM;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_MEM;
-            break;
-        case ECC_PARAM_QX:
-            reg = ECC_MULT_QX_MEM;
-            break;
-        case ECC_PARAM_QY:
-            reg = ECC_MULT_QY_MEM;
-            break;
-        case ECC_PARAM_QZ:
-            reg = ECC_MULT_QZ_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_MEM;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_MEM;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_MEM;
+        break;
+    case ECC_PARAM_QX:
+        reg = ECC_MULT_QX_MEM;
+        break;
+    case ECC_PARAM_QY:
+        reg = ECC_MULT_QY_MEM;
+        break;
+    case ECC_PARAM_QZ:
+        reg = ECC_MULT_QZ_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     memcpy(buf, (void *)reg, len);

components/esp_hal_security/esp32h21/include/hal/ecdsa_ll.h

@@ -108,15 +108,15 @@ static inline void ecdsa_ll_reset_register(void)
 static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_CALC_DONE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 1);
-            break;
-        case ECDSA_INT_SHA_RELEASE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 1);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported interrupt type");
-            break;
+    case ECDSA_INT_CALC_DONE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 1);
+        break;
+    case ECDSA_INT_SHA_RELEASE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 1);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported interrupt type");
+        break;
     }
 }
 
@@ -128,15 +128,15 @@ static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_disable_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_CALC_DONE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 0);
-            break;
-        case ECDSA_INT_SHA_RELEASE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 0);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported interrupt type");
-            break;
+    case ECDSA_INT_CALC_DONE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 0);
+        break;
+    case ECDSA_INT_SHA_RELEASE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 0);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported interrupt type");
+        break;
     }
 }
 
@@ -148,15 +148,15 @@ static inline void ecdsa_ll_disable_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_clear_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_CALC_DONE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_CLR, 1);
-            break;
-        case ECDSA_INT_SHA_RELEASE:
-            REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_SHA_RELEASE_INT_CLR, 1);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported interrupt type");
-            break;
+    case ECDSA_INT_CALC_DONE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_CLR, 1);
+        break;
+    case ECDSA_INT_SHA_RELEASE:
+        REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_SHA_RELEASE_INT_CLR, 1);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported interrupt type");
+        break;
     }
 }
 
@@ -168,18 +168,18 @@ static inline void ecdsa_ll_clear_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_set_mode(ecdsa_mode_t mode)
 {
     switch (mode) {
-        case ECDSA_MODE_SIGN_VERIFY:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 0);
-            break;
-        case ECDSA_MODE_SIGN_GEN:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 1);
-            break;
-        case ECDSA_MODE_EXPORT_PUBKEY:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 2);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported mode");
-            break;
+    case ECDSA_MODE_SIGN_VERIFY:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 0);
+        break;
+    case ECDSA_MODE_SIGN_GEN:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 1);
+        break;
+    case ECDSA_MODE_EXPORT_PUBKEY:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 2);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported mode");
+        break;
     }
 }
 
@@ -191,15 +191,15 @@ static inline void ecdsa_ll_set_mode(ecdsa_mode_t mode)
 static inline void ecdsa_ll_set_curve(ecdsa_curve_t curve)
 {
     switch (curve) {
-        case ECDSA_CURVE_SECP256R1:
-            REG_SET_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE);
-            break;
-        case ECDSA_CURVE_SECP192R1:
-            REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    case ECDSA_CURVE_SECP256R1:
+        REG_SET_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE);
+        break;
+    case ECDSA_CURVE_SECP192R1:
+        REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_ECC_CURVE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
@@ -211,15 +211,15 @@ static inline void ecdsa_ll_set_curve(ecdsa_curve_t curve)
 static inline void ecdsa_ll_set_z_mode(ecdsa_ll_sha_mode_t mode)
 {
     switch (mode) {
-        case ECDSA_Z_USE_SHA_PERI:
-            REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
-            break;
-        case ECDSA_Z_USER_PROVIDED:
-            REG_SET_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            break;
+    case ECDSA_Z_USE_SHA_PERI:
+        REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
+        break;
+    case ECDSA_Z_USER_PROVIDED:
+        REG_SET_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        break;
     }
 }
 
@@ -231,15 +231,15 @@ static inline void ecdsa_ll_set_z_mode(ecdsa_ll_sha_mode_t mode)
 static inline void ecdsa_ll_set_k_type(ecdsa_sign_type_t type)
 {
     switch (type) {
-        case ECDSA_K_TYPE_TRNG:
-            REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
-            break;
-        case ECDSA_K_TYPE_DETERMINISITIC:
-            REG_SET_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported K type");
-            break;
+    case ECDSA_K_TYPE_TRNG:
+        REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
+        break;
+    case ECDSA_K_TYPE_DETERMINISITIC:
+        REG_SET_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported K type");
+        break;
     }
 }
 
@@ -251,18 +251,18 @@ static inline void ecdsa_ll_set_k_type(ecdsa_sign_type_t type)
 static inline void ecdsa_ll_set_stage(ecdsa_ll_stage_t stage)
 {
     switch (stage) {
-        case ECDSA_STAGE_START_CALC:
-            REG_SET_BIT(ECDSA_START_REG, ECDSA_START);
-            break;
-        case ECDSA_STAGE_LOAD_DONE:
-            REG_SET_BIT(ECDSA_START_REG, ECDSA_LOAD_DONE);
-            break;
-        case ECDSA_STAGE_GET_DONE:
-            REG_SET_BIT(ECDSA_START_REG, ECDSA_GET_DONE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported state");
-            break;
+    case ECDSA_STAGE_START_CALC:
+        REG_SET_BIT(ECDSA_START_REG, ECDSA_START);
+        break;
+    case ECDSA_STAGE_LOAD_DONE:
+        REG_SET_BIT(ECDSA_START_REG, ECDSA_LOAD_DONE);
+        break;
+    case ECDSA_STAGE_GET_DONE:
+        REG_SET_BIT(ECDSA_START_REG, ECDSA_GET_DONE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported state");
+        break;
     }
 }
 
@@ -274,15 +274,15 @@ static inline void ecdsa_ll_set_stage(ecdsa_ll_stage_t stage)
 static inline void ecdsa_ll_sha_set_type(ecdsa_ll_sha_type_t type)
 {
     switch (type) {
-        case ECDSA_SHA_224:
-            REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 1);
-            break;
-        case ECDSA_SHA_256:
-            REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 2);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported type");
-            break;
+    case ECDSA_SHA_224:
+        REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 1);
+        break;
+    case ECDSA_SHA_256:
+        REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 2);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported type");
+        break;
     }
 }
 
@@ -294,15 +294,15 @@ static inline void ecdsa_ll_sha_set_type(ecdsa_ll_sha_type_t type)
 static inline void ecdsa_ll_sha_set_mode(ecdsa_ll_sha_mode_t mode)
 {
     switch (mode) {
-        case ECDSA_MODE_SHA_START:
-            REG_SET_BIT(ECDSA_SHA_START_REG, ECDSA_SHA_START);
-            break;
-        case ECDSA_MODE_SHA_CONTINUE:
-            REG_SET_BIT(ECDSA_SHA_CONTINUE_REG, ECDSA_SHA_CONTINUE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported type");
-            break;
+    case ECDSA_MODE_SHA_START:
+        REG_SET_BIT(ECDSA_SHA_START_REG, ECDSA_SHA_START);
+        break;
+    case ECDSA_MODE_SHA_CONTINUE:
+        REG_SET_BIT(ECDSA_SHA_CONTINUE_REG, ECDSA_SHA_CONTINUE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported type");
+        break;
     }
 }
 
@@ -329,24 +329,24 @@ static inline void ecdsa_ll_write_param(ecdsa_ll_param_t param, const uint8_t *b
     uint32_t reg;
     uint32_t word;
     switch (param) {
-        case ECDSA_PARAM_R:
-            reg = ECDSA_R_MEM;
-            break;
-        case ECDSA_PARAM_S:
-            reg = ECDSA_S_MEM;
-            break;
-        case ECDSA_PARAM_Z:
-            reg = ECDSA_Z_MEM;
-            break;
-        case ECDSA_PARAM_QAX:
-            reg = ECDSA_QAX_MEM;
-            break;
-        case ECDSA_PARAM_QAY:
-            reg = ECDSA_QAY_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECDSA_PARAM_R:
+        reg = ECDSA_R_MEM;
+        break;
+    case ECDSA_PARAM_S:
+        reg = ECDSA_S_MEM;
+        break;
+    case ECDSA_PARAM_Z:
+        reg = ECDSA_Z_MEM;
+        break;
+    case ECDSA_PARAM_QAX:
+        reg = ECDSA_QAX_MEM;
+        break;
+    case ECDSA_PARAM_QAY:
+        reg = ECDSA_QAY_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     for (int i = 0; i < len; i += 4) {
@@ -366,24 +366,24 @@ static inline void ecdsa_ll_read_param(ecdsa_ll_param_t param, uint8_t *buf, uin
 {
     uint32_t reg;
     switch (param) {
-        case ECDSA_PARAM_R:
-            reg = ECDSA_R_MEM;
-            break;
-        case ECDSA_PARAM_S:
-            reg = ECDSA_S_MEM;
-            break;
-        case ECDSA_PARAM_Z:
-            reg = ECDSA_Z_MEM;
-            break;
-        case ECDSA_PARAM_QAX:
-            reg = ECDSA_QAX_MEM;
-            break;
-        case ECDSA_PARAM_QAY:
-            reg = ECDSA_QAY_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECDSA_PARAM_R:
+        reg = ECDSA_R_MEM;
+        break;
+    case ECDSA_PARAM_S:
+        reg = ECDSA_S_MEM;
+        break;
+    case ECDSA_PARAM_Z:
+        reg = ECDSA_Z_MEM;
+        break;
+    case ECDSA_PARAM_QAX:
+        reg = ECDSA_QAX_MEM;
+        break;
+    case ECDSA_PARAM_QAY:
+        reg = ECDSA_QAY_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     memcpy(buf, (void *)reg, len);

components/esp_hal_security/esp32h21/include/hal/hmac_ll.h

@@ -67,7 +67,7 @@ static inline void hmac_ll_start(void)
  */
 static inline void hmac_ll_config_output(hmac_hal_output_t config)
 {
-    switch(config) {
+    switch (config) {
     case HMAC_OUTPUT_USER:
         REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_UP);
         break;
@@ -124,7 +124,7 @@ static inline void hmac_ll_wait_idle(void)
     uint32_t query;
     do {
         query = REG_READ(HMAC_QUERY_BUSY_REG);
-    } while(query != 0);
+    } while (query != 0);
 }
 
 /**

components/esp_hal_security/esp32h21/include/hal/mpi_ll.h

@@ -19,7 +19,6 @@
 extern "C" {
 #endif
 
-
 /**
  * @brief Enable the bus clock for MPI peripheral module
  *

components/esp_hal_security/esp32h21/include/hal/sha_ll.h

@@ -171,7 +171,6 @@ static inline void sha_ll_write_digest(esp_sha_type sha_type, void *digest_state
     }
 }
 
-
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32h4/include/hal/ecc_ll.h

@@ -79,73 +79,73 @@ static inline void ecc_ll_clear_interrupt(void)
 
 static inline void ecc_ll_set_mode(ecc_mode_t mode)
 {
-    switch(mode) {
-        case ECC_MODE_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
-            break;
-        case ECC_MODE_VERIFY:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
-            break;
-        case ECC_MODE_VERIFY_THEN_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
-            break;
-        case ECC_MODE_JACOBIAN_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
-            break;
-        case ECC_MODE_POINT_ADD:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5);
-            break;
-        case ECC_MODE_JACOBIAN_POINT_VERIFY:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6);
-            break;
-        case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7);
-            break;
-        case ECC_MODE_MOD_ADD:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8);
-            break;
-        case ECC_MODE_MOD_SUB:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9);
-            break;
-        case ECC_MODE_MOD_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10);
-            break;
-        case ECC_MODE_INVERSE_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported mode");
-            break;
+    switch (mode) {
+    case ECC_MODE_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
+        break;
+    case ECC_MODE_VERIFY:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
+        break;
+    case ECC_MODE_VERIFY_THEN_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
+        break;
+    case ECC_MODE_JACOBIAN_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
+        break;
+    case ECC_MODE_POINT_ADD:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5);
+        break;
+    case ECC_MODE_JACOBIAN_POINT_VERIFY:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6);
+        break;
+    case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7);
+        break;
+    case ECC_MODE_MOD_ADD:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8);
+        break;
+    case ECC_MODE_MOD_SUB:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9);
+        break;
+    case ECC_MODE_MOD_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10);
+        break;
+    case ECC_MODE_INVERSE_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported mode");
+        break;
     }
 }
 
 static inline void ecc_ll_set_curve(ecc_curve_t curve)
 {
-    switch(curve) {
-        case ECC_CURVE_SECP192R1:
-        case ECC_CURVE_SECP256R1:
-        case ECC_CURVE_SECP384R1:
-        case ECC_CURVE_SM2:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH, curve);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    switch (curve) {
+    case ECC_CURVE_SECP192R1:
+    case ECC_CURVE_SECP256R1:
+    case ECC_CURVE_SECP384R1:
+    case ECC_CURVE_SM2:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH, curve);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
 static inline void ecc_ll_set_mod_base(ecc_mod_base_t base)
 {
-    switch(base) {
-        case ECC_MOD_N:
-            REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
-            break;
-        case ECC_MOD_P:
-            REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    switch (base) {
+    case ECC_MOD_N:
+        REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
+        break;
+    case ECC_MOD_P:
+        REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
@@ -163,27 +163,27 @@ static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf,
     uint32_t reg;
     uint32_t word;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_MEM;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_MEM;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_MEM;
-            break;
-        case ECC_PARAM_QX:
-            reg = ECC_MULT_QX_MEM;
-            break;
-        case ECC_PARAM_QY:
-            reg = ECC_MULT_QY_MEM;
-            break;
-        case ECC_PARAM_QZ:
-            reg = ECC_MULT_QZ_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_MEM;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_MEM;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_MEM;
+        break;
+    case ECC_PARAM_QX:
+        reg = ECC_MULT_QX_MEM;
+        break;
+    case ECC_PARAM_QY:
+        reg = ECC_MULT_QY_MEM;
+        break;
+    case ECC_PARAM_QZ:
+        reg = ECC_MULT_QZ_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     for (int i = 0; i < len; i += 4) {
@@ -226,27 +226,27 @@ static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_
 {
     uint32_t reg;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_MEM;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_MEM;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_MEM;
-            break;
-        case ECC_PARAM_QX:
-            reg = ECC_MULT_QX_MEM;
-            break;
-        case ECC_PARAM_QY:
-            reg = ECC_MULT_QY_MEM;
-            break;
-        case ECC_PARAM_QZ:
-            reg = ECC_MULT_QZ_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_MEM;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_MEM;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_MEM;
+        break;
+    case ECC_PARAM_QX:
+        reg = ECC_MULT_QX_MEM;
+        break;
+    case ECC_PARAM_QY:
+        reg = ECC_MULT_QY_MEM;
+        break;
+    case ECC_PARAM_QZ:
+        reg = ECC_MULT_QZ_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     memcpy(buf, (void *)reg, len);

components/esp_hal_security/esp32p4/include/hal/aes_ll.h

@@ -129,7 +129,7 @@ static inline void aes_ll_read_block(void *output)
     for (size_t i = 0; i < AES_BLOCK_WORDS; i++) {
         output_word = REG_READ(AES_TEXT_OUT_0_REG + (i * REG_WIDTH));
         /* Memcpy to avoid potential unaligned access */
-        memcpy( (uint8_t*)output + i * 4, &output_word, sizeof(output_word));
+        memcpy((uint8_t*)output + i * 4, &output_word, sizeof(output_word));
     }
 }
 
@@ -142,7 +142,6 @@ static inline void aes_ll_start_transform(void)
     REG_WRITE(AES_TRIGGER_REG, 1);
 }
 
-
 /**
  * @brief Read state of AES accelerator
  *
@@ -153,7 +152,6 @@ static inline esp_aes_state_t aes_ll_get_state(void)
     return (esp_aes_state_t)REG_READ(AES_STATE_REG);
 }
 
-
 /**
  * @brief Set mode of operation
  *
@@ -206,7 +204,7 @@ static inline void aes_ll_set_iv(const uint8_t *iv)
     uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_MEM);
     uint32_t iv_word;
 
-    for (int i = 0; i < IV_WORDS; i++ ) {
+    for (int i = 0; i < IV_WORDS; i++) {
         /* Memcpy to avoid potential unaligned access */
         memcpy(&iv_word, iv + 4 * i, sizeof(iv_word));
         REG_WRITE(&reg_addr_buf[i], iv_word);

components/esp_hal_security/esp32p4/include/hal/apm_ll.h

@@ -37,7 +37,6 @@ typedef enum {
     APM_LL_MASTER_DMA,
 } apm_ll_master_id_t;
 
-
 /**
  * @brief APM Controller
  */
@@ -108,9 +107,9 @@ typedef enum {
     PMS_COREn_XM_HP_UART2_ALLOW,
     PMS_COREn_XM_HP_UART3_ALLOW,
     PMS_COREn_XM_HP_UART4_ALLOW,
-    PMS_COREn_XM_HP_PARLIO_ALLOW269 ,
-    PMS_COREn_XM_HP_GPSPI2_ALLOW270 ,
-    PMS_COREn_XM_HP_GPSPI3_ALLOW271 ,
+    PMS_COREn_XM_HP_PARLIO_ALLOW269,
+    PMS_COREn_XM_HP_GPSPI2_ALLOW270,
+    PMS_COREn_XM_HP_GPSPI3_ALLOW271,
     PMS_COREn_XM_HP_USBDEVICE_ALLOW,
     PMS_COREn_XM_HP_LEDC_ALLOW,
     PMS_COREn_XM_HP_ETM_ALLOW = 85,
@@ -132,7 +131,6 @@ typedef enum {
     PMS_COREn_XM_HP_PERI_MAX,
 } apm_ll_hp_peri_t;
 
-
 /**
  * @brief LP CPU Peripherals.
  */
@@ -163,7 +161,6 @@ typedef enum {
     PMS_LP_MM_PERI_MAX,
 } apm_ll_lp_peri_t;
 
-
 /**
  * @brief LP CPU Peripherals.
  */
@@ -216,7 +213,6 @@ typedef enum {
         (PMS_PERI_REGION0_LOW_REG + (regn_num * 8)); \
     })
 
-
 #define PMS_PERI_REGION_HIGH_REG(regn_num) \
     ({\
         (PMS_PERI_REGION0_HIGH_REG + (regn_num * 8)); \
@@ -232,7 +228,6 @@ typedef enum {
         (PMS_DMA_GDMA_CH0_W_PMS_REG + (dma_master * 8)); \
     })
 
-
 /**
  * @brief Configure HP peripherals access permission for the HP CPU0/1.
  *
@@ -241,15 +236,15 @@ typedef enum {
  * @param enable     Permission enable/disable
  */
 static inline void apm_ll_hp_peri_access_enable(apm_ll_master_id_t master_id, apm_ll_hp_peri_t hp_peri,
-                                       apm_ll_secure_mode_t sec_mode, bool enable)
+                                                apm_ll_secure_mode_t sec_mode, bool enable)
 {
     HAL_ASSERT((master_id > APM_LL_MASTER_LPCPU) && (master_id < APM_LL_MASTER_DMA)
-              && (hp_peri < PMS_COREn_XM_HP_PERI_MAX) && (sec_mode < APM_LL_SECURE_MODE_INV));
+               && (hp_peri < PMS_COREn_XM_HP_PERI_MAX) && (sec_mode < APM_LL_SECURE_MODE_INV));
 
     if (enable) {
-        REG_SET_BIT(PMS_COREn_XM_PMS_REGn_REG(master_id, sec_mode, hp_peri), BIT(hp_peri%32));
+        REG_SET_BIT(PMS_COREn_XM_PMS_REGn_REG(master_id, sec_mode, hp_peri), BIT(hp_peri % 32));
     } else {
-        REG_CLR_BIT(PMS_COREn_XM_PMS_REGn_REG(master_id, sec_mode, hp_peri), BIT(hp_peri%32));
+        REG_CLR_BIT(PMS_COREn_XM_PMS_REGn_REG(master_id, sec_mode, hp_peri), BIT(hp_peri % 32));
     }
 }
 
@@ -278,7 +273,7 @@ static inline void apm_ll_lp_peri_access_enable(apm_ll_lp_peri_t lp_peri, bool e
  * @param regn_high_addr Configurable address range end address.
  */
 static inline void apm_ll_peri_region_config(uint32_t regn_num, uint32_t regn_low_addr,
-                                                   uint32_t regn_high_addr)
+                                             uint32_t regn_high_addr)
 {
     HAL_ASSERT(regn_num < PMS_PERI_MAX_REGION_NUM);
 
@@ -298,32 +293,32 @@ static inline void apm_ll_peri_region_config(uint32_t regn_num, uint32_t regn_lo
  * @return           Configuration performed successfully?
  */
 static inline int apm_ll_peri_region_pms(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode,
-                                           uint32_t regn_num, uint32_t regn_pms)
+                                         uint32_t regn_num, uint32_t regn_pms)
 {
     HAL_ASSERT((master_id < APM_LL_MASTER_DMA) && (sec_mode < APM_LL_SECURE_MODE_INV));
 
     regn_pms &= 0x3;
 
-    switch(master_id) {
-        case APM_LL_MASTER_LPCPU:
-            REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_LP_CORE_REGION_PMS, regn_pms);
-            break;
-        case APM_LL_MASTER_HPCPU0:
-            if (sec_mode) {
-                REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE0_UM_REGION_PMS, regn_pms);
-            } else {
-                REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE0_MM_REGION_PMS, regn_pms);
-            }
-            break;
-        case APM_LL_MASTER_HPCPU1:
-            if (sec_mode) {
-                REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE1_UM_REGION_PMS, regn_pms);
-            } else {
-                REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE1_MM_REGION_PMS, regn_pms);
-            }
-            break;
-        default:
-            return -1;
+    switch (master_id) {
+    case APM_LL_MASTER_LPCPU:
+        REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_LP_CORE_REGION_PMS, regn_pms);
+        break;
+    case APM_LL_MASTER_HPCPU0:
+        if (sec_mode) {
+            REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE0_UM_REGION_PMS, regn_pms);
+        } else {
+            REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE0_MM_REGION_PMS, regn_pms);
+        }
+        break;
+    case APM_LL_MASTER_HPCPU1:
+        if (sec_mode) {
+            REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE1_UM_REGION_PMS, regn_pms);
+        } else {
+            REG_SET_FIELD(PMS_PERI_REGION_PMS_REG, PMS_HP_CORE1_MM_REGION_PMS, regn_pms);
+        }
+        break;
+    default:
+        return -1;
     }
 
     return 0;
@@ -343,24 +338,24 @@ static inline int apm_ll_apm_ctrl_clk_gating_enable(apm_ll_apm_ctrl_t apm_ctrl,
 
     HAL_ASSERT(apm_ctrl < MAX_APM_CTRL);
 
-    switch(apm_ctrl) {
-        case LP_APM_CTRL:
-            reg = PMS_LP_PERI_PMS_CLK_EN_REG;
-            break;
-        case HP2LP_APM_CTRL:
-            reg = PMS_HP2LP_PERI_PMS_CLK_EN_REG;
-            break;
-        case HP_APM_CTRL:
-            reg = PMS_HP_PERI_PMS_CLK_EN_REG;
-            break;
-        case LP2HP_APM_CTRL:
-            reg = PMS_LP2HP_PERI_PMS_CLK_EN_REG;
-            break;
-        case DMA_APM_CTRL:
-            reg = PMS_DMA_CLK_EN_REG;
-            break;
-        default:
-            return -1;
+    switch (apm_ctrl) {
+    case LP_APM_CTRL:
+        reg = PMS_LP_PERI_PMS_CLK_EN_REG;
+        break;
+    case HP2LP_APM_CTRL:
+        reg = PMS_HP2LP_PERI_PMS_CLK_EN_REG;
+        break;
+    case HP_APM_CTRL:
+        reg = PMS_HP_PERI_PMS_CLK_EN_REG;
+        break;
+    case LP2HP_APM_CTRL:
+        reg = PMS_LP2HP_PERI_PMS_CLK_EN_REG;
+        break;
+    case DMA_APM_CTRL:
+        reg = PMS_DMA_CLK_EN_REG;
+        break;
+    default:
+        return -1;
     }
 
     if (enable) {

components/esp_hal_security/esp32p4/include/hal/ds_ll.h

@@ -111,7 +111,7 @@ static inline void ds_ll_set_key_source(ds_key_source_t key_source)
 static inline void ds_ll_configure_iv(const uint32_t *iv)
 {
     for (size_t i = 0; i < (SOC_DS_KEY_PARAM_MD_IV_LENGTH / sizeof(uint32_t)); i++) {
-        REG_WRITE(DS_IV_MEM + (i * 4) , iv[i]);
+        REG_WRITE(DS_IV_MEM + (i * 4), iv[i]);
     }
 }
 
@@ -125,7 +125,7 @@ static inline void ds_ll_write_message(const uint8_t *msg, size_t size)
 {
     memcpy((uint8_t*) DS_X_MEM, msg, size);
     // Fence ensures all memory operations are completed before proceeding further
-    asm volatile ("fence");
+    asm volatile("fence");
 }
 
 /**
@@ -139,20 +139,23 @@ static inline void ds_ll_write_private_key_params(const uint8_t *encrypted_key_p
 
        (note if ETS_DS_MAX_BITS == 4096, this should be the same as copying data->c to hardware in one fragment)
     */
-    typedef struct { uint32_t addr; size_t len; } frag_t;
+    typedef struct {
+        uint32_t addr;
+        size_t len;
+    } frag_t;
     const frag_t frags[] = {
-                            {DS_Y_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_M_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_RB_MEM, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
-                            {DS_BOX_MEM, DS_IV_MEM - DS_BOX_MEM},
+        {DS_Y_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_M_MEM,  SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_RB_MEM, SOC_DS_SIGNATURE_MAX_BIT_LEN / 8},
+        {DS_BOX_MEM, DS_IV_MEM - DS_BOX_MEM},
     };
-    const size_t NUM_FRAGS = sizeof(frags)/sizeof(frag_t);
+    const size_t NUM_FRAGS = sizeof(frags) / sizeof(frag_t);
     const uint8_t *from = encrypted_key_params;
 
     for (int i = 0; i < NUM_FRAGS; i++) {
         memcpy((uint8_t *)frags[i].addr, from, frags[i].len);
         // Fence ensures all memory operations are completed before proceeding further
-        asm volatile ("fence");
+        asm volatile("fence");
         from += frags[i].len;
     }
 }
@@ -178,7 +181,7 @@ static inline void ds_ll_start_sign(void)
 static inline ds_signature_check_t ds_ll_check_signature(void)
 {
     uint32_t result = REG_READ(DS_QUERY_CHECK_REG);
-    switch(result) {
+    switch (result) {
     case 0:
         return DS_SIGNATURE_OK;
     case 1:
@@ -200,7 +203,7 @@ static inline void ds_ll_read_result(uint8_t *result, size_t size)
 {
     memcpy(result, (uint8_t*) DS_Z_MEM, size);
     // Fence ensures all memory operations are completed before proceeding further
-    asm volatile ("fence");
+    asm volatile("fence");
 }
 
 /**

components/esp_hal_security/esp32p4/include/hal/ecc_ll.h

@@ -85,72 +85,72 @@ static inline void ecc_ll_clear_interrupt(void)
 
 static inline void ecc_ll_set_mode(ecc_mode_t mode)
 {
-    switch(mode) {
-        case ECC_MODE_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
-            break;
-        case ECC_MODE_VERIFY:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
-            break;
-        case ECC_MODE_VERIFY_THEN_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
-            break;
-        case ECC_MODE_JACOBIAN_POINT_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
-            break;
-        case ECC_MODE_POINT_ADD:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5);
-            break;
-        case ECC_MODE_JACOBIAN_POINT_VERIFY:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6);
-            break;
-        case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7);
-            break;
-        case ECC_MODE_MOD_ADD:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8);
-            break;
-        case ECC_MODE_MOD_SUB:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9);
-            break;
-        case ECC_MODE_MOD_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10);
-            break;
-        case ECC_MODE_INVERSE_MUL:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported mode");
-            break;
+    switch (mode) {
+    case ECC_MODE_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 0);
+        break;
+    case ECC_MODE_VERIFY:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 2);
+        break;
+    case ECC_MODE_VERIFY_THEN_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 3);
+        break;
+    case ECC_MODE_JACOBIAN_POINT_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 4);
+        break;
+    case ECC_MODE_POINT_ADD:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 5);
+        break;
+    case ECC_MODE_JACOBIAN_POINT_VERIFY:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 6);
+        break;
+    case ECC_MODE_POINT_VERIFY_JACOBIAN_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 7);
+        break;
+    case ECC_MODE_MOD_ADD:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 8);
+        break;
+    case ECC_MODE_MOD_SUB:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 9);
+        break;
+    case ECC_MODE_MOD_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 10);
+        break;
+    case ECC_MODE_INVERSE_MUL:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_WORK_MODE, 11);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported mode");
+        break;
     }
 }
 
 static inline void ecc_ll_set_curve(ecc_curve_t curve)
 {
     switch (curve) {
-        case ECC_CURVE_SECP192R1:
-        case ECC_CURVE_SECP256R1:
-        case ECC_CURVE_SECP384R1:
-        case ECC_CURVE_SM2:
-            REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH, curve);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
+    case ECC_CURVE_SECP192R1:
+    case ECC_CURVE_SECP256R1:
+    case ECC_CURVE_SECP384R1:
+    case ECC_CURVE_SM2:
+        REG_SET_FIELD(ECC_MULT_CONF_REG, ECC_MULT_KEY_LENGTH, curve);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
     }
 }
 
 static inline void ecc_ll_set_mod_base(ecc_mod_base_t base)
 {
-    switch(base) {
-        case ECC_MOD_N:
-            REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
-            break;
-        case ECC_MOD_P:
-            REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    switch (base) {
+    case ECC_MOD_N:
+        REG_CLR_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
+        break;
+    case ECC_MOD_P:
+        REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_MOD_BASE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
@@ -159,27 +159,27 @@ static inline void ecc_ll_write_param(ecc_ll_param_t param, const uint8_t *buf,
     uint32_t reg;
     uint32_t word;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_MEM;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_MEM;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_MEM;
-            break;
-        case ECC_PARAM_QX:
-            reg = ECC_MULT_QX_MEM;
-            break;
-        case ECC_PARAM_QY:
-            reg = ECC_MULT_QY_MEM;
-            break;
-        case ECC_PARAM_QZ:
-            reg = ECC_MULT_QZ_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_MEM;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_MEM;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_MEM;
+        break;
+    case ECC_PARAM_QX:
+        reg = ECC_MULT_QX_MEM;
+        break;
+    case ECC_PARAM_QY:
+        reg = ECC_MULT_QY_MEM;
+        break;
+    case ECC_PARAM_QZ:
+        reg = ECC_MULT_QZ_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     for (int i = 0; i < len; i += 4) {
@@ -222,27 +222,27 @@ static inline void ecc_ll_read_param(ecc_ll_param_t param, uint8_t *buf, uint16_
 {
     uint32_t reg;
     switch (param) {
-        case ECC_PARAM_PX:
-            reg = ECC_MULT_PX_MEM;
-            break;
-        case ECC_PARAM_PY:
-            reg = ECC_MULT_PY_MEM;
-            break;
-        case ECC_PARAM_K:
-            reg = ECC_MULT_K_MEM;
-            break;
-        case ECC_PARAM_QX:
-            reg = ECC_MULT_QX_MEM;
-            break;
-        case ECC_PARAM_QY:
-            reg = ECC_MULT_QY_MEM;
-            break;
-        case ECC_PARAM_QZ:
-            reg = ECC_MULT_QZ_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECC_PARAM_PX:
+        reg = ECC_MULT_PX_MEM;
+        break;
+    case ECC_PARAM_PY:
+        reg = ECC_MULT_PY_MEM;
+        break;
+    case ECC_PARAM_K:
+        reg = ECC_MULT_K_MEM;
+        break;
+    case ECC_PARAM_QX:
+        reg = ECC_MULT_QX_MEM;
+        break;
+    case ECC_PARAM_QY:
+        reg = ECC_MULT_QY_MEM;
+        break;
+    case ECC_PARAM_QZ:
+        reg = ECC_MULT_QZ_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     memcpy(buf, (void *)reg, len);

components/esp_hal_security/esp32p4/include/hal/ecdsa_ll.h

@@ -126,19 +126,19 @@ static inline void ecdsa_ll_reset_register(void)
 static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_CALC_DONE:
+    case ECDSA_INT_CALC_DONE:
 #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 1);
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 1);
 #else
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_CALC_DONE_INT_ENA, 1);
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_CALC_DONE_INT_ENA, 1);
 #endif
-            break;
-        case ECDSA_INT_SHA_RELEASE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 1);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported interrupt type");
-            break;
+        break;
+    case ECDSA_INT_SHA_RELEASE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 1);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported interrupt type");
+        break;
     }
 }
 
@@ -150,19 +150,19 @@ static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_disable_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_CALC_DONE:
+    case ECDSA_INT_CALC_DONE:
 #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 0);
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 0);
 #else
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_CALC_DONE_INT_ENA, 0);
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_CALC_DONE_INT_ENA, 0);
 #endif
-            break;
-        case ECDSA_INT_SHA_RELEASE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 0);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported interrupt type");
-            break;
+        break;
+    case ECDSA_INT_SHA_RELEASE:
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 0);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported interrupt type");
+        break;
     }
 }
 
@@ -174,19 +174,19 @@ static inline void ecdsa_ll_disable_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_clear_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_CALC_DONE:
+    case ECDSA_INT_CALC_DONE:
 #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_CLR, 1);
+        REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_CLR, 1);
 #else
-            REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_CALC_DONE_INT_CLR, 1);
+        REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_CALC_DONE_INT_CLR, 1);
 #endif
-            break;
-        case ECDSA_INT_SHA_RELEASE:
-            REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_SHA_RELEASE_INT_CLR, 1);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported interrupt type");
-            break;
+        break;
+    case ECDSA_INT_SHA_RELEASE:
+        REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_SHA_RELEASE_INT_CLR, 1);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported interrupt type");
+        break;
     }
 }
 
@@ -198,18 +198,18 @@ static inline void ecdsa_ll_clear_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_set_mode(ecdsa_mode_t mode)
 {
     switch (mode) {
-        case ECDSA_MODE_SIGN_VERIFY:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 0);
-            break;
-        case ECDSA_MODE_SIGN_GEN:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 1);
-            break;
-        case ECDSA_MODE_EXPORT_PUBKEY:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 2);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported mode");
-            break;
+    case ECDSA_MODE_SIGN_VERIFY:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 0);
+        break;
+    case ECDSA_MODE_SIGN_GEN:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 1);
+        break;
+    case ECDSA_MODE_EXPORT_PUBKEY:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_WORK_MODE, 2);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported mode");
+        break;
     }
 }
 
@@ -221,15 +221,15 @@ static inline void ecdsa_ll_set_mode(ecdsa_mode_t mode)
 static inline void ecdsa_ll_set_curve(ecdsa_curve_t curve)
 {
     switch (curve) {
-        case ECDSA_CURVE_SECP192R1:
-        case ECDSA_CURVE_SECP256R1:
-        case ECDSA_CURVE_SECP384R1:
-        case ECDSA_CURVE_SM2:
-            REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_ECC_CURVE, curve);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            return;
+    case ECDSA_CURVE_SECP192R1:
+    case ECDSA_CURVE_SECP256R1:
+    case ECDSA_CURVE_SECP384R1:
+    case ECDSA_CURVE_SM2:
+        REG_SET_FIELD(ECDSA_CONF_REG, ECDSA_ECC_CURVE, curve);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        return;
     }
 }
 
@@ -241,15 +241,15 @@ static inline void ecdsa_ll_set_curve(ecdsa_curve_t curve)
 static inline void ecdsa_ll_set_z_mode(ecdsa_ll_sha_mode_t mode)
 {
     switch (mode) {
-        case ECDSA_Z_USE_SHA_PERI:
-            REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
-            break;
-        case ECDSA_Z_USER_PROVIDED:
-            REG_SET_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            break;
+    case ECDSA_Z_USE_SHA_PERI:
+        REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
+        break;
+    case ECDSA_Z_USER_PROVIDED:
+        REG_SET_BIT(ECDSA_CONF_REG, ECDSA_SOFTWARE_SET_Z);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        break;
     }
 }
 
@@ -261,15 +261,15 @@ static inline void ecdsa_ll_set_z_mode(ecdsa_ll_sha_mode_t mode)
 static inline void ecdsa_ll_set_k_type(ecdsa_sign_type_t type)
 {
     switch (type) {
-        case ECDSA_K_TYPE_TRNG:
-            REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
-            break;
-        case ECDSA_K_TYPE_DETERMINISITIC:
-            REG_SET_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported K type");
-            break;
+    case ECDSA_K_TYPE_TRNG:
+        REG_CLR_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
+        break;
+    case ECDSA_K_TYPE_DETERMINISITIC:
+        REG_SET_BIT(ECDSA_CONF_REG, ECDSA_DETERMINISTIC_K);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported K type");
+        break;
     }
 }
 
@@ -293,18 +293,18 @@ static inline void ecdsa_ll_set_deterministic_loop(uint16_t loop_number)
 static inline void ecdsa_ll_set_stage(ecdsa_ll_stage_t stage)
 {
     switch (stage) {
-        case ECDSA_STAGE_START_CALC:
-            REG_SET_BIT(ECDSA_START_REG, ECDSA_START);
-            break;
-        case ECDSA_STAGE_LOAD_DONE:
-            REG_SET_BIT(ECDSA_START_REG, ECDSA_LOAD_DONE);
-            break;
-        case ECDSA_STAGE_GET_DONE:
-            REG_SET_BIT(ECDSA_START_REG, ECDSA_GET_DONE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported state");
-            break;
+    case ECDSA_STAGE_START_CALC:
+        REG_SET_BIT(ECDSA_START_REG, ECDSA_START);
+        break;
+    case ECDSA_STAGE_LOAD_DONE:
+        REG_SET_BIT(ECDSA_START_REG, ECDSA_LOAD_DONE);
+        break;
+    case ECDSA_STAGE_GET_DONE:
+        REG_SET_BIT(ECDSA_START_REG, ECDSA_GET_DONE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported state");
+        break;
     }
 }
 
@@ -316,15 +316,15 @@ static inline void ecdsa_ll_set_stage(ecdsa_ll_stage_t stage)
 static inline void ecdsa_ll_sha_set_type(ecdsa_ll_sha_type_t type)
 {
     switch (type) {
-        case ECDSA_SHA_224:
-            REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 1);
-            break;
-        case ECDSA_SHA_256:
-            REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 2);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported type");
-            break;
+    case ECDSA_SHA_224:
+        REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 1);
+        break;
+    case ECDSA_SHA_256:
+        REG_SET_FIELD(ECDSA_SHA_MODE_REG, ECDSA_SHA_MODE, 2);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported type");
+        break;
     }
 }
 
@@ -336,15 +336,15 @@ static inline void ecdsa_ll_sha_set_type(ecdsa_ll_sha_type_t type)
 static inline void ecdsa_ll_sha_set_mode(ecdsa_ll_sha_mode_t mode)
 {
     switch (mode) {
-        case ECDSA_MODE_SHA_START:
-            REG_SET_BIT(ECDSA_SHA_START_REG, ECDSA_SHA_START);
-            break;
-        case ECDSA_MODE_SHA_CONTINUE:
-            REG_SET_BIT(ECDSA_SHA_CONTINUE_REG, ECDSA_SHA_CONTINUE);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported type");
-            break;
+    case ECDSA_MODE_SHA_START:
+        REG_SET_BIT(ECDSA_SHA_START_REG, ECDSA_SHA_START);
+        break;
+    case ECDSA_MODE_SHA_CONTINUE:
+        REG_SET_BIT(ECDSA_SHA_CONTINUE_REG, ECDSA_SHA_CONTINUE);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported type");
+        break;
     }
 }
 
@@ -371,24 +371,24 @@ static inline void ecdsa_ll_write_param(ecdsa_ll_param_t param, const uint8_t *b
     uint32_t reg;
     uint32_t word;
     switch (param) {
-        case ECDSA_PARAM_R:
-            reg = ECDSA_R_MEM;
-            break;
-        case ECDSA_PARAM_S:
-            reg = ECDSA_S_MEM;
-            break;
-        case ECDSA_PARAM_Z:
-            reg = ECDSA_Z_MEM;
-            break;
-        case ECDSA_PARAM_QAX:
-            reg = ECDSA_QAX_MEM;
-            break;
-        case ECDSA_PARAM_QAY:
-            reg = ECDSA_QAY_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECDSA_PARAM_R:
+        reg = ECDSA_R_MEM;
+        break;
+    case ECDSA_PARAM_S:
+        reg = ECDSA_S_MEM;
+        break;
+    case ECDSA_PARAM_Z:
+        reg = ECDSA_Z_MEM;
+        break;
+    case ECDSA_PARAM_QAX:
+        reg = ECDSA_QAX_MEM;
+        break;
+    case ECDSA_PARAM_QAY:
+        reg = ECDSA_QAY_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     for (int i = 0; i < len; i += 4) {
@@ -408,24 +408,24 @@ static inline void ecdsa_ll_read_param(ecdsa_ll_param_t param, uint8_t *buf, uin
 {
     uint32_t reg;
     switch (param) {
-        case ECDSA_PARAM_R:
-            reg = ECDSA_R_MEM;
-            break;
-        case ECDSA_PARAM_S:
-            reg = ECDSA_S_MEM;
-            break;
-        case ECDSA_PARAM_Z:
-            reg = ECDSA_Z_MEM;
-            break;
-        case ECDSA_PARAM_QAX:
-            reg = ECDSA_QAX_MEM;
-            break;
-        case ECDSA_PARAM_QAY:
-            reg = ECDSA_QAY_MEM;
-            break;
-        default:
-            HAL_ASSERT(false && "Invalid parameter");
-            return;
+    case ECDSA_PARAM_R:
+        reg = ECDSA_R_MEM;
+        break;
+    case ECDSA_PARAM_S:
+        reg = ECDSA_S_MEM;
+        break;
+    case ECDSA_PARAM_Z:
+        reg = ECDSA_Z_MEM;
+        break;
+    case ECDSA_PARAM_QAX:
+        reg = ECDSA_QAX_MEM;
+        break;
+    case ECDSA_PARAM_QAY:
+        reg = ECDSA_QAY_MEM;
+        break;
+    default:
+        HAL_ASSERT(false && "Invalid parameter");
+        return;
     }
 
     memcpy(buf, (void *)reg, len);
@@ -480,22 +480,22 @@ __attribute__((always_inline)) static inline void ecdsa_ll_set_ecdsa_key_blk(ecd
     uint8_t efuse_blk_low = 0;
     uint8_t efuse_blk_high = 0;
     switch (curve) {
-        case ECDSA_CURVE_SECP192R1:
-            EFUSE.ecdsa.cfg_ecdsa_p192_blk = efuse_blk;
-            break;
-        case ECDSA_CURVE_SECP256R1:
-            EFUSE.ecdsa.cfg_ecdsa_p256_blk = efuse_blk;
-            break;
-        case ECDSA_CURVE_SECP384R1:
-            // ECDSA-p384 uses two efuse blocks to store the key. These two blocks are stored in a single integer
-            // where the least significant 4 bits store the low key block number and the next 4 more significant bits store the high key block number.
-            HAL_ECDSA_EXTRACT_KEY_BLOCKS(efuse_blk, efuse_blk_high, efuse_blk_low);
-            EFUSE.ecdsa.cfg_ecdsa_p384_h_blk = efuse_blk_high;
-            EFUSE.ecdsa.cfg_ecdsa_p384_l_blk = efuse_blk_low;
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported curve");
-            break;
+    case ECDSA_CURVE_SECP192R1:
+        EFUSE.ecdsa.cfg_ecdsa_p192_blk = efuse_blk;
+        break;
+    case ECDSA_CURVE_SECP256R1:
+        EFUSE.ecdsa.cfg_ecdsa_p256_blk = efuse_blk;
+        break;
+    case ECDSA_CURVE_SECP384R1:
+        // ECDSA-p384 uses two efuse blocks to store the key. These two blocks are stored in a single integer
+        // where the least significant 4 bits store the low key block number and the next 4 more significant bits store the high key block number.
+        HAL_ECDSA_EXTRACT_KEY_BLOCKS(efuse_blk, efuse_blk_high, efuse_blk_low);
+        EFUSE.ecdsa.cfg_ecdsa_p384_h_blk = efuse_blk_high;
+        EFUSE.ecdsa.cfg_ecdsa_p384_l_blk = efuse_blk_low;
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported curve");
+        break;
     }
 #endif
 }

components/esp_hal_security/esp32p4/include/hal/hmac_ll.h

@@ -84,7 +84,7 @@ static inline void hmac_ll_start(void)
  */
 static inline void hmac_ll_config_output(hmac_hal_output_t config)
 {
-    switch(config) {
+    switch (config) {
     case HMAC_OUTPUT_USER:
         REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, EFUSE_KEY_PURPOSE_HMAC_UP);
         break;
@@ -141,7 +141,7 @@ static inline void hmac_ll_wait_idle(void)
     uint32_t query;
     do {
         query = REG_READ(HMAC_QUERY_BUSY_REG);
-    } while(query != 0);
+    } while (query != 0);
 }
 
 /**

components/esp_hal_security/esp32p4/include/hal/key_mgr_ll.h

@@ -137,36 +137,36 @@ static inline void key_mgr_ll_continue(void)
 /* @brief Enable or Disable the KEY_MGR interrupts */
 static inline void key_mgr_ll_configure_interrupt(const esp_key_mgr_interrupt_type_t intr, bool en)
 {
-    switch(intr) {
-        case ESP_KEY_MGR_INT_PREP_DONE:
-            REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_PREP_DONE_INT_ENA, en);
-            break;
-        case ESP_KEY_MGR_INT_PROC_DONE:
-            REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_PROC_DONE_INT_ENA, en);
-            break;
-        case ESP_KEY_MGR_INT_POST_DONE:
-            REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_POST_DONE_INT_ENA, en);
-            break;
-        default:
-            return;
+    switch (intr) {
+    case ESP_KEY_MGR_INT_PREP_DONE:
+        REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_PREP_DONE_INT_ENA, en);
+        break;
+    case ESP_KEY_MGR_INT_PROC_DONE:
+        REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_PROC_DONE_INT_ENA, en);
+        break;
+    case ESP_KEY_MGR_INT_POST_DONE:
+        REG_SET_FIELD(KEYMNG_INT_ENA_REG, KEYMNG_POST_DONE_INT_ENA, en);
+        break;
+    default:
+        return;
     }
 }
 
 /* @brief Clear the KEY_MGR interrupts */
 static inline void key_mgr_ll_clear_int(const esp_key_mgr_interrupt_type_t intr)
 {
-    switch(intr) {
-        case ESP_KEY_MGR_INT_PREP_DONE:
-            REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_PREP_DONE_INT_CLR, 1);
-            break;
-        case ESP_KEY_MGR_INT_PROC_DONE:
-            REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_PROC_DONE_INT_CLR, 1);
-            break;
-        case ESP_KEY_MGR_INT_POST_DONE:
-            REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_POST_DONE_INT_CLR, 1);
-            break;
-        default:
-            return;
+    switch (intr) {
+    case ESP_KEY_MGR_INT_PREP_DONE:
+        REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_PREP_DONE_INT_CLR, 1);
+        break;
+    case ESP_KEY_MGR_INT_PROC_DONE:
+        REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_PROC_DONE_INT_CLR, 1);
+        break;
+    case ESP_KEY_MGR_INT_POST_DONE:
+        REG_SET_FIELD(KEYMNG_INT_CLR_REG, KEYMNG_POST_DONE_INT_CLR, 1);
+        break;
+    default:
+        return;
     }
 }
 
@@ -185,75 +185,75 @@ static inline void key_mgr_ll_use_sw_init_key(void)
 static inline void key_mgr_ll_set_key_usage(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_usage_t key_usage)
 {
     switch (key_type) {
-        case ESP_KEY_MGR_ECDSA_KEY:
-            if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
-                REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
-            } else {
-                REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
-            }
-            break;
+    case ESP_KEY_MGR_ECDSA_KEY:
+        if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
+            REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
+        } else {
+            REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA);
+        }
+        break;
 
-        case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
-            if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
-                REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
-            } else {
-                REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
-            }
-            break;
+    case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
+        if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
+            REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
+        } else {
+            REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH);
+        }
+        break;
 
 #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
-        case ESP_KEY_MGR_HMAC_KEY:
-            if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
-                REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
-            } else {
-                REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
-            }
-            break;
+    case ESP_KEY_MGR_HMAC_KEY:
+        if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
+            REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
+        } else {
+            REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC);
+        }
+        break;
 
-        case ESP_KEY_MGR_DS_KEY:
-            if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
-                REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
-            } else {
-                REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
-            }
-            break;
+    case ESP_KEY_MGR_DS_KEY:
+        if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
+            REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
+        } else {
+            REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS);
+        }
+        break;
 
-        case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
-            if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
-                REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
-            } else {
-                REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
-            }
+    case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
+        if (key_usage == ESP_KEY_MGR_USE_EFUSE_KEY) {
+            REG_SET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
+        } else {
+            REG_CLR_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM);
+        }
         break;
 #endif
-        default:
-            HAL_ASSERT(false && "Unsupported key type");
-            return;
+    default:
+        HAL_ASSERT(false && "Unsupported key type");
+        return;
     }
 }
 
 static inline esp_key_mgr_key_usage_t key_mgr_ll_get_key_usage(esp_key_mgr_key_type_t key_type)
 {
     switch (key_type) {
-        case ESP_KEY_MGR_ECDSA_KEY:
-            return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA));
+    case ESP_KEY_MGR_ECDSA_KEY:
+        return (esp_key_mgr_key_usage_t)(REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_ECDSA));
 
-        case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
-            return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH));
+    case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
+        return (esp_key_mgr_key_usage_t)(REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_FLASH));
 
 #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
-        case ESP_KEY_MGR_HMAC_KEY:
-            return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC));
+    case ESP_KEY_MGR_HMAC_KEY:
+        return (esp_key_mgr_key_usage_t)(REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_HMAC));
 
-        case ESP_KEY_MGR_DS_KEY:
-            return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS));
+    case ESP_KEY_MGR_DS_KEY:
+        return (esp_key_mgr_key_usage_t)(REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_DS));
 
-        case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
-            return (esp_key_mgr_key_usage_t) (REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM));
+    case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
+        return (esp_key_mgr_key_usage_t)(REG_GET_BIT(KEYMNG_STATIC_REG, KEYMNG_USE_EFUSE_KEY_PSRAM));
 #endif
-        default:
-            HAL_ASSERT(false && "Unsupported key type");
-            return ESP_KEY_MGR_USAGE_INVALID;
+    default:
+        HAL_ASSERT(false && "Unsupported key type");
+        return ESP_KEY_MGR_USAGE_INVALID;
     }
 }
 
@@ -274,31 +274,31 @@ static inline void key_mgr_ll_lock_use_sw_init_key_reg(void)
  */
 static inline void key_mgr_ll_lock_use_efuse_key_reg(esp_key_mgr_key_type_t key_type)
 {
-    switch(key_type) {
-        case ESP_KEY_MGR_ECDSA_KEY:
-            REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA);
-            break;
+    switch (key_type) {
+    case ESP_KEY_MGR_ECDSA_KEY:
+        REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_ECDSA);
+        break;
 
-        case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
-            REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_FLASH);
-            break;
+    case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
+        REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_FLASH);
+        break;
 
 #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
-        case ESP_KEY_MGR_HMAC_KEY:
-            REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_HMAC);
-            break;
+    case ESP_KEY_MGR_HMAC_KEY:
+        REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_HMAC);
+        break;
 
-        case ESP_KEY_MGR_DS_KEY:
-            REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_DS);
-            break;
+    case ESP_KEY_MGR_DS_KEY:
+        REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_DS);
+        break;
 
-        case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
-            REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM);
-            break;
+    case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
+        REG_SET_BIT(KEYMNG_LOCK_REG, KEYMNG_USE_EFUSE_KEY_LOCK_PSRAM);
+        break;
 #endif
-        default:
-            HAL_ASSERT(false && "Unsupported key type");
-            return;
+    default:
+        HAL_ASSERT(false && "Unsupported key type");
+        return;
     }
 }
 
@@ -334,49 +334,49 @@ static inline bool key_mgr_ll_is_result_success(void)
 static inline bool key_mgr_ll_is_key_deployment_valid(const esp_key_mgr_key_type_t key_type, const esp_key_mgr_key_len_t key_len)
 {
     switch (key_type) {
-        case ESP_KEY_MGR_ECDSA_KEY:
-            switch (key_len) {
-                case ESP_KEY_MGR_ECDSA_LEN_192:
-                    return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_192_VLD);
-                case ESP_KEY_MGR_ECDSA_LEN_256:
-                    return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_256_VLD);
-                case ESP_KEY_MGR_ECDSA_LEN_384:
-                    return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_384_VLD);
-                default:
-                    HAL_ASSERT(false && "Unsupported key type");
-                    return 0;
-            }
+    case ESP_KEY_MGR_ECDSA_KEY:
+        switch (key_len) {
+        case ESP_KEY_MGR_ECDSA_LEN_192:
+            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_192_VLD);
+        case ESP_KEY_MGR_ECDSA_LEN_256:
+            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_256_VLD);
+        case ESP_KEY_MGR_ECDSA_LEN_384:
+            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_ECDSA_384_VLD);
+        default:
+            HAL_ASSERT(false && "Unsupported key type");
+            return 0;
+        }
 
-        case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
-            switch (key_len) {
-                case ESP_KEY_MGR_XTS_AES_LEN_128:
-                case ESP_KEY_MGR_XTS_AES_LEN_256:
-                    return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_FLASH_VLD);
-                default:
-                    HAL_ASSERT(false && "Unsupported key type");
-                    return 0;
-            }
+    case ESP_KEY_MGR_FLASH_XTS_AES_KEY:
+        switch (key_len) {
+        case ESP_KEY_MGR_XTS_AES_LEN_128:
+        case ESP_KEY_MGR_XTS_AES_LEN_256:
+            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_FLASH_VLD);
+        default:
+            HAL_ASSERT(false && "Unsupported key type");
+            return 0;
+        }
 
 #if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
-        case ESP_KEY_MGR_HMAC_KEY:
-            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_HMAC_VLD);
+    case ESP_KEY_MGR_HMAC_KEY:
+        return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_HMAC_VLD);
 
-        case ESP_KEY_MGR_DS_KEY:
-            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_DS_VLD);
+    case ESP_KEY_MGR_DS_KEY:
+        return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_DS_VLD);
 
-        case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
-            switch (key_len) {
-                case ESP_KEY_MGR_XTS_AES_LEN_128:
-                case ESP_KEY_MGR_XTS_AES_LEN_256:
-                    return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_PSRAM_VLD);
-                default:
-                    HAL_ASSERT(false && "Unsupported key type");
-                    return 0;
-            }
-#endif
+    case ESP_KEY_MGR_PSRAM_XTS_AES_KEY:
+        switch (key_len) {
+        case ESP_KEY_MGR_XTS_AES_LEN_128:
+        case ESP_KEY_MGR_XTS_AES_LEN_256:
+            return REG_GET_FIELD(KEYMNG_KEY_VLD_REG, KEYMNG_KEY_PSRAM_VLD);
         default:
-            HAL_ASSERT(false && "Unsupported mode");
+            HAL_ASSERT(false && "Unsupported key type");
             return 0;
+        }
+#endif
+    default:
+        HAL_ASSERT(false && "Unsupported mode");
+        return 0;
     }
 }
 
@@ -410,7 +410,7 @@ static inline void key_mgr_ll_write_assist_info(const uint8_t *assist_info_buf,
  * @input
  * assist_info_buf      Assist info buffer, this should be a writable buffer of size KEY_MGR_ASSIST_INFO_LEN. The buffer must be 32 bit aligned
  */
-static inline void key_mgr_ll_read_assist_info( uint8_t *assist_info_buf)
+static inline void key_mgr_ll_read_assist_info(uint8_t *assist_info_buf)
 {
     memcpy(assist_info_buf, (uint8_t *)KEYMNG_ASSIST_INFO_MEM, KEY_MGR_ASSIST_INFO_LEN);
 }
@@ -461,15 +461,15 @@ static inline void key_mgr_ll_set_xts_aes_key_len(const esp_key_mgr_key_type_t k
     }
 
     switch (key_len) {
-        case ESP_KEY_MGR_XTS_AES_LEN_128:
-            REG_CLR_BIT(KEYMNG_STATIC_REG, key_len_bit_mask);
-            break;
-        case ESP_KEY_MGR_XTS_AES_LEN_256:
-            REG_SET_BIT(KEYMNG_STATIC_REG, key_len_bit_mask);
-            break;
-        default:
-            HAL_ASSERT(false && "Unsupported key length");
-            return;
+    case ESP_KEY_MGR_XTS_AES_LEN_128:
+        REG_CLR_BIT(KEYMNG_STATIC_REG, key_len_bit_mask);
+        break;
+    case ESP_KEY_MGR_XTS_AES_LEN_256:
+        REG_SET_BIT(KEYMNG_STATIC_REG, key_len_bit_mask);
+        break;
+    default:
+        HAL_ASSERT(false && "Unsupported key length");
+        return;
     }
 }
 
@@ -492,13 +492,13 @@ static inline esp_key_mgr_key_len_t key_mgr_ll_get_xts_aes_key_len(const esp_key
     }
 
     switch (key_len_bit) {
-        case 0:
-            return ESP_KEY_MGR_XTS_AES_LEN_128;
-        case 1:
-            return ESP_KEY_MGR_XTS_AES_LEN_256;
-        default:
-            HAL_ASSERT(false && "Unsupported key length");
-            return (esp_key_mgr_key_len_t) key_len_bit;
+    case 0:
+        return ESP_KEY_MGR_XTS_AES_LEN_128;
+    case 1:
+        return ESP_KEY_MGR_XTS_AES_LEN_256;
+    default:
+        HAL_ASSERT(false && "Unsupported key length");
+        return (esp_key_mgr_key_len_t) key_len_bit;
     }
 }
 

components/esp_hal_security/esp32s2/include/hal/aes_ll.h

@@ -16,7 +16,6 @@
 extern "C" {
 #endif
 
-
 /**
  * @brief State of AES accelerator, busy, idle or done
  *
@@ -132,11 +131,10 @@ static inline void aes_ll_read_block(void *output)
     for (size_t i = 0; i < AES_BLOCK_WORDS; i++) {
         output_word = REG_READ(AES_TEXT_OUT_BASE + (i * REG_WIDTH));
         /* Memcpy to avoid potential unaligned access */
-        memcpy( (uint8_t*)output + i * 4, &output_word, sizeof(output_word));
+        memcpy((uint8_t*)output + i * 4, &output_word, sizeof(output_word));
     }
 }
 
-
 /**
  * @brief Starts block transform
  *
@@ -166,7 +164,6 @@ static inline esp_aes_state_t aes_ll_get_state(void)
     return (esp_aes_state_t)REG_READ(AES_STATE_REG);
 }
 
-
 /**
  * @brief Set mode of operation
  *
@@ -219,7 +216,7 @@ static inline void aes_ll_set_iv(const uint8_t *iv)
     uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_BASE);
     uint32_t iv_word;
 
-    for (int i = 0; i < IV_WORDS; i++ ) {
+    for (int i = 0; i < IV_WORDS; i++) {
         /* Memcpy to avoid potential unaligned access */
         memcpy(&iv_word, iv + 4 * i, sizeof(iv_word));
         REG_WRITE(&reg_addr_buf[i], iv_word);
@@ -311,8 +308,8 @@ static inline void aes_ll_gcm_set_j0(const uint8_t *j0)
     uint32_t *reg_addr_buf = (uint32_t *)(AES_J_BASE);
     uint32_t j0_word;
 
-    for (int i = 0; i < AES_BLOCK_WORDS; i++ ) {
-    /* Memcpy to avoid potential unaligned access */
+    for (int i = 0; i < AES_BLOCK_WORDS; i++) {
+        /* Memcpy to avoid potential unaligned access */
         memcpy(&j0_word, j0 + 4 * i, sizeof(j0_word));
         REG_WRITE(&reg_addr_buf[i], j0_word);
     }

components/esp_hal_security/esp32s2/include/hal/crypto_dma_ll.h

@@ -21,7 +21,7 @@ extern "C" {
 #include "soc/dport_reg.h"
 
 typedef enum {
-    CRYPTO_DMA_AES= 0,
+    CRYPTO_DMA_AES = 0,
     CRYPTO_DMA_SHA,
 } crypto_dma_mode_t;
 
@@ -127,7 +127,6 @@ static inline bool crypto_dma_ll_inlink_is_eof(void)
     return ((REG_READ(CRYPTO_DMA_INT_RAW_REG) & INT_RAW_IN_SUC_EOF) == INT_RAW_IN_SUC_EOF);
 }
 
-
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32s2/include/hal/mpi_ll.h

@@ -18,7 +18,6 @@
 extern "C" {
 #endif
 
-
 /**
  * @brief Enable the bus clock for MPI peripheral module
  *

components/esp_hal_security/esp32s3/include/hal/aes_ll.h

@@ -127,7 +127,7 @@ static inline void aes_ll_read_block(void *output)
     for (size_t i = 0; i < AES_BLOCK_WORDS; i++) {
         output_word = REG_READ(AES_TEXT_OUT_BASE + (i * REG_WIDTH));
         /* Memcpy to avoid potential unaligned access */
-        memcpy( (uint8_t*)output + i * 4, &output_word, sizeof(output_word));
+        memcpy((uint8_t*)output + i * 4, &output_word, sizeof(output_word));
     }
 }
 
@@ -140,7 +140,6 @@ static inline void aes_ll_start_transform(void)
     REG_WRITE(AES_TRIGGER_REG, 1);
 }
 
-
 /**
  * @brief Read state of AES accelerator
  *
@@ -151,7 +150,6 @@ static inline esp_aes_state_t aes_ll_get_state(void)
     return (esp_aes_state_t)REG_READ(AES_STATE_REG);
 }
 
-
 /**
  * @brief Set mode of operation
  *
@@ -204,7 +202,7 @@ static inline void aes_ll_set_iv(const uint8_t *iv)
     uint32_t *reg_addr_buf = (uint32_t *)(AES_IV_BASE);
     uint32_t iv_word;
 
-    for (int i = 0; i < IV_WORDS; i++ ) {
+    for (int i = 0; i < IV_WORDS; i++) {
         /* Memcpy to avoid potential unaligned access */
         memcpy(&iv_word, iv + 4 * i, sizeof(iv_word));
         REG_WRITE(&reg_addr_buf[i], iv_word);
@@ -255,7 +253,6 @@ static inline void aes_ll_interrupt_clear(void)
     REG_WRITE(AES_INT_CLEAR_REG, 1);
 }
 
-
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/esp32s3/include/hal/hmac_ll.h

@@ -80,7 +80,7 @@ static inline void hmac_ll_start(void)
  */
 static inline void hmac_ll_config_output(hmac_hal_output_t config)
 {
-    switch(config) {
+    switch (config) {
     case HMAC_OUTPUT_USER:
         REG_WRITE(HMAC_SET_PARA_PURPOSE_REG, HMAC_LL_EFUSE_KEY_PURPOSE_UP);
         break;
@@ -137,7 +137,7 @@ static inline void hmac_ll_wait_idle(void)
     uint32_t query;
     do {
         query = REG_READ(HMAC_QUERY_BUSY_REG);
-    } while(query != 0);
+    } while (query != 0);
 }
 
 /**

components/esp_hal_security/esp32s3/include/hal/mpi_ll.h

@@ -19,7 +19,6 @@
 extern "C" {
 #endif
 
-
 /**
  * @brief Enable the bus clock for MPI peripheral module
  *

components/esp_hal_security/hmac_hal.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/esp_hal_security/huk_hal.c

@@ -1,11 +1,10 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 // The HAL layer for Hardware Unique Key(HUK) Generator
 
-
 #include "hal/huk_hal.h"
 #include "hal/huk_ll.h"
 #include "hal/huk_types.h"

components/esp_hal_security/include/hal/aes_hal.h

@@ -25,7 +25,6 @@
 extern "C" {
 #endif
 
-
 /**
  * @brief Sets the key used for AES encryption/decryption
  *
@@ -114,7 +113,6 @@ void aes_hal_transform_dma_finish(void);
  */
 #define aes_hal_interrupt_clear() aes_ll_interrupt_clear()
 
-
 #if SOC_AES_SUPPORT_GCM
 /**
  * @brief Calculates the Hash sub-key H0 needed to start AES-GCM
@@ -159,7 +157,6 @@ void aes_hal_gcm_read_tag(uint8_t *tag, size_t tag_len);
 
 #endif //SOC_AES_SUPPORT_DMA
 
-
 #ifdef __cplusplus
 }
 #endif

components/esp_hal_security/include/hal/aes_types.h

@@ -13,7 +13,6 @@ extern "C" {
 #define ESP_AES_ENCRYPT     1
 #define ESP_AES_DECRYPT     0
 
-
 /* DMA AES working modes*/
 typedef enum {
     ESP_AES_BLOCK_MODE_ECB = 0,

components/esp_hal_security/include/hal/apm_hal.h

@@ -35,7 +35,7 @@ typedef struct {
  * @param enable     Permission enable/disable
  */
 void apm_hal_hp_peri_access_enable(apm_ll_master_id_t master_id, apm_ll_hp_peri_t hp_peri,
-                                       apm_ll_secure_mode_t sec_mode, bool enable);
+                                   apm_ll_secure_mode_t sec_mode, bool enable);
 
 /**
  * @brief Configure LP peripherals access permission for the LP CPU.
@@ -53,7 +53,7 @@ void apm_hal_lp_peri_access_enable(apm_ll_lp_peri_t lp_peri, bool enable);
  * @param regn_high_addr Configurable address range end address.
  */
 void apm_hal_peri_region_config(uint32_t regn_num, uint32_t regn_low_addr,
-                                                   uint32_t regn_high_addr);
+                                uint32_t regn_high_addr);
 
 /**
  * @brief Configure peripherals configurable address ranges.
@@ -67,7 +67,7 @@ void apm_hal_peri_region_config(uint32_t regn_num, uint32_t regn_low_addr,
  * @return           Configuration performed successfully?
  */
 int apm_hal_peri_region_pms(apm_ll_master_id_t master_id, apm_ll_secure_mode_t sec_mode,
-                                           uint32_t regn_num, uint32_t regn_pms);
+                            uint32_t regn_num, uint32_t regn_pms);
 
 /**
  * @brief Configure APM controller clock gating.
@@ -100,7 +100,6 @@ void apm_hal_dma_region_config(uint32_t regn_num, uint32_t regn_low_addr, uint32
  */
 void apm_hal_dma_region_pms(apm_hal_dma_region_config_data_t *pms_data);
 
-
 #else
 
 /**
@@ -115,7 +114,6 @@ void apm_hal_dma_region_pms(apm_hal_dma_region_config_data_t *pms_data);
     .regn_pms        = (PMS),                           \
     .filter_en       = true
 
-
 #if SOC_APM_SUPPORT_CTRL_CFG_LOCK
 #define APM_HAL_REGION_ENTRY(PATH, NUM, START, END, PMS, LOCK) \
     { APM_HAL_REGION_ENTRY_BASE(PATH, NUM, START, END, PMS), .lock_en = LOCK }

components/esp_hal_security/include/hal/ecdsa_hal.h

@@ -59,7 +59,7 @@ typedef struct {
  * @param len Length of the r_out and s_out buffer (32 bytes for SECP256R1, 24 for SECP192R1)
  */
 void ecdsa_hal_gen_signature(ecdsa_hal_config_t *conf, const uint8_t *hash,
-                            uint8_t *r_out, uint8_t *s_out, uint16_t len);
+                             uint8_t *r_out, uint8_t *s_out, uint16_t len);
 
 /**
  * @brief Verify given ECDSA signature