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feat(pvt): add pvt enable flag & change pvt limit & sleep adapt time

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This commit is contained in:
yanzihan@espressif.com
2026-03-20 15:49:09 +08:00
parent 4495f9028c
commit aa5e2df7f9
8 changed files with 89 additions and 28 deletions
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components/esp_hw_support/port/esp32c5/include/soc/rtc.h
+3 -3
View File
@@ -74,12 +74,12 @@ set pvt default param
#define PVT_CMD2 0x427
#define PVT_TARGET 0xffff
#define PVT_CLK_DIV 1
#define PVT_DELAY_NUM_HIGH 150
#define PVT_DELAY_NUM_LOW 143
#define PVT_DELAY_NUM_HIGH 154
#define PVT_DELAY_NUM_LOW 147
#define PVT_PUMP_CHANNEL_CODE 1
#define PVT_PUMP_BITMAP 22
#define PVT_PUMP_DRV 0
#define PVT_DELAY_NUM_PUMP 139
#define PVT_DELAY_NUM_PUMP 143
/**
* @brief Initialize PVT related parameters
components/esp_hw_support/port/esp32c5/pmu_pvt.c
+25
View File
@@ -26,6 +26,8 @@
#include "esp_hw_log.h"
static __attribute__((unused)) const char *TAG = "pmu_pvt";
static bool pvt_enable_flag = false;
static bool pvt_pump_enable_flag = false;
#if CONFIG_ESP_ENABLE_PVT
@@ -79,6 +81,9 @@ void pvt_auto_dbias_init(void)
{
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
if (pvt_enable_flag == true) {
return;
}
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
/*config for dbias func*/
@@ -113,6 +118,9 @@ void IRAM_ATTR pvt_func_enable(bool enable)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
if (enable) {
if (pvt_enable_flag == true) {
return;
}
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // start calibration @HP_CALI_DBIAS_DEFAULT
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
@@ -122,7 +130,12 @@ void IRAM_ATTR pvt_func_enable(bool enable)
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pvt
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // must clear @HP_CALI_DBIAS_DEFAULT
SET_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); // enable auto dbias
esp_rom_delay_us(50);
pvt_enable_flag = true;
} else {
if (pvt_enable_flag == false) {
return;
}
uint32_t pvt_hp_dbias = get_pvt_hp_dbias();
uint32_t pvt_lp_dbias = get_pvt_lp_dbias(); // update pvt_cali_dbias
SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, pvt_hp_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
@@ -131,6 +144,7 @@ void IRAM_ATTR pvt_func_enable(bool enable)
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pmu
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
pvt_enable_flag = false;
}
}
}
@@ -140,6 +154,9 @@ void charge_pump_init(void)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
/*config for charge pump*/
if (pvt_pump_enable_flag == true) {
return;
}
SET_PERI_REG_BITS(PVT_PMUP_CHANNEL_CFG_REG, PVT_PUMP_CHANNEL_CODE0, PVT_PUMP_CHANNEL_CODE, PVT_PUMP_CHANNEL_CODE0_S); //Set channel code
WRITE_PERI_REG(PVT_PMUP_BITMAP_LOW0_REG, (1 << PVT_PUMP_BITMAP)); // Select monitor cell for charge pump
SET_PERI_REG_BITS(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_DRV0, PVT_PUMP_DRV, PVT_PUMP_DRV0_S); //Configure the charging intensity
@@ -151,9 +168,17 @@ void IRAM_ATTR charge_pump_enable(bool enable)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
if (enable) {
if (pvt_pump_enable_flag == true) {
return;
}
SET_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); // enable charge pump
pvt_pump_enable_flag = true;
} else {
if (pvt_pump_enable_flag == false) {
return;
}
CLEAR_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); //disable charge pump
pvt_pump_enable_flag = false;
}
}
}
components/esp_hw_support/port/esp32c5/rtc_clk.c
+4 -8
View File
@@ -177,10 +177,6 @@ static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
clk_ll_bus_update();
esp_rom_set_cpu_ticks_per_us(cpu_freq);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
static void rtc_clk_cpu_freq_to_rc_fast(void)
@@ -190,10 +186,6 @@ static void rtc_clk_cpu_freq_to_rc_fast(void)
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
clk_ll_bus_update();
esp_rom_set_cpu_ticks_per_us(20);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
/**
@@ -464,6 +456,10 @@ FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
{
rtc_clk_cpu_set_to_default_config();
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
#ifndef BOOTLOADER_BUILD
components/esp_hw_support/port/esp32c6/pmu_pvt.c
+24
View File
@@ -28,6 +28,8 @@
static __attribute__((unused)) const char *TAG = "pmu_pvt";
#if CONFIG_ESP_ENABLE_PVT
static bool pvt_enable_flag = false;
static bool pvt_pump_enable_flag = false;
static uint8_t get_lp_hp_gap(void)
{
@@ -79,6 +81,9 @@ void pvt_auto_dbias_init(void)
{
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 3) {
if (pvt_enable_flag == true) {
return;
}
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
/*config for dbias func*/
@@ -114,6 +119,9 @@ void IRAM_ATTR pvt_func_enable(bool enable)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 3) {
if (enable) {
if (pvt_enable_flag == true) {
return;
}
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // start calibration @HP_CALI_DBIAS_DEFAUL
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
@@ -123,7 +131,11 @@ void IRAM_ATTR pvt_func_enable(bool enable)
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pvt
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // must clear @HP_CALI_DBIAS_DEFAULT
SET_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); // enable auto dbias
pvt_enable_flag = true;
} else {
if (pvt_enable_flag == false) {
return;
}
uint32_t pvt_hp_dbias = get_pvt_hp_dbias();
uint32_t pvt_lp_dbias = get_pvt_lp_dbias(); // update pvt_cali_dbias
SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, pvt_hp_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
@@ -132,6 +144,7 @@ void IRAM_ATTR pvt_func_enable(bool enable)
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pmu
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
pvt_enable_flag = false;
}
}
}
@@ -141,6 +154,9 @@ void charge_pump_init(void)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 3) {
/*config for charge pump*/
if (pvt_pump_enable_flag == true) {
return;
}
SET_PERI_REG_BITS(PVT_PMUP_CHANNEL_CFG_REG, PVT_PUMP_CHANNEL_CODE0, PVT_PUMP_CHANNEL_CODE, PVT_PUMP_CHANNEL_CODE0_S); //Set channel code
WRITE_PERI_REG(PVT_PMUP_BITMAP_LOW0_REG, (1 << PVT_PUMP_BITMAP)); // Select monitor cell for charge pump
SET_PERI_REG_BITS(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_DRV0, PVT_PUMP_DRV, PVT_PUMP_DRV0_S); //Configure the charging intensity
@@ -152,9 +168,17 @@ void IRAM_ATTR charge_pump_enable(bool enable)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 3) {
if (enable) {
if (pvt_pump_enable_flag == true) {
return;
}
SET_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); // enable charge pump
pvt_pump_enable_flag = true;
} else {
if (pvt_pump_enable_flag == false) {
return;
}
CLEAR_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); //disable charge pump
pvt_pump_enable_flag = false;
}
}
}
components/esp_hw_support/port/esp32c6/rtc_clk.c
+4 -8
View File
@@ -188,10 +188,6 @@ static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
clk_ll_cpu_set_ls_divider(div);
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
esp_rom_set_cpu_ticks_per_us(cpu_freq);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
static void rtc_clk_cpu_freq_to_rc_fast(void)
@@ -200,10 +196,6 @@ static void rtc_clk_cpu_freq_to_rc_fast(void)
clk_ll_cpu_set_ls_divider(1);
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
esp_rom_set_cpu_ticks_per_us(20);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
/**
@@ -368,6 +360,10 @@ FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
{
rtc_clk_cpu_set_to_default_config();
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
components/esp_hw_support/port/esp32c61/pmu_pvt.c
+24
View File
@@ -25,6 +25,8 @@
#include "esp_hw_log.h"
static __attribute__((unused)) const char *TAG = "pmu_pvt";
static bool pvt_enable_flag = false;
static bool pvt_pump_enable_flag = false;
#if CONFIG_ESP_ENABLE_PVT
@@ -78,6 +80,9 @@ void pvt_auto_dbias_init(void)
{
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
if (pvt_enable_flag == true) {
return;
}
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
/*config for dbias func*/
@@ -112,6 +117,9 @@ void IRAM_ATTR pvt_func_enable(bool enable)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
if (enable) {
if (pvt_enable_flag == true) {
return;
}
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // start calibration @HP_CALI_DBIAS_DEFAULT
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
@@ -121,7 +129,11 @@ void IRAM_ATTR pvt_func_enable(bool enable)
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pvt
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // must clear @HP_CALI_DBIAS_DEFAULT
SET_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); // enable auto dbias
pvt_enable_flag = true;
} else {
if (pvt_enable_flag == false) {
return;
}
uint32_t pvt_hp_dbias = get_pvt_hp_dbias();
uint32_t pvt_lp_dbias = get_pvt_lp_dbias(); // update pvt_cali_dbias
SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, pvt_hp_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
@@ -130,6 +142,7 @@ void IRAM_ATTR pvt_func_enable(bool enable)
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pmu
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
pvt_enable_flag = false;
}
}
}
@@ -139,6 +152,9 @@ void charge_pump_init(void)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
/*config for charge pump*/
if (pvt_pump_enable_flag == true) {
return;
}
SET_PERI_REG_BITS(PVT_PMUP_CHANNEL_CFG_REG, PVT_PUMP_CHANNEL_CODE0, PVT_PUMP_CHANNEL_CODE, PVT_PUMP_CHANNEL_CODE0_S); //Set channel code
WRITE_PERI_REG(PVT_PMUP_BITMAP_LOW0_REG, (1 << PVT_PUMP_BITMAP)); // Select monitor cell for charge pump
SET_PERI_REG_BITS(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_DRV0, PVT_PUMP_DRV, PVT_PUMP_DRV0_S); //Configure the charging intensity
@@ -150,9 +166,17 @@ void IRAM_ATTR charge_pump_enable(bool enable)
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
if (enable) {
if (pvt_pump_enable_flag == true) {
return;
}
SET_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); // enable charge pump
pvt_pump_enable_flag = true;
} else {
if (pvt_pump_enable_flag == false) {
return;
}
CLEAR_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); //disable charge pump
pvt_pump_enable_flag = false;
}
}
}
components/esp_hw_support/port/esp32c61/rtc_clk.c
+4 -8
View File
@@ -175,10 +175,6 @@ static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
clk_ll_bus_update();
esp_rom_set_cpu_ticks_per_us(cpu_freq);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
static void rtc_clk_cpu_freq_to_rc_fast(void)
@@ -188,10 +184,6 @@ static void rtc_clk_cpu_freq_to_rc_fast(void)
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
clk_ll_bus_update();
esp_rom_set_cpu_ticks_per_us(20);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
/**
@@ -353,6 +345,10 @@ FORCE_IRAM_ATTR void rtc_clk_cpu_set_to_default_config(void)
void rtc_clk_cpu_freq_set_xtal_for_sleep(void)
{
rtc_clk_cpu_set_to_default_config();
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
void rtc_clk_cpu_freq_to_pll_and_pll_lock_release(int cpu_freq_mhz)
components/esp_hw_support/sleep_modes.c
+1 -1
View File
@@ -219,7 +219,7 @@
#elif CONFIG_IDF_TARGET_ESP32C5
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (318)
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (56)
#define PVT_REINIT_COST_US (25)
#define PVT_REINIT_COST_US (75)
#elif CONFIG_IDF_TARGET_ESP32C61
#define DEFAULT_SLEEP_OUT_OVERHEAD_US (65)
#define DEFAULT_HARDWARE_OUT_OVERHEAD_US (70)