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Merge branch 'feat/enable_pseudo_round_support_for_aes' into 'master'
feat: enable pesudo round functionality for AES in ESP32P4 ECO5 Closes IDF-13526 and IDF-13437 See merge request espressif/esp-idf!42204
This commit is contained in:
Mahavir Jain
@@ -11,6 +11,7 @@
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#include "hal/aes_types.h"
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#include "soc/hp_sys_clkrst_struct.h"
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#include "soc/hwcrypto_reg.h"
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#include "hal/config.h"
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#ifdef __cplusplus
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extern "C" {
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@@ -256,6 +257,31 @@ static inline void aes_ll_interrupt_clear(void)
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REG_WRITE(AES_INT_CLEAR_REG, 1);
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}
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/**
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* @brief Enable the pseudo-round function during AES operations
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*
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* @param enable true to enable, false to disable
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* @param base basic number of pseudo rounds, zero if disable
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* @param increment increment number of pseudo rounds, zero if disable
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* @param key_rng_cnt update frequency of the pseudo-key, zero if disable
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*/
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static inline void aes_ll_enable_pseudo_rounds(bool enable, uint8_t base, uint8_t increment, uint8_t key_rng_cnt)
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{
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#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
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REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_EN, enable);
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if (enable) {
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REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, base);
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REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, increment);
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REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, key_rng_cnt);
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} else {
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REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_BASE, 0);
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REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_INC, 0);
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REG_SET_FIELD(AES_PSEUDO_REG, AES_PSEUDO_RNG_CNT, 0);
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}
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#endif
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}
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/**
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* @brief Continue a previous started transform
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*
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@@ -343,6 +369,18 @@ static inline void aes_ll_gcm_read_tag(uint8_t *tag)
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}
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}
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/**
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* @brief Check if the pseudo round function is supported
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*/
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static inline bool aes_ll_is_pseudo_rounds_function_supported(void)
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{
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#if HAL_CONFIG(CHIP_SUPPORT_MIN_REV) >= 300
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return true;
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#else
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return false;
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#endif
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}
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#ifdef __cplusplus
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}
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#endif
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@@ -383,6 +383,10 @@ config SOC_AES_SUPPORT_AES_256
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bool
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default y
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config SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION
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bool
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default y
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config SOC_ADC_RTC_CTRL_SUPPORTED
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bool
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default y
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@@ -126,6 +126,8 @@
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#define SOC_AES_SUPPORT_AES_128 (1)
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#define SOC_AES_SUPPORT_AES_256 (1)
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#define SOC_AES_SUPPORT_PSEUDO_ROUND_FUNCTION (1)
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/*-------------------------- ADC CAPS -------------------------------*/
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/*!< SAR ADC Module*/
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#define SOC_ADC_RTC_CTRL_SUPPORTED 1
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@@ -12,7 +12,7 @@ extern "C" {
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#endif
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/** AES_KEY_0_REG register
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* Key material key_0 configure register
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* AES key data register 0
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*/
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#define AES_KEY_0_REG (DR_REG_AES_BASE + 0x0)
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/** AES_KEY_0 : R/W; bitpos: [31:0]; default: 0;
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@@ -24,7 +24,7 @@ extern "C" {
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#define AES_KEY_0_S 0
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/** AES_KEY_1_REG register
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* Key material key_1 configure register
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* AES key data register 1
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*/
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#define AES_KEY_1_REG (DR_REG_AES_BASE + 0x4)
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/** AES_KEY_1 : R/W; bitpos: [31:0]; default: 0;
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@@ -36,7 +36,7 @@ extern "C" {
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#define AES_KEY_1_S 0
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/** AES_KEY_2_REG register
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* Key material key_2 configure register
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* AES key data register 2
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*/
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#define AES_KEY_2_REG (DR_REG_AES_BASE + 0x8)
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/** AES_KEY_2 : R/W; bitpos: [31:0]; default: 0;
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@@ -48,7 +48,7 @@ extern "C" {
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#define AES_KEY_2_S 0
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/** AES_KEY_3_REG register
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* Key material key_3 configure register
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* AES key data register 3
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*/
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#define AES_KEY_3_REG (DR_REG_AES_BASE + 0xc)
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/** AES_KEY_3 : R/W; bitpos: [31:0]; default: 0;
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@@ -60,7 +60,7 @@ extern "C" {
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#define AES_KEY_3_S 0
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/** AES_KEY_4_REG register
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* Key material key_4 configure register
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* AES key data register 4
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*/
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#define AES_KEY_4_REG (DR_REG_AES_BASE + 0x10)
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/** AES_KEY_4 : R/W; bitpos: [31:0]; default: 0;
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@@ -72,7 +72,7 @@ extern "C" {
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#define AES_KEY_4_S 0
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/** AES_KEY_5_REG register
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* Key material key_5 configure register
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* AES key data register 5
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*/
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#define AES_KEY_5_REG (DR_REG_AES_BASE + 0x14)
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/** AES_KEY_5 : R/W; bitpos: [31:0]; default: 0;
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@@ -84,7 +84,7 @@ extern "C" {
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#define AES_KEY_5_S 0
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/** AES_KEY_6_REG register
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* Key material key_6 configure register
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* AES key data register 6
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*/
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#define AES_KEY_6_REG (DR_REG_AES_BASE + 0x18)
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/** AES_KEY_6 : R/W; bitpos: [31:0]; default: 0;
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@@ -96,7 +96,7 @@ extern "C" {
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#define AES_KEY_6_S 0
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/** AES_KEY_7_REG register
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* Key material key_7 configure register
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* AES key data register 7
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*/
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#define AES_KEY_7_REG (DR_REG_AES_BASE + 0x1c)
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/** AES_KEY_7 : R/W; bitpos: [31:0]; default: 0;
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@@ -108,7 +108,7 @@ extern "C" {
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#define AES_KEY_7_S 0
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/** AES_TEXT_IN_0_REG register
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* source text material text_in_0 configure register
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* Source text data register 0
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*/
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#define AES_TEXT_IN_0_REG (DR_REG_AES_BASE + 0x20)
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/** AES_TEXT_IN_0 : R/W; bitpos: [31:0]; default: 0;
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@@ -120,7 +120,7 @@ extern "C" {
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#define AES_TEXT_IN_0_S 0
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/** AES_TEXT_IN_1_REG register
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* source text material text_in_1 configure register
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* Source text data register 1
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*/
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#define AES_TEXT_IN_1_REG (DR_REG_AES_BASE + 0x24)
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/** AES_TEXT_IN_1 : R/W; bitpos: [31:0]; default: 0;
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@@ -132,7 +132,7 @@ extern "C" {
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#define AES_TEXT_IN_1_S 0
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/** AES_TEXT_IN_2_REG register
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* source text material text_in_2 configure register
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* Source text data register 2
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*/
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#define AES_TEXT_IN_2_REG (DR_REG_AES_BASE + 0x28)
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/** AES_TEXT_IN_2 : R/W; bitpos: [31:0]; default: 0;
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@@ -144,7 +144,7 @@ extern "C" {
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#define AES_TEXT_IN_2_S 0
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/** AES_TEXT_IN_3_REG register
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* source text material text_in_3 configure register
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* Source text data register 3
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*/
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#define AES_TEXT_IN_3_REG (DR_REG_AES_BASE + 0x2c)
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/** AES_TEXT_IN_3 : R/W; bitpos: [31:0]; default: 0;
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@@ -156,7 +156,7 @@ extern "C" {
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#define AES_TEXT_IN_3_S 0
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/** AES_TEXT_OUT_0_REG register
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* result text material text_out_0 configure register
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* Result text data register 0
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*/
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#define AES_TEXT_OUT_0_REG (DR_REG_AES_BASE + 0x30)
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/** AES_TEXT_OUT_0 : R/W; bitpos: [31:0]; default: 0;
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@@ -168,7 +168,7 @@ extern "C" {
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#define AES_TEXT_OUT_0_S 0
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/** AES_TEXT_OUT_1_REG register
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* result text material text_out_1 configure register
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* Result text data register 1
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*/
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#define AES_TEXT_OUT_1_REG (DR_REG_AES_BASE + 0x34)
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/** AES_TEXT_OUT_1 : R/W; bitpos: [31:0]; default: 0;
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@@ -180,7 +180,7 @@ extern "C" {
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#define AES_TEXT_OUT_1_S 0
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/** AES_TEXT_OUT_2_REG register
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* result text material text_out_2 configure register
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* Result text data register 2
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*/
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#define AES_TEXT_OUT_2_REG (DR_REG_AES_BASE + 0x38)
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/** AES_TEXT_OUT_2 : R/W; bitpos: [31:0]; default: 0;
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@@ -192,7 +192,7 @@ extern "C" {
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#define AES_TEXT_OUT_2_S 0
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/** AES_TEXT_OUT_3_REG register
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* result text material text_out_3 configure register
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* Result text data register 3
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*/
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#define AES_TEXT_OUT_3_REG (DR_REG_AES_BASE + 0x3c)
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/** AES_TEXT_OUT_3 : R/W; bitpos: [31:0]; default: 0;
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@@ -204,12 +204,19 @@ extern "C" {
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#define AES_TEXT_OUT_3_S 0
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/** AES_MODE_REG register
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* AES Mode register
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* Defines key length and encryption / decryption
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*/
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#define AES_MODE_REG (DR_REG_AES_BASE + 0x40)
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/** AES_MODE : R/W; bitpos: [2:0]; default: 0;
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* This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1:
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* Reserved, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: Reserved, 3'd6: AES-DE-256.
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* Configures the key length and encryption / decryption of the AES accelerator.
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* 0: AES-128 encryption
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* 1: AES-192 encryption
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* 2: AES-256 encryption
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* 3: Reserved
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* 4: AES-128 decryption
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* 5: AES-192 decryption
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* 6: AES-256 decryption
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* 7: Reserved
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*/
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#define AES_MODE 0x00000007U
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#define AES_MODE_M (AES_MODE_V << AES_MODE_S)
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@@ -230,11 +237,13 @@ extern "C" {
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#define AES_ENDIAN_S 0
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/** AES_TRIGGER_REG register
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* AES trigger register
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* Operation start controlling register
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*/
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#define AES_TRIGGER_REG (DR_REG_AES_BASE + 0x48)
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/** AES_TRIGGER : WT; bitpos: [0]; default: 0;
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* Set this bit to start AES calculation.
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* Configures whether or not to start AES operation.
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* 0: No effect
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* 1: Start
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*/
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#define AES_TRIGGER (BIT(0))
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#define AES_TRIGGER_M (AES_TRIGGER_V << AES_TRIGGER_S)
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@@ -242,12 +251,21 @@ extern "C" {
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#define AES_TRIGGER_S 0
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/** AES_STATE_REG register
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* AES state register
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* Operation status register
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*/
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#define AES_STATE_REG (DR_REG_AES_BASE + 0x4c)
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/** AES_STATE : RO; bitpos: [1:0]; default: 0;
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* Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0:
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* idle, 1: busy, 2: calculation_done.
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* Represents the working status of the AES accelerator.
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* In Typical AES working mode:
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* 0: IDLE
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* 1: WORK
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* 2: No effect
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* 3: No effect
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* In DMA-AES working mode:
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* 0: IDLE
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* 1: WORK
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* 2: DONE
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* 3: No effect
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*/
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#define AES_STATE 0x00000003U
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#define AES_STATE_M (AES_STATE_V << AES_STATE_S)
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@@ -279,11 +297,13 @@ extern "C" {
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#define AES_T0_MEM_SIZE_BYTES 16
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/** AES_DMA_ENABLE_REG register
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* DMA-AES working mode register
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* Selects the working mode of the AES accelerator
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*/
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#define AES_DMA_ENABLE_REG (DR_REG_AES_BASE + 0x90)
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/** AES_DMA_ENABLE : R/W; bitpos: [0]; default: 0;
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* 1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
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* Configures the working mode of the AES accelerator.
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* 0: Typical AES
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* 1: DMA-AES
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*/
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#define AES_DMA_ENABLE (BIT(0))
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#define AES_DMA_ENABLE_M (AES_DMA_ENABLE_V << AES_DMA_ENABLE_S)
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@@ -291,12 +311,20 @@ extern "C" {
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#define AES_DMA_ENABLE_S 0
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/** AES_BLOCK_MODE_REG register
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* AES cipher block mode register
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* Defines the block cipher mode
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*/
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#define AES_BLOCK_MODE_REG (DR_REG_AES_BASE + 0x94)
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/** AES_BLOCK_MODE : R/W; bitpos: [2:0]; default: 0;
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* Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB,
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* 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
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* Configures the block cipher mode of the AES accelerator operating under the DMA-AES
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* working mode.
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* 0: ECB (Electronic Code Block)
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* 1: CBC (Cipher Block Chaining)
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* 2: OFB (Output FeedBack)
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* 3: CTR (Counter)
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* 4: CFB8 (8-bit Cipher FeedBack)
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* 5: CFB128 (128-bit Cipher FeedBack)
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* 6: GCM
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* 7: Reserved
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*/
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#define AES_BLOCK_MODE 0x00000007U
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#define AES_BLOCK_MODE_M (AES_BLOCK_MODE_V << AES_BLOCK_MODE_S)
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@@ -304,11 +332,12 @@ extern "C" {
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#define AES_BLOCK_MODE_S 0
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/** AES_BLOCK_NUM_REG register
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* AES block number register
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* Block number configuration register
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*/
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#define AES_BLOCK_NUM_REG (DR_REG_AES_BASE + 0x98)
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/** AES_BLOCK_NUM : R/W; bitpos: [31:0]; default: 0;
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* Those bits stores the number of Plaintext/ciphertext block.
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* Represents the Block Number of plaintext or ciphertext when the AES accelerator
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* operates under the DMA-AES working mode. For details, see Section . "
|
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*/
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#define AES_BLOCK_NUM 0xFFFFFFFFU
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#define AES_BLOCK_NUM_M (AES_BLOCK_NUM_V << AES_BLOCK_NUM_S)
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@@ -316,11 +345,13 @@ extern "C" {
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#define AES_BLOCK_NUM_S 0
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/** AES_INC_SEL_REG register
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* Standard incrementing function configure register
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* Standard incrementing function register
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*/
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#define AES_INC_SEL_REG (DR_REG_AES_BASE + 0x9c)
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/** AES_INC_SEL : R/W; bitpos: [0]; default: 0;
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* This bit decides the standard incrementing function. 0: INC32. 1: INC128.
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* Configures the Standard Incrementing Function for CTR block operation.
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* 0: INC_32
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* 1: INC_128
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*/
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#define AES_INC_SEL (BIT(0))
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#define AES_INC_SEL_M (AES_INC_SEL_V << AES_INC_SEL_S)
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@@ -364,11 +395,13 @@ extern "C" {
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#define AES_CONTINUE_S 0
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/** AES_INT_CLEAR_REG register
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* AES Interrupt clear register
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* DMA-AES interrupt clear register
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*/
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#define AES_INT_CLEAR_REG (DR_REG_AES_BASE + 0xac)
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/** AES_INT_CLEAR : WT; bitpos: [0]; default: 0;
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* Set this bit to clear the AES interrupt.
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* Configures whether or not to clear AES interrupt.
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* 0: No effect
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* 1: Clear
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*/
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#define AES_INT_CLEAR (BIT(0))
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#define AES_INT_CLEAR_M (AES_INT_CLEAR_V << AES_INT_CLEAR_S)
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@@ -376,11 +409,13 @@ extern "C" {
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#define AES_INT_CLEAR_S 0
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/** AES_INT_ENA_REG register
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* AES Interrupt enable register
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* DMA-AES interrupt enable register
|
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*/
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#define AES_INT_ENA_REG (DR_REG_AES_BASE + 0xb0)
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/** AES_INT_ENA : R/W; bitpos: [0]; default: 0;
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* Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
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* Configures whether or not to enable AES interrupt.
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* 0: Disable
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* 1: Enable
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*/
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#define AES_INT_ENA (BIT(0))
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#define AES_INT_ENA_M (AES_INT_ENA_V << AES_INT_ENA_S)
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@@ -391,27 +426,86 @@ extern "C" {
|
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* AES version control register
|
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*/
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#define AES_DATE_REG (DR_REG_AES_BASE + 0xb4)
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/** AES_DATE : R/W; bitpos: [29:0]; default: 538513936;
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/** AES_DATE : R/W; bitpos: [27:0]; default: 36774000;
|
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* This bits stores the version information of AES.
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*/
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#define AES_DATE 0x3FFFFFFFU
|
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#define AES_DATE 0x0FFFFFFFU
|
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#define AES_DATE_M (AES_DATE_V << AES_DATE_S)
|
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#define AES_DATE_V 0x3FFFFFFFU
|
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#define AES_DATE_V 0x0FFFFFFFU
|
||||
#define AES_DATE_S 0
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||||
/** AES_DMA_EXIT_REG register
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* AES-DMA exit config
|
||||
* Operation exit controlling register
|
||||
*/
|
||||
#define AES_DMA_EXIT_REG (DR_REG_AES_BASE + 0xb8)
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/** AES_DMA_EXIT : WT; bitpos: [0]; default: 0;
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||||
* Set this register to leave calculation done stage. Recommend to use it after
|
||||
* software finishes reading DMA's output buffer.
|
||||
* Configures whether or not to exit AES operation.
|
||||
* 0: No effect
|
||||
* 1: Exit
|
||||
* Only valid for DMA-AES operation.
|
||||
*/
|
||||
#define AES_DMA_EXIT (BIT(0))
|
||||
#define AES_DMA_EXIT_M (AES_DMA_EXIT_V << AES_DMA_EXIT_S)
|
||||
#define AES_DMA_EXIT_V 0x00000001U
|
||||
#define AES_DMA_EXIT_S 0
|
||||
|
||||
/** AES_RX_RESET_REG register
|
||||
* AES-DMA reset rx-fifo register
|
||||
*/
|
||||
#define AES_RX_RESET_REG (DR_REG_AES_BASE + 0xc0)
|
||||
/** AES_RX_RESET : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to reset rx_fifo under dma_aes working mode.
|
||||
*/
|
||||
#define AES_RX_RESET (BIT(0))
|
||||
#define AES_RX_RESET_M (AES_RX_RESET_V << AES_RX_RESET_S)
|
||||
#define AES_RX_RESET_V 0x00000001U
|
||||
#define AES_RX_RESET_S 0
|
||||
|
||||
/** AES_TX_RESET_REG register
|
||||
* AES-DMA reset tx-fifo register
|
||||
*/
|
||||
#define AES_TX_RESET_REG (DR_REG_AES_BASE + 0xc4)
|
||||
/** AES_TX_RESET : WT; bitpos: [0]; default: 0;
|
||||
* Set this bit to reset tx_fifo under dma_aes working mode.
|
||||
*/
|
||||
#define AES_TX_RESET (BIT(0))
|
||||
#define AES_TX_RESET_M (AES_TX_RESET_V << AES_TX_RESET_S)
|
||||
#define AES_TX_RESET_V 0x00000001U
|
||||
#define AES_TX_RESET_S 0
|
||||
|
||||
/** AES_PSEUDO_REG register
|
||||
* AES PSEUDO function configure register
|
||||
*/
|
||||
#define AES_PSEUDO_REG (DR_REG_AES_BASE + 0xd0)
|
||||
/** AES_PSEUDO_EN : R/W; bitpos: [0]; default: 0;
|
||||
* This bit decides whether the pseudo round function is enable or not.
|
||||
*/
|
||||
#define AES_PSEUDO_EN (BIT(0))
|
||||
#define AES_PSEUDO_EN_M (AES_PSEUDO_EN_V << AES_PSEUDO_EN_S)
|
||||
#define AES_PSEUDO_EN_V 0x00000001U
|
||||
#define AES_PSEUDO_EN_S 0
|
||||
/** AES_PSEUDO_BASE : R/W; bitpos: [4:1]; default: 2;
|
||||
* Those bits decides the basic number of pseudo round number.
|
||||
*/
|
||||
#define AES_PSEUDO_BASE 0x0000000FU
|
||||
#define AES_PSEUDO_BASE_M (AES_PSEUDO_BASE_V << AES_PSEUDO_BASE_S)
|
||||
#define AES_PSEUDO_BASE_V 0x0000000FU
|
||||
#define AES_PSEUDO_BASE_S 1
|
||||
/** AES_PSEUDO_INC : R/W; bitpos: [6:5]; default: 2;
|
||||
* Those bits decides the increment number of pseudo round number
|
||||
*/
|
||||
#define AES_PSEUDO_INC 0x00000003U
|
||||
#define AES_PSEUDO_INC_M (AES_PSEUDO_INC_V << AES_PSEUDO_INC_S)
|
||||
#define AES_PSEUDO_INC_V 0x00000003U
|
||||
#define AES_PSEUDO_INC_S 5
|
||||
/** AES_PSEUDO_RNG_CNT : R/W; bitpos: [9:7]; default: 7;
|
||||
* Those bits decides the update frequency of the pseudo-key.
|
||||
*/
|
||||
#define AES_PSEUDO_RNG_CNT 0x00000007U
|
||||
#define AES_PSEUDO_RNG_CNT_M (AES_PSEUDO_RNG_CNT_V << AES_PSEUDO_RNG_CNT_S)
|
||||
#define AES_PSEUDO_RNG_CNT_V 0x00000007U
|
||||
#define AES_PSEUDO_RNG_CNT_S 7
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user