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https://github.com/espressif/esp-idf.git
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Merge branch 'feat/support_esp32s31_pmu_basic' into 'master'
feat(esp_hw_support): support esp32s31 pmu basic Closes IDF-14642 See merge request espressif/esp-idf!45494
This commit is contained in:
Wu Zheng Hui
@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2017-2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2017-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -9,14 +9,7 @@
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#include "soc/chip_revision.h"
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#include "hal/efuse_hal.h"
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32C2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3 // TODO: IDF-5645
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#include "soc/rtc_cntl_reg.h"
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#else
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#include "soc/lp_wdt_reg.h"
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#include "soc/lp_timer_reg.h"
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#include "soc/lp_analog_peri_reg.h"
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#include "soc/pmu_reg.h"
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#endif
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#include "soc/rtc_cntl_periph.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "hal/clk_tree_ll.h"
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@@ -163,7 +156,16 @@ __attribute__((weak)) void bootloader_clock_configure(void)
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SET_PERI_REG_MASK(LP_ANALOG_PERI_LP_INT_CLR_REG, LP_ANALOG_PERI_LP_INT_CLR_REG); /* BROWN_OUT */
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SET_PERI_REG_MASK(LP_WDT_INT_CLR_REG, LP_WDT_LP_WDT_INT_CLR); /* WDT */
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#elif CONFIG_IDF_TARGET_ESP32S31
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//ESP32S31-TODO IDF-14696
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// CLR ENA
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CLEAR_PERI_REG_MASK(RTC_WDT_INT_ENA_REG, RTC_WDT_SUPER_WDT_INT_ENA); /* SWD */
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CLEAR_PERI_REG_MASK(LP_ANA_LP_INT_ENA_REG, LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */
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CLEAR_PERI_REG_MASK(RTC_WDT_INT_ENA_REG, RTC_WDT_LP_WDT_INT_ENA); /* WDT */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_WAKEUP_INT_ENA); /* SLP_REJECT */
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CLEAR_PERI_REG_MASK(PMU_HP_INT_ENA_REG, PMU_SOC_SLEEP_REJECT_INT_ENA); /* SLP_WAKEUP */
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// SET CLR
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SET_PERI_REG_MASK(RTC_WDT_INT_CLR_REG, RTC_WDT_SUPER_WDT_INT_CLR); /* SWD */
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SET_PERI_REG_MASK(LP_ANA_LP_INT_CLR_REG, LP_ANA_BOD_MODE0_LP_INT_ENA); /* BROWN_OUT */
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SET_PERI_REG_MASK(RTC_WDT_INT_CLR_REG, RTC_WDT_LP_WDT_INT_CLR); /* WDT */
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#else
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REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
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REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
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@@ -45,7 +45,7 @@
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assert(buffer != NULL);
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for (size_t i = 0; i < length; i++) {
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#if SOC_RTC_TIMER_V2_SUPPORTED
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#if !SOC_RTC_TIMER_V1
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random = REG_READ(WDEV_RND_REG);
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start = esp_cpu_get_cycle_count();
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do {
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -636,8 +636,8 @@ static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in
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static inline void gpio_ll_force_hold_all(void)
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{
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// WT flag, it gets self-cleared after the configuration is done
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PMU.imm_pad_hold_all.tie_high_hp_pad_hold_all = 1;
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PMU.imm_pad_hold_all.tie_high_lp_pad_hold_all = 1;
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PMU.imm.pad_hold_all.tie_high_hp_pad_hold_all = 1;
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PMU.imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
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}
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/**
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@@ -647,8 +647,8 @@ static inline void gpio_ll_force_hold_all(void)
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static inline void gpio_ll_force_unhold_all(void)
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{
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// WT flag, it gets self-cleared after the configuration is done
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PMU.imm_pad_hold_all.tie_low_hp_pad_hold_all = 1;
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PMU.imm_pad_hold_all.tie_low_lp_pad_hold_all = 1;
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PMU.imm.pad_hold_all.tie_low_hp_pad_hold_all = 1;
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PMU.imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
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}
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/**
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -16,7 +16,29 @@
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extern "C" {
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#endif
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// TODO: ["ESP32S31"] IDF-14653
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typedef struct {
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pmu_dev_t *dev;
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} pmu_hal_context_t;
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void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
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uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
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void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
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uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
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void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal);
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void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal);
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void pmu_hal_hp_set_sleep_modem_backup_enable(pmu_hal_context_t *hal);
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void pmu_hal_hp_set_sleep_modem_backup_disable(pmu_hal_context_t *hal);
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void pmu_hal_hp_set_modem_active_backup_enable(pmu_hal_context_t *hal);
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void pmu_hal_hp_set_modem_active_backup_disable(pmu_hal_context_t *hal);
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#ifdef __cplusplus
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}
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
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||||
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -16,13 +16,782 @@
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#include "soc/pmu_struct.h"
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#include "hal/pmu_types.h"
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#include "hal/misc.h"
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#include "hal/config.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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// TODO: ["ESP32S31"] IDF-14642
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FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_interrupt_raw(pmu_dev_t *hw)
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{
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return hw->lp_ext.int_raw.val;
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}
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FORCE_INLINE_ATTR void pmu_ll_lp_clear_intsts_mask(pmu_dev_t *hw, uint32_t mask)
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{
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hw->lp_ext.int_clr.val = mask;
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}
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FORCE_INLINE_ATTR void pmu_ll_lp_clear_sw_intr_status(pmu_dev_t *hw)
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{
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hw->lp_ext.int_clr.hp_sw_trigger = 1;
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}
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FORCE_INLINE_ATTR void pmu_ll_lp_enable_sw_intr(pmu_dev_t *hw, bool enable)
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{
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hw->lp_ext.int_ena.hp_sw_trigger = enable;
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}
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FORCE_INLINE_ATTR void pmu_ll_lp_trigger_sw_intr(pmu_dev_t *hw)
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{
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hw->hp_lp_cpu_comm.lp_trigger_hp = 1;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_trigger_sw_intr(pmu_dev_t *hw)
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{
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hw->hp_lp_cpu_comm.hp_trigger_lp = 1;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t flag)
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{
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hw->hp_sys[mode].dig_power.val = flag;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func0, uint32_t icg_func1)
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{
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hw->hp_sys[mode].icg[0].icg_func = icg_func0;
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hw->hp_sys[mode].icg[1].icg_func = icg_func1;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_apb(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t bitmap0, uint32_t bitmap1)
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{
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hw->hp_sys[mode].icg[0].icg_apb = bitmap0;
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hw->hp_sys[mode].icg[1].icg_apb = bitmap1;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_modem(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t code)
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{
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hw->hp_sys[mode].icg_modem.code = code;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_c_channel_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool ena)
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{
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hw->hp_sys[mode].syscntl.c_channel = ena ? 1 : 0;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_uart_wakeup_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool wakeup_en)
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{
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hw->hp_sys[mode].syscntl.uart_wakeup_en = wakeup_en;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_lp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
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{
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hw->hp_sys[mode].syscntl.lp_pad_hold_all = hold_all;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_hold_all_hp_pad(pmu_dev_t *hw, pmu_hp_mode_t mode, bool hold_all)
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{
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hw->hp_sys[mode].syscntl.hp_pad_hold_all = hold_all;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_pad_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
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{
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hw->hp_sys[mode].syscntl.dig_pad_slp_sel = slp_sel;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_pause_watchdog(pmu_dev_t *hw, pmu_hp_mode_t mode, bool pause_wdt)
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{
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hw->hp_sys[mode].syscntl.dig_pause_wdt = pause_wdt;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_cpu_stall(pmu_dev_t *hw, pmu_hp_mode_t mode, bool cpu_stall)
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{
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hw->hp_sys[mode].syscntl.dig_cpu_stall = cpu_stall;
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}
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/**
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* @brief Set the power domain that needs to be powered down in the clock power
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*
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* @param hw Beginning address of the peripheral registers.
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* @param mode The pmu mode
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* @param flag Clock power domain flag
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*
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* @return None
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*/
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FORCE_INLINE_ATTR void pmu_ll_hp_set_clk_power(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t xpd_flag)
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{
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hw->hp_sys[mode].clk_power.val = xpd_flag;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_xtal_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_xtal)
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{
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hw->hp_sys[mode].xtal.xpd_xtal = xpd_xtal;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd_bias)
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{
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hw->hp_sys[mode].bias.xpd_bias = xpd_bias;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_dbg_atten(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t value)
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{
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hw->hp_sys[mode].bias.dbg_atten = value;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_current_power_off(pmu_dev_t *hw, pmu_hp_mode_t mode, bool off)
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{
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hw->hp_sys[mode].bias.pd_cur = off;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool en)
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{
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hw->hp_sys[mode].bias.bias_sleep = en;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_retention_param(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t param)
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{
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hw->hp_sys[mode].backup_cfg.val = param;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_enable(pmu_dev_t *hw)
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{
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hw->hp_sys[PMU_MODE_HP_ACTIVE].backup_cfg.hp_sleep2active_backup_en = 1;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_active_backup_disable(pmu_dev_t *hw)
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{
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hw->hp_sys[PMU_MODE_HP_ACTIVE].backup_cfg.hp_sleep2active_backup_en = 0;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_enable(pmu_dev_t *hw)
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{
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hw->hp_sys[PMU_MODE_HP_ACTIVE].backup_cfg.hp_modem2active_backup_en = 1;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_active_backup_disable(pmu_dev_t *hw)
|
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{
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hw->hp_sys[PMU_MODE_HP_ACTIVE].backup_cfg.hp_modem2active_backup_en = 0;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_enable(pmu_dev_t *hw)
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{
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hw->hp_sys[PMU_MODE_HP_MODEM].backup_cfg.hp_sleep2modem_backup_en = 1;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_to_modem_backup_disable(pmu_dev_t *hw)
|
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{
|
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hw->hp_sys[PMU_MODE_HP_MODEM].backup_cfg.hp_sleep2modem_backup_en = 0;
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}
|
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FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_enable(pmu_dev_t *hw)
|
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{
|
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hw->hp_sys[PMU_MODE_HP_SLEEP].backup_cfg.hp_active2sleep_backup_en = 1;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_active_to_sleep_backup_disable(pmu_dev_t *hw)
|
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{
|
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hw->hp_sys[PMU_MODE_HP_SLEEP].backup_cfg.hp_active2sleep_backup_en = 0;
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}
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FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_enable(pmu_dev_t *hw)
|
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{
|
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hw->hp_sys[PMU_MODE_HP_SLEEP].backup_cfg.hp_modem2sleep_backup_en = 1;
|
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}
|
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|
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FORCE_INLINE_ATTR void pmu_ll_hp_set_modem_to_sleep_backup_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_sys[PMU_MODE_HP_SLEEP].backup_cfg.hp_modem2sleep_backup_en = 0;
|
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}
|
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|
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FORCE_INLINE_ATTR void pmu_ll_hp_set_backup_icg_func(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t icg_func0, uint32_t icg_func1)
|
||||
{
|
||||
hw->hp_sys[mode].backup_clock[0] = icg_func0;
|
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hw->hp_sys[mode].backup_clock[1] = icg_func1;
|
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}
|
||||
|
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FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_nodiv(pmu_dev_t *hw, pmu_hp_mode_t mode, bool sysclk_nodiv)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_nodiv = sysclk_nodiv;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_enable(pmu_dev_t *hw, pmu_hp_mode_t mode, bool icg_sysclk_en)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_sysclk_en = icg_sysclk_en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.sysclk_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_icg_sysclk_slp_sel(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.icg_slp_sel = slp_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_dig_sysclk(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t sysclk_sel)
|
||||
{
|
||||
hw->hp_sys[mode].sysclk.dig_sysclk_sel = sysclk_sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_lp_dbias_voltage(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t voltage)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_HP_ACTIVE);
|
||||
hw->hp_sys[mode].regulator0.lp_dbias_vol = voltage;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_hp_dbias_voltage(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t voltage)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_HP_ACTIVE);
|
||||
hw->hp_sys[mode].regulator0.hp_dbias_vol = voltage;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias_select(pmu_dev_t *hw, pmu_hp_mode_t mode, bool sel)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_HP_ACTIVE);
|
||||
hw->hp_sys[mode].regulator0.dbias_sel = sel;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias_init(pmu_dev_t *hw, pmu_hp_mode_t mode, bool init)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_HP_ACTIVE);
|
||||
hw->hp_sys[mode].regulator0.dig_dbias_init = init;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_mem_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_xpd(pmu_dev_t *hw, pmu_hp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_logic_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_logic_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_sleep_memory_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.slp_mem_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_dbias(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->hp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_hp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->hp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_slp_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool slp_xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_xpd = slp_xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.xpd = xpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_sleep_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t slp_dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.slp_dbias = slp_dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_dbias(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t dbias)
|
||||
{
|
||||
hw->lp_sys[mode].regulator0.dbias = dbias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_regulator_driver_bar(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t drv_b)
|
||||
{
|
||||
hw->lp_sys[mode].regulator1.drv_b = drv_b;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_xtal_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_xtal)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].xtal.xpd_xtal = xpd_xtal;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dig_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t flag)
|
||||
{
|
||||
hw->lp_sys[mode].dig_power.val = flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t xpd_flag)
|
||||
{
|
||||
hw->lp_sys[mode].clk_power.val = xpd_flag;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_clk_power(pmu_dev_t *hw, pmu_lp_mode_t mode)
|
||||
{
|
||||
return hw->lp_sys[mode].clk_power.val;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_xpd(pmu_dev_t *hw, pmu_lp_mode_t mode, bool xpd_bias)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.xpd_bias = xpd_bias;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_dbg_atten(pmu_dev_t *hw, pmu_lp_mode_t mode, uint32_t value)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.dbg_atten = value;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_current_power_off(pmu_dev_t *hw, pmu_lp_mode_t mode, bool off)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.pd_cur = off;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_bias_sleep_enable(pmu_dev_t *hw, pmu_lp_mode_t mode, bool en)
|
||||
{
|
||||
HAL_ASSERT(mode == PMU_MODE_LP_SLEEP);
|
||||
hw->lp_sys[mode].bias.bias_sleep = en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_clk_power(pmu_dev_t *hw, uint32_t flag0, uint32_t flag1)
|
||||
{
|
||||
hw->imm.clk_power_0.val = flag0;
|
||||
hw->imm.clk_power_1.val = flag1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_icg_slp_sel(pmu_dev_t *hw, bool slp_sel)
|
||||
{
|
||||
if (slp_sel) {
|
||||
hw->imm.sleep_sysclk.tie_high_icg_slp_sel = 1;
|
||||
} else {
|
||||
hw->imm.sleep_sysclk.tie_low_icg_slp_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_sysclk_sel(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_sysclk_sel = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_switch(pmu_dev_t *hw, bool update)
|
||||
{
|
||||
hw->imm.sleep_sysclk.update_dig_icg_switch = update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_func(pmu_dev_t *hw, bool icg_func_update)
|
||||
{
|
||||
hw->imm.hp_func_icg.update_dig_icg_func_en = icg_func_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_apb(pmu_dev_t *hw, bool icg_apb_update)
|
||||
{
|
||||
hw->imm.hp_apb_icg.update_dig_icg_apb_en = icg_apb_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_update_dig_icg_modem_code(pmu_dev_t *hw, bool icg_modem_update)
|
||||
{
|
||||
hw->imm.modem_icg.update_dig_icg_modem_en = icg_modem_update;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_rootclk_sel(pmu_dev_t *hw, bool rootclk_sel)
|
||||
{
|
||||
if (rootclk_sel) {
|
||||
hw->imm.lp_icg.tie_high_lp_rootclk_sel = 1;
|
||||
} else {
|
||||
hw->imm.lp_icg.tie_low_lp_rootclk_sel = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_hp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_hp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_hp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_imm_set_lp_pad_hold_all(pmu_dev_t *hw, bool hold_all)
|
||||
{
|
||||
if (hold_all) {
|
||||
hw->imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
|
||||
} else {
|
||||
hw->imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool rst)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_top_reset = rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool iso)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_top_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_up(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpu)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_top_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_reset(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_rst)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_top_no_reset = no_rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_no_isolate(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool no_iso)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_top_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_power_force_power_down(pmu_dev_t *hw, pmu_hp_power_domain_t domain, bool fpd)
|
||||
{
|
||||
hw->power.hp_pd[domain].force_top_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_reset(pmu_dev_t *hw, bool rst)
|
||||
{
|
||||
hw->power.lp_peri.force_lp_peri_reset = rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_isolate(pmu_dev_t *hw, bool iso)
|
||||
{
|
||||
hw->power.lp_peri.force_lp_peri_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_up(pmu_dev_t *hw, bool fpu)
|
||||
{
|
||||
hw->power.lp_peri.force_lp_peri_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_reset(pmu_dev_t *hw, bool no_rst)
|
||||
{
|
||||
hw->power.lp_peri.force_lp_peri_no_reset = no_rst;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_no_isolate(pmu_dev_t *hw, bool no_iso)
|
||||
{
|
||||
hw->power.lp_peri.force_lp_peri_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_power_force_power_down(pmu_dev_t *hw, bool fpd)
|
||||
{
|
||||
hw->power.lp_peri.force_lp_peri_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_isolate(pmu_dev_t *hw, uint32_t iso)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_iso = iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_down(pmu_dev_t *hw, uint32_t fpd)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_pd = fpd;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_no_isolate(pmu_dev_t *hw, uint32_t no_iso)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_no_iso = no_iso;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_memory_power_up(pmu_dev_t *hw, uint32_t fpu)
|
||||
{
|
||||
hw->power.mem_cntl.force_hp_mem_pu = fpu;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_enable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl0.sleep_req = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_enable(pmu_dev_t *hw, uint32_t reject)
|
||||
{
|
||||
hw->wakeup.cntl1.sleep_reject_ena = reject;
|
||||
hw->wakeup.cntl0.slp_reject_en = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reject_disable(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl0.slp_reject_en = 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_wakeup_enable(pmu_dev_t *hw, uint32_t wakeup)
|
||||
{
|
||||
hw->wakeup.cntl2 = wakeup;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_sleep_protect_mode(pmu_dev_t *hw, int mode)
|
||||
{
|
||||
hw->wakeup.cntl3.sleep_prt_sel = mode;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, hp_min_slp_val, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
hw->wakeup.cntl4.slp_reject_cause_clr = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_modem_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->wakeup.cntl5.modem_wait_target = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_modem_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.cntl5.modem_wait_target;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl7, ana_wait_target);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_wakeup(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.soc_wakeup == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR bool pmu_ll_hp_is_sleep_reject(pmu_dev_t *hw)
|
||||
{
|
||||
return (hw->hp_ext.int_raw.soc_sleep_reject == 1);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_sw_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.sw = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_wakeup_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.soc_wakeup = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_clear_reject_intr_status(pmu_dev_t *hw)
|
||||
{
|
||||
hw->hp_ext.int_clr.soc_sleep_reject = 1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_enable_sw_intr(pmu_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->hp_ext.int_ena.sw = enable;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_wakeup_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_reject_cause(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->wakeup.status1;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_min_sleep_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl3, lp_min_slp_val, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_modify_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_modify_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, modify_icg_cntl_wait);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_switch_icg_cntl_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_switch_icg_cntl_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->hp_ext.clk_cntl, switch_icg_cntl_wait);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_down_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.powerdown_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_down_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.powerdown_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_analog_wait_target_cycle(pmu_dev_t *hw, uint32_t slow_clk_cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target, slow_clk_cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_analog_wait_target_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->wakeup.cntl5, lp_ana_wait_target);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_xtal_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_xtal_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_xtal_stable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_set_pll_stable_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable, cycle);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_pll_stable_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(hw->power.clk_wait, wait_pll_stable);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer1.powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_lp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer1.powerup_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_supply_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.wait_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_supply_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.wait_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_digital_power_up_wait_cycle(pmu_dev_t *hw, uint32_t cycle)
|
||||
{
|
||||
hw->power.wait_timer0.powerup_timer = cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_hp_get_digital_power_up_wait_cycle(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->power.wait_timer0.powerup_timer;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.dg_lp_iso_wait_timer = isolate_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_lp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.dg_lp_rst_wait_timer = reset_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_isolate_wait_cycle(pmu_dev_t *hw, uint32_t isolate_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.dg_hp_iso_wait_timer = isolate_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void pmu_ll_hp_set_reset_wait_cycle(pmu_dev_t *hw, uint32_t reset_wait_cycle)
|
||||
{
|
||||
hw->power.wait_timer2.dg_hp_rst_wait_timer = reset_wait_cycle;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t pmu_ll_get_sysclk_sleep_select_state(pmu_dev_t *hw)
|
||||
{
|
||||
return hw->clk_state0.sysclk_slp_sel;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get ext1 wakeup source status
|
||||
* @return The lower 8 bits of the returned value are the bitmap of
|
||||
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
|
||||
*/
|
||||
static inline uint32_t pmu_ll_ext1_get_wakeup_status(void)
|
||||
{
|
||||
return REG_GET_FIELD(PMU_EXT_WAKEUP_ST_REG, PMU_EXT_WAKEUP_STATUS);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the ext1 wakeup source status
|
||||
*/
|
||||
static inline void pmu_ll_ext1_clear_wakeup_status(void)
|
||||
{
|
||||
REG_SET_BIT(PMU_EXT_WAKEUP_CNTL_REG, PMU_EXT_WAKEUP_STATUS_CLR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the wake-up LP_IO of the ext1 wake-up source
|
||||
* @param io_mask wakeup LP_IO bitmap, bit 0~7 corresponds to LP_IO 0~7
|
||||
* @param level_mask 0: Wake the chip when all selected GPIOs go low
|
||||
* 1: Wake the chip when any of the selected GPIOs go high
|
||||
*/
|
||||
static inline void pmu_ll_ext1_set_wakeup_pins(uint32_t io_mask, int level_mask)
|
||||
{
|
||||
REG_SET_FIELD(PMU_EXT_WAKEUP_SEL_REG, PMU_EXT_WAKEUP_SEL, io_mask);
|
||||
REG_SET_FIELD(PMU_EXT_WAKEUP_LV_REG, PMU_EXT_WAKEUP_LV, level_mask);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear all ext1 wakup-source setting
|
||||
*/
|
||||
static inline void pmu_ll_ext1_clear_wakeup_pins(void)
|
||||
{
|
||||
REG_SET_FIELD(PMU_EXT_WAKEUP_SEL_REG, PMU_EXT_WAKEUP_SEL, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get ext1 wakeup source setting
|
||||
* @return The lower 8 bits of the returned value are the bitmap of
|
||||
* the wakeup source status, bit 0~7 corresponds to LP_IO 0~7
|
||||
*/
|
||||
static inline uint32_t pmu_ll_ext1_get_wakeup_pins(void)
|
||||
{
|
||||
return REG_GET_FIELD(PMU_EXT_WAKEUP_SEL_REG, PMU_EXT_WAKEUP_SEL);
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -1,9 +1,82 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU (ESP32-S31 specific part)
|
||||
|
||||
// TODO: ["ESP32S31"] IDF-14653
|
||||
#include "soc/soc.h"
|
||||
#include "esp_attr.h"
|
||||
#include "hal/pmu_hal.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
void IRAM_ATTR pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_hp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_hp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t IRAM_ATTR pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_hp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_hp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void IRAM_ATTR pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle)
|
||||
{
|
||||
pmu_ll_lp_set_digital_power_supply_wait_cycle(hal->dev, power_supply_wait_cycle);
|
||||
pmu_ll_lp_set_digital_power_up_wait_cycle(hal->dev, power_up_wait_cycle);
|
||||
}
|
||||
|
||||
uint32_t IRAM_ATTR pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal)
|
||||
{
|
||||
uint32_t power_supply_wait_cycle = pmu_ll_lp_get_digital_power_supply_wait_cycle(hal->dev);
|
||||
uint32_t power_up_wait_cycle = pmu_ll_lp_get_digital_power_up_wait_cycle(hal->dev);
|
||||
return power_supply_wait_cycle + power_up_wait_cycle;
|
||||
}
|
||||
|
||||
void IRAM_ATTR pmu_hal_hp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle)
|
||||
{
|
||||
pmu_ll_hp_set_isolate_wait_cycle(hal->dev, isolate_wait_cycle);
|
||||
pmu_ll_hp_set_reset_wait_cycle(hal->dev, reset_wait_cycle);
|
||||
}
|
||||
|
||||
void IRAM_ATTR pmu_hal_lp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle)
|
||||
{
|
||||
pmu_ll_lp_set_isolate_wait_cycle(hal->dev, isolate_wait_cycle);
|
||||
pmu_ll_lp_set_reset_wait_cycle(hal->dev, reset_wait_cycle);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_active_to_sleep_backup_enable(hal->dev);
|
||||
pmu_ll_hp_set_sleep_to_active_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_active_backup_disable(hal->dev);
|
||||
pmu_ll_hp_set_active_to_sleep_backup_disable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_modem_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_sleep_to_modem_backup_disable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_enable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_modem_to_active_backup_enable(hal->dev);
|
||||
}
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_disable(pmu_hal_context_t *hal)
|
||||
{
|
||||
pmu_ll_hp_set_modem_to_active_backup_disable(hal->dev);
|
||||
}
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -43,6 +43,15 @@ typedef enum {
|
||||
PMU_HP_PD_HPMEM = 2,
|
||||
PMU_HP_PD_CPU = 3,
|
||||
} pmu_hp_power_domain_t;
|
||||
#elif SOC_IS(ESP32S31)
|
||||
typedef enum {
|
||||
PMU_HP_PD_TOP = 0, /*!< Power domain of digital top */
|
||||
PMU_HP_PD_HPALIVE,
|
||||
PMU_HP_PD_MODEMPWR,
|
||||
PMU_HP_PD_HPCPU,
|
||||
PMU_HP_PD_HPCNNT,
|
||||
PMU_HP_PD_MODEM
|
||||
} pmu_hp_power_domain_t;
|
||||
#else
|
||||
typedef enum {
|
||||
PMU_HP_PD_TOP = 0, /*!< Power domain of digital top */
|
||||
|
||||
@@ -8,8 +8,9 @@
|
||||
The `esp_hal_rtc_timer` component provides a **unified Hardware Abstraction Layer** for RTC Timer peripherals across all ESP-IDF supported targets. This HAL abstracts hardware differences between legacy RTC timer implementations (in RTC_CNTL peripheral) and modern low-power timer implementations, providing a consistent API for wakeup timer configuration and RTC time reading across different ESP chip families.
|
||||
|
||||
The component consolidates timer functionality from two different hardware implementations:
|
||||
- **SOC_RTC_TIMER_V1_SUPPORTED**: Legacy RTC timer functionality in RTC_CNTL peripheral (ESP32, ESP32C2, ESP32C3, ESP32S2, ESP32S3)
|
||||
- **SOC_RTC_TIMER_V2_SUPPORTED**: Newer LP timer peripheral (ESP32C5, ESP32C6, ESP32C61, ESP32H2, ESP32H21, ESP32H4, ESP32P4)
|
||||
- **SOC_RTC_TIMER_V1**: Legacy RTC timer functionality in RTC_CNTL peripheral for ESP32, ESP32C2, ESP32C3, ESP32S2, ESP32S3
|
||||
- **SOC_RTC_TIMER_V2**: LP timer peripheral for ESP32C5, ESP32C6, ESP32C61, ESP32H2, ESP32H21, ESP32H4, ESP32P4
|
||||
- **SOC_RTC_TIMER_V3**: RTC timer peripheral for ESP32S31
|
||||
|
||||
### Unified HAL API (All Chips)
|
||||
- Wakeup timer configuration via `rtc_timer_hal_set_wakeup_time()`
|
||||
|
||||
@@ -1,19 +1,18 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-P4 RTC_Timer register operations
|
||||
// The LL layer for ESP32S31 RTC_Timer register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "soc/soc.h"
|
||||
#include "soc/lp_timer_struct.h"
|
||||
#include "soc/lp_timer_reg.h"
|
||||
#include "soc/lp_system_reg.h"
|
||||
#include "soc/rtc_timer_struct.h"
|
||||
#include "soc/rtc_timer_reg.h"
|
||||
#include "hal/misc.h"
|
||||
#include "esp_attr.h"
|
||||
|
||||
@@ -21,7 +20,106 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// TODO: ["ESP32S31"] IDF-14642
|
||||
FORCE_INLINE_ATTR void rtc_timer_ll_set_alarm_target(rtc_timer_dev_t *dev, uint8_t timer_id, uint64_t value)
|
||||
{
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].hi, target_hi, (value >> 32) & 0xFFFF);
|
||||
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->target[timer_id].lo, target_lo, value & 0xFFFFFFFF);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_timer_ll_set_target_enable(rtc_timer_dev_t *dev, uint8_t timer_id, bool en)
|
||||
{
|
||||
dev->target[timer_id].hi.enable = en;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_low(rtc_timer_dev_t *dev, uint8_t timer_id)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].lo, counter_lo);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_counter_value_high(rtc_timer_dev_t *dev, uint8_t timer_id)
|
||||
{
|
||||
return HAL_FORCE_READ_U32_REG_FIELD(dev->counter[timer_id].hi, counter_hi);
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void rtc_timer_ll_counter_snapshot(rtc_timer_dev_t *dev)
|
||||
{
|
||||
dev->update.main_timer_update = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear alarm interrupt status
|
||||
*
|
||||
* @param dev LP timer peripheral instance
|
||||
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rtc_timer_ll_clear_alarm_intr_status(rtc_timer_dev_t *dev, uint8_t timer_id)
|
||||
{
|
||||
if (timer_id == 0) {
|
||||
dev->int_clr.soc_wakeup_int_clr = 1;
|
||||
} else if (timer_id == 1) {
|
||||
dev->lp_int_clr.main_timer_lp_int_clr = 1;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get interrupt raw status
|
||||
*
|
||||
* @param dev LP timer peripheral instance
|
||||
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
|
||||
* @return Interrupt raw status value
|
||||
*/
|
||||
FORCE_INLINE_ATTR uint32_t rtc_timer_ll_get_intr_raw(rtc_timer_dev_t *dev, uint8_t timer_id)
|
||||
{
|
||||
if (timer_id == 0) {
|
||||
return dev->int_raw.val;
|
||||
} else if (timer_id == 1) {
|
||||
return dev->lp_int_raw.val;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable/disable alarm interrupt
|
||||
*
|
||||
* @param dev LP timer peripheral instance
|
||||
* @param timer_id Timer ID (0 for main timer, 1 for LP timer)
|
||||
* @param enable Enable or disable interrupt
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rtc_timer_ll_alarm_intr_enable(rtc_timer_dev_t *dev, uint8_t timer_id, bool enable)
|
||||
{
|
||||
if (timer_id == 0) {
|
||||
dev->int_ena.soc_wakeup_int_ena = enable;
|
||||
} else if (timer_id == 1) {
|
||||
dev->lp_int_ena.main_timer_lp_int_ena = enable;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set wakeup timer value
|
||||
*
|
||||
* @param timer_id Timer ID
|
||||
* @param ticks Timer value in RTC slow clock ticks
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rtc_timer_ll_set_wakeup_time(uint8_t timer_id, uint64_t ticks)
|
||||
{
|
||||
rtc_timer_ll_clear_alarm_intr_status(&RTC_TIMER, timer_id);
|
||||
rtc_timer_ll_set_alarm_target(&RTC_TIMER, timer_id, ticks);
|
||||
rtc_timer_ll_set_target_enable(&RTC_TIMER, timer_id, true);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get current RTC timer cycle count
|
||||
*
|
||||
* @param timer_id Timer ID
|
||||
* @return Current RTC time in RTC slow clock ticks
|
||||
*/
|
||||
FORCE_INLINE_ATTR uint64_t rtc_timer_ll_get_cycle_count(uint8_t timer_id)
|
||||
{
|
||||
rtc_timer_ll_counter_snapshot(&RTC_TIMER);
|
||||
uint32_t lo = rtc_timer_ll_get_counter_value_low(&RTC_TIMER, timer_id);
|
||||
uint32_t hi = rtc_timer_ll_get_counter_value_high(&RTC_TIMER, timer_id);
|
||||
return ((uint64_t)hi << 32) | lo;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -1,327 +0,0 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "hal/misc.h"
|
||||
#include "hal/wdt_types.h"
|
||||
#include "soc/rtc_cntl_periph.h"
|
||||
#include "soc/efuse_reg.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_assert.h"
|
||||
|
||||
#include "esp32s31/rom/ets_sys.h"
|
||||
|
||||
// TODO: ["ESP32S31"] IDF-14636
|
||||
|
||||
/* The value that needs to be written to LP_WDT_WPROTECT_REG to write-enable the wdt registers */
|
||||
#define LP_WDT_WKEY_VALUE 0x50D83AA1
|
||||
/* The value that needs to be written to LP_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
|
||||
#define LP_WDT_SWD_WKEY_VALUE 0x50D83AA1
|
||||
|
||||
/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
|
||||
#define LP_WDT_RESET_LENGTH_100_NS 0
|
||||
#define LP_WDT_RESET_LENGTH_200_NS 1
|
||||
#define LP_WDT_RESET_LENGTH_300_NS 2
|
||||
#define LP_WDT_RESET_LENGTH_400_NS 3
|
||||
#define LP_WDT_RESET_LENGTH_500_NS 4
|
||||
#define LP_WDT_RESET_LENGTH_800_NS 5
|
||||
#define LP_WDT_RESET_LENGTH_1600_NS 6
|
||||
#define LP_WDT_RESET_LENGTH_3200_NS 7
|
||||
|
||||
#define LP_WDT_STG_SEL_OFF 0
|
||||
#define LP_WDT_STG_SEL_INT 1
|
||||
#define LP_WDT_STG_SEL_RESET_CPU 2
|
||||
#define LP_WDT_STG_SEL_RESET_SYSTEM 3
|
||||
#define LP_WDT_STG_SEL_RESET_RTC 4
|
||||
|
||||
//Type check wdt_stage_action_t
|
||||
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == LP_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
|
||||
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == LP_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
|
||||
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == LP_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
|
||||
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == LP_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
|
||||
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_RTC == LP_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
|
||||
//Type check wdt_reset_sig_length_t
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == LP_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == LP_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == LP_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == LP_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == LP_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == LP_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == LP_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == LP_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
|
||||
/**
|
||||
* @brief Enable the RWDT
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_enable(lp_wdt_dev_t *hw)
|
||||
{
|
||||
hw->config0.wdt_en = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable the RWDT
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @note This function does not disable the flashboot mode. Therefore, given that
|
||||
* the MWDT is disabled using this function, a timeout can still occur
|
||||
* if the flashboot mode is simultaneously enabled.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_disable(lp_wdt_dev_t *hw)
|
||||
{
|
||||
hw->config0.wdt_en = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the RWDT is enabled
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @return True if RTC WDT is enabled
|
||||
*/
|
||||
FORCE_INLINE_ATTR bool lpwdt_ll_check_if_enabled(lp_wdt_dev_t *hw)
|
||||
{
|
||||
return (hw->config0.wdt_en) ? true : false;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure a particular stage of the RWDT
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param stage Which stage to configure
|
||||
* @param timeout Number of timer ticks for the stage to timeout (see note).
|
||||
* @param behavior What action to take when the stage times out
|
||||
*
|
||||
* @note The value of of RWDT stage 0 timeout register is special, in
|
||||
* that an implicit multiplier is applied to that value to produce
|
||||
* and effective timeout tick value. The multiplier is dependent
|
||||
* on an EFuse value. Therefore, when configuring stage 0, the valid
|
||||
* values for the timeout argument are:
|
||||
* - If Efuse value is 0, any even number between [2,2*UINT32_MAX]
|
||||
* - If Efuse value is 1, any multiple of 4 between [4,4*UINT32_MAX]
|
||||
* - If Efuse value is 2, any multiple of 8 between [8,8*UINT32_MAX]
|
||||
* - If Efuse value is 3, any multiple of 16 between [16,16*UINT32_MAX]
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_config_stage(lp_wdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior)
|
||||
{
|
||||
switch (stage) {
|
||||
case WDT_STAGE0:
|
||||
hw->config0.wdt_stg0 = behavior;
|
||||
//Account of implicty multiplier applied to stage 0 timeout tick config value
|
||||
hw->config1.val = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL));
|
||||
break;
|
||||
case WDT_STAGE1:
|
||||
hw->config0.wdt_stg1 = behavior;
|
||||
hw->config2.val = timeout_ticks;
|
||||
break;
|
||||
case WDT_STAGE2:
|
||||
hw->config0.wdt_stg2 = behavior;
|
||||
hw->config3.val = timeout_ticks;
|
||||
break;
|
||||
case WDT_STAGE3:
|
||||
hw->config0.wdt_stg3 = behavior;
|
||||
hw->config4.val = timeout_ticks;
|
||||
break;
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable a particular stage of the RWDT
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param stage Which stage to disable
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_disable_stage(lp_wdt_dev_t *hw, wdt_stage_t stage)
|
||||
{
|
||||
switch (stage) {
|
||||
case WDT_STAGE0:
|
||||
hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
|
||||
break;
|
||||
case WDT_STAGE1:
|
||||
hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
|
||||
break;
|
||||
case WDT_STAGE2:
|
||||
hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
|
||||
break;
|
||||
case WDT_STAGE3:
|
||||
hw->config0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
|
||||
break;
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the length of the CPU reset action
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param length Length of CPU reset signal
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_set_cpu_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
|
||||
{
|
||||
hw->config0.wdt_cpu_reset_length = length;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the length of the system reset action
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param length Length of system reset signal
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_set_sys_reset_length(lp_wdt_dev_t *hw, wdt_reset_sig_length_t length)
|
||||
{
|
||||
hw->config0.wdt_sys_reset_length = length;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable the RWDT flashboot mode.
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
|
||||
*
|
||||
* @note Flashboot mode is independent and can trigger a WDT timeout event if the
|
||||
* WDT's enable bit is set to 0. Flashboot mode for RWDT is automatically enabled
|
||||
* on flashboot, and should be disabled by software when flashbooting completes.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_set_flashboot_en(lp_wdt_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param enable True to enable CPU0 to be reset, false to disable.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_set_procpu_reset_en(lp_wdt_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param enable True to enable CPU1 to be reset, false to disable.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_set_appcpu_reset_en(lp_wdt_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable the RWDT pause during sleep functionality
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param enable True to enable, false to disable.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_set_pause_in_sleep_en(lp_wdt_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable/Disable chip reset on RWDT timeout.
|
||||
*
|
||||
* A chip reset also resets the analog portion of the chip. It will appear as a
|
||||
* POWERON reset rather than an RTC reset.
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param enable True to enable, false to disable.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_en(lp_wdt_dev_t *hw, bool enable)
|
||||
{
|
||||
// hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set width of chip reset signal
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param width Width of chip reset signal in terms of number of RTC_SLOW_CLK cycles
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_set_chip_reset_width(lp_wdt_dev_t *hw, uint32_t width)
|
||||
{
|
||||
// HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Feed the RWDT
|
||||
*
|
||||
* Resets the current timer count and current stage.
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_feed(lp_wdt_dev_t *hw)
|
||||
{
|
||||
// hw->feed.rtc_wdt_feed = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable write protection of the RWDT registers
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_write_protect_enable(lp_wdt_dev_t *hw)
|
||||
{
|
||||
hw->wprotect.val = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable write protection of the RWDT registers
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_write_protect_disable(lp_wdt_dev_t *hw)
|
||||
{
|
||||
hw->wprotect.val = LP_WDT_WKEY_VALUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the RWDT interrupt.
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param enable True to enable RWDT interrupt, false to disable.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_set_intr_enable(lp_wdt_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the RWDT interrupt has been triggered
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @return True if the RWDT interrupt was triggered
|
||||
*/
|
||||
FORCE_INLINE_ATTR bool lpwdt_ll_check_intr_status(lp_wdt_dev_t *hw)
|
||||
{
|
||||
return (hw->int_st.lp_wdt_int_st) ? true : false;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the RWDT interrupt status.
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lpwdt_ll_clear_intr_status(lp_wdt_dev_t *hw)
|
||||
{
|
||||
hw->int_clr.lp_wdt_int_clr = 1;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,10 +1,8 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
// The LL layer for RTC(LP) watchdog register operations.
|
||||
// Note that most of the register operations in this layer are non-atomic operations.
|
||||
|
||||
#pragma once
|
||||
|
||||
@@ -12,70 +10,321 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "hal/lpwdt_ll.h"
|
||||
#include <stdlib.h>
|
||||
#include <stdbool.h>
|
||||
#include "hal/misc.h"
|
||||
#include "hal/wdt_types.h"
|
||||
#include "soc/rtc_cntl_periph.h"
|
||||
#include "soc/efuse_reg.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp_assert.h"
|
||||
|
||||
// TODO: ["ESP32S31"] IDF-14656
|
||||
#include "esp32s31/rom/ets_sys.h"
|
||||
|
||||
typedef lp_wdt_dev_t rwdt_dev_t;
|
||||
// TODO: ["ESP32S31"] IDF-14636
|
||||
|
||||
#define RWDT_DEV_GET() &LP_WDT
|
||||
/* The value that needs to be written to RTC_WDT_WPROTECT_REG to write-enable the wdt registers */
|
||||
#define RTC_WDT_WKEY_VALUE 0x50D83AA1
|
||||
/* The value that needs to be written to RTC_WDT_SWD_WPROTECT_REG to write-enable the swd registers */
|
||||
#define RTC_WDT_SWD_WKEY_VALUE 0x50D83AA1
|
||||
|
||||
#define rwdt_ll_enable(hw) \
|
||||
lpwdt_ll_enable(hw)
|
||||
/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH and RTC_CNTL_WDT_SYS_RESET_LENGTH */
|
||||
#define RTC_WDT_RESET_LENGTH_100_NS 0
|
||||
#define RTC_WDT_RESET_LENGTH_200_NS 1
|
||||
#define RTC_WDT_RESET_LENGTH_300_NS 2
|
||||
#define RTC_WDT_RESET_LENGTH_400_NS 3
|
||||
#define RTC_WDT_RESET_LENGTH_500_NS 4
|
||||
#define RTC_WDT_RESET_LENGTH_800_NS 5
|
||||
#define RTC_WDT_RESET_LENGTH_1600_NS 6
|
||||
#define RTC_WDT_RESET_LENGTH_3200_NS 7
|
||||
|
||||
#define rwdt_ll_disable(hw) \
|
||||
lpwdt_ll_disable(hw)
|
||||
#define RTC_WDT_STG_SEL_OFF 0
|
||||
#define RTC_WDT_STG_SEL_INT 1
|
||||
#define RTC_WDT_STG_SEL_RESET_CPU 2
|
||||
#define RTC_WDT_STG_SEL_RESET_SYSTEM 3
|
||||
#define RTC_WDT_STG_SEL_RESET_RTC 4
|
||||
|
||||
#define rwdt_ll_check_if_enabled(hw) \
|
||||
lpwdt_ll_check_if_enabled(hw)
|
||||
//Type check wdt_stage_action_t
|
||||
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_OFF == RTC_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
|
||||
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_INT == RTC_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
|
||||
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_CPU == RTC_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
|
||||
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_SYSTEM == RTC_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
|
||||
ESP_STATIC_ASSERT(WDT_STAGE_ACTION_RESET_RTC == RTC_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
|
||||
//Type check wdt_reset_sig_length_t
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_100ns == RTC_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_200ns == RTC_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_300ns == RTC_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_400ns == RTC_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_500ns == RTC_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_800ns == RTC_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_1_6us == RTC_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
ESP_STATIC_ASSERT(WDT_RESET_SIG_LENGTH_3_2us == RTC_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
|
||||
|
||||
#define rwdt_ll_config_stage(hw, stage, timeout_ticks, behavior) \
|
||||
lpwdt_ll_config_stage(hw, stage, timeout_ticks, behavior)
|
||||
typedef rtc_wdt_dev_t rwdt_dev_t;
|
||||
|
||||
#define rwdt_ll_disable_stage(hw, stage) \
|
||||
lpwdt_ll_disable_stage(hw, stage)
|
||||
#define RWDT_DEV_GET() &RTC_WDT
|
||||
|
||||
#define rwdt_ll_set_cpu_reset_length(hw, length) \
|
||||
lpwdt_ll_set_cpu_reset_length(hw, length)
|
||||
/**
|
||||
* @brief Enable the RWDT
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_enable(rwdt_dev_t *hw)
|
||||
{
|
||||
hw->config0.wdt_en = 1;
|
||||
}
|
||||
|
||||
#define rwdt_ll_set_sys_reset_length(hw, length) \
|
||||
lpwdt_ll_set_sys_reset_length(hw, length)
|
||||
/**
|
||||
* @brief Disable the RWDT
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @note This function does not disable the flashboot mode. Therefore, given that
|
||||
* the MWDT is disabled using this function, a timeout can still occur
|
||||
* if the flashboot mode is simultaneously enabled.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_disable(rwdt_dev_t *hw)
|
||||
{
|
||||
hw->config0.wdt_en = 0;
|
||||
}
|
||||
|
||||
#define rwdt_ll_set_flashboot_en(hw, enable) \
|
||||
lpwdt_ll_set_flashboot_en(hw, enable)
|
||||
/**
|
||||
* @brief Check if the RWDT is enabled
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @return True if RTC WDT is enabled
|
||||
*/
|
||||
FORCE_INLINE_ATTR bool rwdt_ll_check_if_enabled(rwdt_dev_t *hw)
|
||||
{
|
||||
return (hw->config0.wdt_en) ? true : false;
|
||||
}
|
||||
|
||||
#define rwdt_ll_set_procpu_reset_en(hw, enable) \
|
||||
lpwdt_ll_set_procpu_reset_en(hw, enable)
|
||||
/**
|
||||
* @brief Configure a particular stage of the RWDT
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param stage Which stage to configure
|
||||
* @param timeout Number of timer ticks for the stage to timeout (see note).
|
||||
* @param behavior What action to take when the stage times out
|
||||
*
|
||||
* @note The value of of RWDT stage 0 timeout register is special, in
|
||||
* that an implicit multiplier is applied to that value to produce
|
||||
* and effective timeout tick value. The multiplier is dependent
|
||||
* on an EFuse value. Therefore, when configuring stage 0, the valid
|
||||
* values for the timeout argument are:
|
||||
* - If Efuse value is 0, any even number between [2,2*UINT32_MAX]
|
||||
* - If Efuse value is 1, any multiple of 4 between [4,4*UINT32_MAX]
|
||||
* - If Efuse value is 2, any multiple of 8 between [8,8*UINT32_MAX]
|
||||
* - If Efuse value is 3, any multiple of 16 between [16,16*UINT32_MAX]
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_config_stage(rwdt_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior)
|
||||
{
|
||||
switch (stage) {
|
||||
case WDT_STAGE0:
|
||||
hw->config0.wdt_stg0 = behavior;
|
||||
//Account of implicty multiplier applied to stage 0 timeout tick config value
|
||||
hw->config1.val = timeout_ticks >> (1 + REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_WDT_DELAY_SEL));
|
||||
break;
|
||||
case WDT_STAGE1:
|
||||
hw->config0.wdt_stg1 = behavior;
|
||||
hw->config2.val = timeout_ticks;
|
||||
break;
|
||||
case WDT_STAGE2:
|
||||
hw->config0.wdt_stg2 = behavior;
|
||||
hw->config3.val = timeout_ticks;
|
||||
break;
|
||||
case WDT_STAGE3:
|
||||
hw->config0.wdt_stg3 = behavior;
|
||||
hw->config4.val = timeout_ticks;
|
||||
break;
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
#define rwdt_ll_set_appcpu_reset_en(hw, enable) \
|
||||
lpwdt_ll_set_appcpu_reset_en(hw, enable)
|
||||
/**
|
||||
* @brief Disable a particular stage of the RWDT
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param stage Which stage to disable
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_disable_stage(rwdt_dev_t *hw, wdt_stage_t stage)
|
||||
{
|
||||
switch (stage) {
|
||||
case WDT_STAGE0:
|
||||
hw->config0.wdt_stg0 = WDT_STAGE_ACTION_OFF;
|
||||
break;
|
||||
case WDT_STAGE1:
|
||||
hw->config0.wdt_stg1 = WDT_STAGE_ACTION_OFF;
|
||||
break;
|
||||
case WDT_STAGE2:
|
||||
hw->config0.wdt_stg2 = WDT_STAGE_ACTION_OFF;
|
||||
break;
|
||||
case WDT_STAGE3:
|
||||
hw->config0.wdt_stg3 = WDT_STAGE_ACTION_OFF;
|
||||
break;
|
||||
default:
|
||||
abort();
|
||||
}
|
||||
}
|
||||
|
||||
#define rwdt_ll_set_pause_in_sleep_en(hw, enable) \
|
||||
lpwdt_ll_set_pause_in_sleep_en(hw, enable)
|
||||
/**
|
||||
* @brief Set the length of the CPU reset action
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param length Length of CPU reset signal
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_set_cpu_reset_length(rwdt_dev_t *hw, wdt_reset_sig_length_t length)
|
||||
{
|
||||
hw->config0.wdt_cpu_reset_length = length;
|
||||
}
|
||||
|
||||
#define rwdt_ll_set_chip_reset_en(hw, enable) \
|
||||
lpwdt_ll_set_chip_reset_en(hw, enable)
|
||||
/**
|
||||
* @brief Set the length of the system reset action
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param length Length of system reset signal
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_set_sys_reset_length(rwdt_dev_t *hw, wdt_reset_sig_length_t length)
|
||||
{
|
||||
hw->config0.wdt_sys_reset_length = length;
|
||||
}
|
||||
|
||||
#define rwdt_ll_set_chip_reset_width(hw, width) \
|
||||
lpwdt_ll_set_chip_reset_width(hw, width)
|
||||
/**
|
||||
* @brief Enable/Disable the RWDT flashboot mode.
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
|
||||
*
|
||||
* @note Flashboot mode is independent and can trigger a WDT timeout event if the
|
||||
* WDT's enable bit is set to 0. Flashboot mode for RWDT is automatically enabled
|
||||
* on flashboot, and should be disabled by software when flashbooting completes.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_set_flashboot_en(rwdt_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->config0.wdt_flashboot_mod_en = (enable) ? 1 : 0;
|
||||
}
|
||||
|
||||
#define rwdt_ll_feed(hw) \
|
||||
lpwdt_ll_feed(hw)
|
||||
/**
|
||||
* @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param enable True to enable CPU0 to be reset, false to disable.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_set_procpu_reset_en(rwdt_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->config0.wdt_procpu_reset_en = (enable) ? 1 : 0;
|
||||
}
|
||||
|
||||
#define rwdt_ll_write_protect_enable(hw) \
|
||||
lpwdt_ll_write_protect_enable(hw)
|
||||
/**
|
||||
* @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param enable True to enable CPU1 to be reset, false to disable.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_set_appcpu_reset_en(rwdt_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->config0.wdt_appcpu_reset_en = (enable) ? 1 : 0;
|
||||
}
|
||||
|
||||
#define rwdt_ll_write_protect_disable(hw) \
|
||||
lpwdt_ll_write_protect_disable(hw)
|
||||
/**
|
||||
* @brief Enable/Disable the RWDT pause during sleep functionality
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param enable True to enable, false to disable.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_set_pause_in_sleep_en(rwdt_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->config0.wdt_pause_in_slp = (enable) ? 1 : 0;
|
||||
}
|
||||
|
||||
#define rwdt_ll_set_intr_enable(hw, enable) \
|
||||
lpwdt_ll_set_intr_enable(hw, enable)
|
||||
/**
|
||||
* @brief Enable/Disable chip reset on RWDT timeout.
|
||||
*
|
||||
* A chip reset also resets the analog portion of the chip. It will appear as a
|
||||
* POWERON reset rather than an RTC reset.
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param enable True to enable, false to disable.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_en(rwdt_dev_t *hw, bool enable)
|
||||
{
|
||||
// hw->config0.wdt_chip_reset_en = (enable) ? 1 : 0;
|
||||
}
|
||||
|
||||
#define rwdt_ll_check_intr_status(hw) \
|
||||
lpwdt_ll_check_intr_status(hw)
|
||||
/**
|
||||
* @brief Set width of chip reset signal
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param width Width of chip reset signal in terms of number of RTC_SLOW_CLK cycles
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_set_chip_reset_width(rwdt_dev_t *hw, uint32_t width)
|
||||
{
|
||||
// HAL_FORCE_MODIFY_U32_REG_FIELD(hw->config0, wdt_chip_reset_width, width);
|
||||
}
|
||||
|
||||
#define rwdt_ll_clear_intr_status(hw) \
|
||||
lpwdt_ll_clear_intr_status(hw)
|
||||
/**
|
||||
* @brief Feed the RWDT
|
||||
*
|
||||
* Resets the current timer count and current stage.
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_feed(rwdt_dev_t *hw)
|
||||
{
|
||||
// hw->feed.rtc_wdt_feed = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable write protection of the RWDT registers
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_write_protect_enable(rwdt_dev_t *hw)
|
||||
{
|
||||
hw->wprotect.val = 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable write protection of the RWDT registers
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_write_protect_disable(rwdt_dev_t *hw)
|
||||
{
|
||||
hw->wprotect.val = RTC_WDT_WKEY_VALUE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable the RWDT interrupt.
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @param enable True to enable RWDT interrupt, false to disable.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_set_intr_enable(rwdt_dev_t *hw, bool enable)
|
||||
{
|
||||
hw->int_ena.lp_wdt_int_ena = (enable) ? 1 : 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if the RWDT interrupt has been triggered
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
* @return True if the RWDT interrupt was triggered
|
||||
*/
|
||||
FORCE_INLINE_ATTR bool rwdt_ll_check_intr_status(rwdt_dev_t *hw)
|
||||
{
|
||||
return (hw->int_st.lp_wdt_int_st) ? true : false;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear the RWDT interrupt status.
|
||||
*
|
||||
* @param hw Start address of the peripheral registers.
|
||||
*/
|
||||
FORCE_INLINE_ATTR void rwdt_ll_clear_intr_status(rwdt_dev_t *hw)
|
||||
{
|
||||
hw->int_clr.lp_wdt_int_clr = 1;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
||||
@@ -75,8 +75,8 @@ typedef enum {
|
||||
#define RTC_GPIO_TRIG_EN (PMU_GPIO_WAKEUP_EN)
|
||||
#endif
|
||||
|
||||
#if SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#define RTC_TIMER_TRIG_EN PMU_LP_TIMER_WAKEUP_EN //!< Timer wakeup
|
||||
#if !SOC_RTC_TIMER_V1
|
||||
#define RTC_TIMER_TRIG_EN PMU_RTC_TIMER_WAKEUP_EN //!< Timer wakeup
|
||||
#else
|
||||
#define RTC_TIMER_TRIG_EN 0
|
||||
#endif
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -131,15 +131,6 @@ use together with RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT
|
||||
#define RTC_CNTL_RTC_DBIAS_LIGHTSLEEP_0V6 5
|
||||
#define RTC_CNTL_DIG_DBIAS_LIGHTSLEEP_0V6 5
|
||||
|
||||
/*
|
||||
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
|
||||
storing in efuse (based on ATE 5k ECO3 chips)
|
||||
*/
|
||||
#define K_RTC_MID_MUL10000 215
|
||||
#define K_DIG_MID_MUL10000 213
|
||||
#define V_RTC_MID_MUL10000 10800
|
||||
#define V_DIG_MID_MUL10000 10860
|
||||
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
@@ -152,9 +143,6 @@ typedef struct rtc_cpu_freq_config_s {
|
||||
|
||||
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
|
||||
|
||||
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
|
||||
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
|
||||
|
||||
#define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
|
||||
#define RTC_CAL_8MD256 _Pragma ("GCC warning \"'RTC_CAL_8MD256' macro is deprecated\"") CLK_CAL_RC_FAST_D256
|
||||
#define RTC_CAL_32K_OSC_SLOW _Pragma ("GCC warning \"'RTC_CAL_32K_OSC_SLOW' macro is deprecated\"") CLK_CAL_32K_OSC_SLOW
|
||||
|
||||
@@ -154,9 +154,6 @@ typedef struct rtc_cpu_freq_config_s {
|
||||
|
||||
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
|
||||
|
||||
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
|
||||
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
|
||||
|
||||
#define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
|
||||
#define RTC_CAL_8MD256 _Pragma ("GCC warning \"'RTC_CAL_8MD256' macro is deprecated\"") CLK_CAL_RC_FAST_D256
|
||||
#define RTC_CAL_32K_XTAL _Pragma ("GCC warning \"'RTC_CAL_32K_XTAL' macro is deprecated\"") CLK_CAL_32K_XTAL
|
||||
|
||||
@@ -49,9 +49,6 @@ extern "C" {
|
||||
|
||||
#define MHZ (1000000)
|
||||
|
||||
#define OTHER_BLOCKS_POWERUP 1
|
||||
#define OTHER_BLOCKS_WAIT 1
|
||||
|
||||
/* Delays for various clock sources to be enabled/switched.
|
||||
* All values are in microseconds.
|
||||
*/
|
||||
@@ -60,45 +57,9 @@ extern "C" {
|
||||
#define SOC_DELAY_RC_FAST_ENABLE 50
|
||||
#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5
|
||||
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 128
|
||||
|
||||
/* Various delays to be programmed into power control state machines */
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1)
|
||||
#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4)
|
||||
#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1)
|
||||
#define RTC_CNTL_MIN_SLP_VAL_MIN (2)
|
||||
|
||||
/*
|
||||
set sleep_init default param
|
||||
*/
|
||||
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
|
||||
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0
|
||||
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
|
||||
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_BIASSLP_SLEEP_ON 0
|
||||
#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
|
||||
#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_ON 0
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
|
||||
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
|
||||
|
||||
/*
|
||||
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
|
||||
storing in efuse (based on ATE 5k ECO3 chips)
|
||||
*/
|
||||
#define K_RTC_MID_MUL10000 215
|
||||
#define K_DIG_MID_MUL10000 213
|
||||
#define V_RTC_MID_MUL10000 10800
|
||||
#define V_DIG_MID_MUL10000 10860
|
||||
|
||||
#if CONFIG_ESP_ENABLE_PVT
|
||||
/*
|
||||
set pvt default param
|
||||
@@ -158,9 +119,6 @@ typedef struct rtc_cpu_freq_config_s {
|
||||
|
||||
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
|
||||
|
||||
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
|
||||
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
|
||||
|
||||
#define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
|
||||
#define RTC_CAL_32K_XTAL _Pragma ("GCC warning \"'RTC_CAL_32K_XTAL' macro is deprecated\"") CLK_CAL_32K_XTAL
|
||||
#define RTC_CAL_32K_OSC_SLOW _Pragma ("GCC warning \"'RTC_CAL_32K_OSC_SLOW' macro is deprecated\"") CLK_CAL_32K_OSC_SLOW
|
||||
|
||||
@@ -14,7 +14,7 @@ extern "C" {
|
||||
#define PMU_EXT1_WAKEUP_EN BIT(1)
|
||||
#define PMU_GPIO_WAKEUP_EN BIT(2)
|
||||
#define PMU_WIFI_BEACON_WAKEUP_EN BIT(3)
|
||||
#define PMU_LP_TIMER_WAKEUP_EN BIT(4)
|
||||
#define PMU_RTC_TIMER_WAKEUP_EN BIT(4)
|
||||
#define PMU_WIFI_SOC_WAKEUP_EN BIT(5)
|
||||
#define PMU_UART0_WAKEUP_EN BIT(6)
|
||||
#define PMU_UART1_WAKEUP_EN BIT(7)
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -53,9 +53,6 @@ extern "C" {
|
||||
#define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
|
||||
#define RTC_FAST_CLK_20M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value
|
||||
|
||||
#define OTHER_BLOCKS_POWERUP 1
|
||||
#define OTHER_BLOCKS_WAIT 1
|
||||
|
||||
/* Delays for various clock sources to be enabled/switched.
|
||||
* All values are in microseconds.
|
||||
*/
|
||||
@@ -65,37 +62,10 @@ extern "C" {
|
||||
#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5
|
||||
#define SOC_DELAY_RC32K_ENABLE 300
|
||||
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 128
|
||||
#define RTC_CNTL_RC32K_DFREQ_DEFAULT 700
|
||||
|
||||
/* Various delays to be programmed into power control state machines */
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1)
|
||||
#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4)
|
||||
#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1)
|
||||
#define RTC_CNTL_MIN_SLP_VAL_MIN (2)
|
||||
|
||||
/*
|
||||
set sleep_init default param
|
||||
*/
|
||||
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
|
||||
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0
|
||||
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
|
||||
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_BIASSLP_SLEEP_ON 0
|
||||
#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
|
||||
#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_ON 0
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
|
||||
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
|
||||
|
||||
#if CONFIG_ESP_ENABLE_PVT
|
||||
/*
|
||||
set pvt default param
|
||||
@@ -144,15 +114,6 @@ void charge_pump_enable(bool enable);
|
||||
|
||||
#endif //#if CONFIG_ESP_ENABLE_PVT
|
||||
|
||||
/*
|
||||
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
|
||||
storing in efuse (based on ATE 5k ECO3 chips)
|
||||
*/
|
||||
#define K_RTC_MID_MUL10000 215
|
||||
#define K_DIG_MID_MUL10000 213
|
||||
#define V_RTC_MID_MUL10000 10800
|
||||
#define V_DIG_MID_MUL10000 10860
|
||||
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
@@ -165,9 +126,6 @@ typedef struct rtc_cpu_freq_config_s {
|
||||
|
||||
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
|
||||
|
||||
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
|
||||
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
|
||||
|
||||
#define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
|
||||
#define RTC_CAL_RC_SLOW _Pragma ("GCC warning \"'RTC_CAL_RC_SLOW' macro is deprecated\"") CLK_CAL_RC_SLOW
|
||||
#define RTC_CAL_RC32K _Pragma ("GCC warning \"'RTC_CAL_RC32K' macro is deprecated\"") CLK_CAL_RC32K
|
||||
|
||||
@@ -14,7 +14,7 @@ extern "C" {
|
||||
#define PMU_EXT1_WAKEUP_EN BIT(1)
|
||||
#define PMU_GPIO_WAKEUP_EN BIT(2)
|
||||
#define PMU_WIFI_BEACON_WAKEUP_EN BIT(3)
|
||||
#define PMU_LP_TIMER_WAKEUP_EN BIT(4)
|
||||
#define PMU_RTC_TIMER_WAKEUP_EN BIT(4)
|
||||
#define PMU_WIFI_SOC_WAKEUP_EN BIT(5)
|
||||
#define PMU_UART0_WAKEUP_EN BIT(6)
|
||||
#define PMU_UART1_WAKEUP_EN BIT(7)
|
||||
|
||||
@@ -49,9 +49,6 @@ extern "C" {
|
||||
|
||||
#define MHZ (1000000)
|
||||
|
||||
#define OTHER_BLOCKS_POWERUP 1
|
||||
#define OTHER_BLOCKS_WAIT 1
|
||||
|
||||
/* Delays for various clock sources to be enabled/switched.
|
||||
* All values are in microseconds.
|
||||
*/
|
||||
@@ -60,45 +57,9 @@ extern "C" {
|
||||
#define SOC_DELAY_RC_FAST_ENABLE 50
|
||||
#define SOC_DELAY_RC_FAST_DIGI_SWITCH 5
|
||||
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 128
|
||||
|
||||
/* Various delays to be programmed into power control state machines */
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1)
|
||||
#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4)
|
||||
#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1)
|
||||
#define RTC_CNTL_MIN_SLP_VAL_MIN (2)
|
||||
|
||||
/*
|
||||
set sleep_init default param
|
||||
*/
|
||||
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
|
||||
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0
|
||||
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
|
||||
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_BIASSLP_SLEEP_ON 0
|
||||
#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
|
||||
#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_ON 0
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
|
||||
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
|
||||
|
||||
/*
|
||||
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
|
||||
storing in efuse (based on ATE 5k ECO3 chips)
|
||||
*/
|
||||
#define K_RTC_MID_MUL10000 215
|
||||
#define K_DIG_MID_MUL10000 213
|
||||
#define V_RTC_MID_MUL10000 10800
|
||||
#define V_DIG_MID_MUL10000 10860
|
||||
|
||||
#if CONFIG_ESP_ENABLE_PVT
|
||||
/*
|
||||
set pvt default param
|
||||
@@ -158,9 +119,6 @@ typedef struct rtc_cpu_freq_config_s {
|
||||
|
||||
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
|
||||
|
||||
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
|
||||
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
|
||||
|
||||
#define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
|
||||
#define RTC_CAL_32K_XTAL _Pragma ("GCC warning \"'RTC_CAL_32K_XTAL' macro is deprecated\"") CLK_CAL_32K_XTAL
|
||||
#define RTC_CAL_32K_OSC_SLOW _Pragma ("GCC warning \"'RTC_CAL_32K_OSC_SLOW' macro is deprecated\"") CLK_CAL_32K_OSC_SLOW
|
||||
|
||||
@@ -14,7 +14,7 @@ extern "C" {
|
||||
#define PMU_EXT1_WAKEUP_EN BIT(1)
|
||||
#define PMU_GPIO_WAKEUP_EN BIT(2)
|
||||
#define PMU_WIFI_BEACON_WAKEUP_EN BIT(3)
|
||||
#define PMU_LP_TIMER_WAKEUP_EN BIT(4)
|
||||
#define PMU_RTC_TIMER_WAKEUP_EN BIT(4)
|
||||
#define PMU_WIFI_SOC_WAKEUP_EN BIT(5)
|
||||
#define PMU_UART0_WAKEUP_EN BIT(6)
|
||||
#define PMU_UART1_WAKEUP_EN BIT(7)
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -54,9 +54,6 @@ extern "C" {
|
||||
#define RTC_SLOW_CLK_32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
|
||||
#define RTC_FAST_CLK_8M_CAL_TIMEOUT_THRES(cycles) (TIMG_RTC_CALI_TIMEOUT_THRES_V) // Just use the max timeout thres value
|
||||
|
||||
#define OTHER_BLOCKS_POWERUP 1
|
||||
#define OTHER_BLOCKS_WAIT 1
|
||||
|
||||
/* Delays for various clock sources to be enabled/switched.
|
||||
* All values are in microseconds.
|
||||
*/
|
||||
@@ -68,46 +65,10 @@ extern "C" {
|
||||
#define SOC_DELAY_LP_PLL_SWITCH 3
|
||||
#define SOC_DELAY_LP_PLL_ENABLE 50
|
||||
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 860
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 85
|
||||
#define RTC_CNTL_RC32K_DFREQ_DEFAULT 700
|
||||
|
||||
/* Various delays to be programmed into power control state machines */
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1)
|
||||
#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4)
|
||||
#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1)
|
||||
#define RTC_CNTL_MIN_SLP_VAL_MIN (2)
|
||||
|
||||
/*
|
||||
set sleep_init default param
|
||||
*/
|
||||
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
|
||||
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0
|
||||
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
|
||||
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_BIASSLP_SLEEP_ON 0
|
||||
#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
|
||||
#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_ON 0
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
|
||||
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
|
||||
|
||||
/*
|
||||
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
|
||||
storing in efuse (based on ATE 5k ECO3 chips)
|
||||
*/
|
||||
#define K_RTC_MID_MUL10000 215
|
||||
#define K_DIG_MID_MUL10000 213
|
||||
#define V_RTC_MID_MUL10000 10800
|
||||
#define V_DIG_MID_MUL10000 10860
|
||||
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
@@ -120,9 +81,6 @@ typedef struct rtc_cpu_freq_config_s {
|
||||
|
||||
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
|
||||
|
||||
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
|
||||
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
|
||||
|
||||
#define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
|
||||
#define RTC_CAL_RC_SLOW _Pragma ("GCC warning \"'RTC_CAL_RC_SLOW' macro is deprecated\"") CLK_CAL_RC_SLOW
|
||||
#define RTC_CAL_RC32K _Pragma ("GCC warning \"'RTC_CAL_RC32K' macro is deprecated\"") CLK_CAL_RC32K
|
||||
|
||||
@@ -13,7 +13,7 @@ extern "C" {
|
||||
#define PMU_EXT0_WAKEUP_EN BIT(0)
|
||||
#define PMU_EXT1_WAKEUP_EN BIT(1)
|
||||
#define PMU_GPIO_WAKEUP_EN BIT(2)
|
||||
#define PMU_LP_TIMER_WAKEUP_EN BIT(4)
|
||||
#define PMU_RTC_TIMER_WAKEUP_EN BIT(4)
|
||||
#define PMU_UART0_WAKEUP_EN BIT(6)
|
||||
#define PMU_UART1_WAKEUP_EN BIT(7)
|
||||
#define PMU_BLE_SOC_WAKEUP_EN BIT(10)
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -50,9 +50,6 @@ extern "C" {
|
||||
|
||||
#define MHZ (1000000)
|
||||
|
||||
#define OTHER_BLOCKS_POWERUP 1
|
||||
#define OTHER_BLOCKS_WAIT 1
|
||||
|
||||
/* Delays for various clock sources to be enabled/switched.
|
||||
* All values are in microseconds.
|
||||
*/
|
||||
@@ -69,15 +66,6 @@ extern "C" {
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 860
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 85
|
||||
|
||||
/* Various delays to be programmed into power control state machines */
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1)
|
||||
#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4)
|
||||
#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1)
|
||||
#define RTC_CNTL_MIN_SLP_VAL_MIN (2)
|
||||
|
||||
// /*
|
||||
// set sleep_init default param
|
||||
// */
|
||||
|
||||
@@ -13,7 +13,7 @@ extern "C" {
|
||||
#define PMU_EXT0_WAKEUP_EN BIT(0)
|
||||
#define PMU_EXT1_WAKEUP_EN BIT(1)
|
||||
#define PMU_GPIO_WAKEUP_EN BIT(2)
|
||||
#define PMU_LP_TIMER_WAKEUP_EN BIT(4)
|
||||
#define PMU_RTC_TIMER_WAKEUP_EN BIT(4)
|
||||
#define PMU_UART0_WAKEUP_EN BIT(6)
|
||||
#define PMU_UART1_WAKEUP_EN BIT(7)
|
||||
#define PMU_BLE_SOC_WAKEUP_EN BIT(10)
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -50,9 +50,6 @@ extern "C" {
|
||||
|
||||
#define MHZ (1000000)
|
||||
|
||||
#define OTHER_BLOCKS_POWERUP 1
|
||||
#define OTHER_BLOCKS_WAIT 1
|
||||
|
||||
/* Delays for various clock sources to be enabled/switched.
|
||||
* All values are in microseconds.
|
||||
*/
|
||||
@@ -68,16 +65,6 @@ extern "C" {
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 28
|
||||
|
||||
/* Various delays to be programmed into power control state machines */
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1)
|
||||
#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4)
|
||||
#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1)
|
||||
#define RTC_CNTL_MIN_SLP_VAL_MIN (2)
|
||||
|
||||
// /*
|
||||
// set sleep_init default param
|
||||
// */
|
||||
|
||||
@@ -13,7 +13,7 @@ extern "C" {
|
||||
#define PMU_EXT0_WAKEUP_EN BIT(0)
|
||||
#define PMU_EXT1_WAKEUP_EN BIT(1)
|
||||
#define PMU_GPIO_WAKEUP_EN BIT(2)
|
||||
#define PMU_LP_TIMER_WAKEUP_EN BIT(4)
|
||||
#define PMU_RTC_TIMER_WAKEUP_EN BIT(4)
|
||||
#define PMU_UART0_WAKEUP_EN BIT(6)
|
||||
#define PMU_UART1_WAKEUP_EN BIT(7)
|
||||
#define PMU_TOUCH_WAKEUP_EN BIT(9)
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -50,9 +50,6 @@ extern "C" {
|
||||
|
||||
#define MHZ (1000000)
|
||||
|
||||
#define OTHER_BLOCKS_POWERUP 1
|
||||
#define OTHER_BLOCKS_WAIT 1
|
||||
|
||||
/* Delays for various clock sources to be enabled/switched.
|
||||
* All values are in microseconds.
|
||||
*/
|
||||
@@ -71,32 +68,7 @@ extern "C" {
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 128
|
||||
#define RTC_CNTL_RC32K_DFREQ_DEFAULT 700
|
||||
|
||||
/* Various delays to be programmed into power control state machines */
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250)
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1)
|
||||
#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4)
|
||||
#define RTC_CNTL_WAKEUP_DELAY_CYCLES (5)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_POWERUP_CYCLES (1)
|
||||
#define RTC_CNTL_OTHER_BLOCKS_WAIT_CYCLES (1)
|
||||
#define RTC_CNTL_MIN_SLP_VAL_MIN (2)
|
||||
|
||||
/*
|
||||
set sleep_init default param
|
||||
*/
|
||||
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 5
|
||||
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0
|
||||
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
|
||||
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_BIASSLP_SLEEP_ON 0
|
||||
#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
|
||||
#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_ON 0
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
|
||||
#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT 254
|
||||
|
||||
#if CONFIG_ESP_ENABLE_PVT
|
||||
|
||||
#define PVT_CHANNEL0_SEL 49
|
||||
#define PVT_CHANNEL1_SEL 53
|
||||
#define PVT_CHANNEL0_CFG 0x13e80
|
||||
@@ -130,15 +102,6 @@ void pvt_func_enable(bool enable);
|
||||
|
||||
#endif //#if CONFIG_ESP_ENABLE_PVT
|
||||
|
||||
/*
|
||||
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
|
||||
storing in efuse (based on ATE 5k ECO3 chips)
|
||||
*/
|
||||
#define K_RTC_MID_MUL10000 215
|
||||
#define K_DIG_MID_MUL10000 213
|
||||
#define V_RTC_MID_MUL10000 10800
|
||||
#define V_DIG_MID_MUL10000 10860
|
||||
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
@@ -151,9 +114,6 @@ typedef struct rtc_cpu_freq_config_s {
|
||||
|
||||
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
|
||||
|
||||
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
|
||||
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
|
||||
|
||||
#define RTC_CAL_RTC_MUX _Pragma ("GCC warning \"'RTC_CAL_RTC_MUX' macro is deprecated\"") CLK_CAL_RTC_SLOW
|
||||
#define RTC_CAL_MPLL _Pragma ("GCC warning \"'RTC_CAL_MPLL' macro is deprecated\"") CLK_CAL_MPLL
|
||||
#define RTC_CAL_SPLL _Pragma ("GCC warning \"'RTC_CAL_SPLL' macro is deprecated\"") CLK_CAL_SPLL
|
||||
|
||||
@@ -23,7 +23,7 @@ extern "C" {
|
||||
#define PMU_LP_UART_WAKEUP_EN BIT(10)
|
||||
#define PMU_TOUCH_WAKEUP_EN BIT(11)
|
||||
#define PMU_EXT1_WAKEUP_EN BIT(12)
|
||||
#define PMU_LP_TIMER_WAKEUP_EN BIT(13)
|
||||
#define PMU_RTC_TIMER_WAKEUP_EN BIT(13)
|
||||
#define PMU_BOD_WAKEUP_EN BIT(14)
|
||||
#define PMU_VBAT_UNDERVOLT_WAKEUP_EN BIT(15)
|
||||
#define PMU_LP_CORE_TRAP_WAKEUP_EN BIT(16)
|
||||
|
||||
@@ -4,6 +4,9 @@ set(srcs
|
||||
"rtc_clk.c"
|
||||
"rtc_time.c"
|
||||
"chip_info.c"
|
||||
"pmu_param.c"
|
||||
"pmu_init.c"
|
||||
"pmu_sleep.c"
|
||||
)
|
||||
|
||||
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -56,15 +56,6 @@ extern "C" {
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 128
|
||||
#define RTC_CNTL_RC32K_DFREQ_DEFAULT 700
|
||||
|
||||
/*
|
||||
The follow value is used to get a reasonable rtc voltage dbias value according to digital dbias & some other value
|
||||
storing in efuse (based on ATE 5k ECO3 chips)
|
||||
*/
|
||||
#define K_RTC_MID_MUL10000 215
|
||||
#define K_DIG_MID_MUL10000 213
|
||||
#define V_RTC_MID_MUL10000 10800
|
||||
#define V_DIG_MID_MUL10000 10860
|
||||
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
@@ -77,9 +68,6 @@ typedef struct rtc_cpu_freq_config_s {
|
||||
|
||||
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
|
||||
|
||||
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
|
||||
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
|
||||
|
||||
/**
|
||||
* @brief Clock source to be calibrated using rtc_clk_cal function
|
||||
*
|
||||
|
||||
@@ -0,0 +1,208 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <esp_types.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_attr.h"
|
||||
#include "soc/chip_revision.h"
|
||||
#include "soc/soc.h"
|
||||
#include "soc/pmu_struct.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "hal/pmu_hal.h"
|
||||
#include "pmu_param.h"
|
||||
#include "esp_private/esp_pmu.h"
|
||||
#include "esp_hw_log.h"
|
||||
|
||||
ESP_HW_LOG_ATTR_TAG(TAG, "pmu_init");
|
||||
|
||||
typedef struct {
|
||||
const pmu_hp_system_power_param_t *power;
|
||||
const pmu_hp_system_clock_param_t *clock;
|
||||
const pmu_hp_system_digital_param_t *digital;
|
||||
const pmu_hp_system_analog_param_t *analog;
|
||||
const pmu_hp_system_retention_param_t *retent;
|
||||
} pmu_hp_system_param_t;
|
||||
|
||||
typedef struct {
|
||||
const pmu_lp_system_power_param_t *power;
|
||||
const pmu_lp_system_analog_param_t *analog;
|
||||
} pmu_lp_system_param_t;
|
||||
|
||||
pmu_context_t * __attribute__((weak)) IRAM_ATTR PMU_instance(void)
|
||||
{
|
||||
/* It should be explicitly defined in the internal RAM, because this
|
||||
* instance will be used in pmu_sleep.c */
|
||||
static DRAM_ATTR pmu_hal_context_t pmu_hal = { .dev = &PMU };
|
||||
static DRAM_ATTR pmu_sleep_machine_constant_t pmu_mc = PMU_SLEEP_MC_DEFAULT();
|
||||
static DRAM_ATTR pmu_context_t pmu_context = { .hal = &pmu_hal, .mc = (void *)&pmu_mc };
|
||||
return &pmu_context;
|
||||
}
|
||||
|
||||
void pmu_hp_system_init(pmu_context_t *ctx, pmu_hp_mode_t mode, pmu_hp_system_param_t *param)
|
||||
{
|
||||
const pmu_hp_system_power_param_t *power = param->power;
|
||||
const pmu_hp_system_clock_param_t *clock = param->clock;
|
||||
const pmu_hp_system_digital_param_t *dig = param->digital;
|
||||
const pmu_hp_system_analog_param_t *anlg = param->analog;
|
||||
const pmu_hp_system_retention_param_t *ret = param->retent;
|
||||
|
||||
assert(ctx->hal);
|
||||
/* Default configuration of hp-system power in active, modem and sleep modes */
|
||||
pmu_ll_hp_set_dig_power(ctx->hal->dev, mode, power->dig_power.val);
|
||||
pmu_ll_hp_set_clk_power(ctx->hal->dev, mode, power->clk_power.val);
|
||||
pmu_ll_hp_set_xtal_xpd (ctx->hal->dev, mode, power->xtal.xpd_xtal);
|
||||
|
||||
/* Default configuration of hp-system clock in active, modem and sleep modes */
|
||||
pmu_ll_hp_set_icg_func (ctx->hal->dev, mode, clock->icg_func.clock[0], clock->icg_func.clock[1]);
|
||||
pmu_ll_hp_set_icg_apb (ctx->hal->dev, mode, clock->icg_apb.clock[0], clock->icg_apb.clock[1]);
|
||||
pmu_ll_hp_set_icg_modem (ctx->hal->dev, mode, clock->icg_modem.code);
|
||||
pmu_ll_hp_set_sysclk_nodiv (ctx->hal->dev, mode, clock->sysclk.dig_sysclk_nodiv);
|
||||
pmu_ll_hp_set_icg_sysclk_enable (ctx->hal->dev, mode, clock->sysclk.icg_sysclk_en);
|
||||
pmu_ll_hp_set_sysclk_slp_sel (ctx->hal->dev, mode, clock->sysclk.sysclk_slp_sel);
|
||||
pmu_ll_hp_set_icg_sysclk_slp_sel(ctx->hal->dev, mode, clock->sysclk.icg_slp_sel);
|
||||
pmu_ll_hp_set_dig_sysclk (ctx->hal->dev, mode, clock->sysclk.dig_sysclk_sel);
|
||||
|
||||
/* Default configuration of hp-system digital sub-system in active, modem
|
||||
* and sleep modes */
|
||||
pmu_ll_hp_set_c_channel_enable (ctx->hal->dev, mode, dig->syscntl.c_channel);
|
||||
pmu_ll_hp_set_uart_wakeup_enable(ctx->hal->dev, mode, dig->syscntl.uart_wakeup_en);
|
||||
pmu_ll_hp_set_hold_all_lp_pad (ctx->hal->dev, mode, dig->syscntl.lp_pad_hold_all);
|
||||
pmu_ll_hp_set_hold_all_hp_pad (ctx->hal->dev, mode, dig->syscntl.hp_pad_hold_all);
|
||||
pmu_ll_hp_set_dig_pad_slp_sel (ctx->hal->dev, mode, dig->syscntl.dig_pad_slp_sel);
|
||||
pmu_ll_hp_set_pause_watchdog (ctx->hal->dev, mode, dig->syscntl.dig_pause_wdt);
|
||||
pmu_ll_hp_set_cpu_stall (ctx->hal->dev, mode, dig->syscntl.dig_cpu_stall);
|
||||
|
||||
/* Default configuration of hp-system analog sub-system in active, modem and
|
||||
* sleep modes */
|
||||
pmu_ll_hp_set_bias_xpd (ctx->hal->dev, mode, anlg->bias.xpd_bias);
|
||||
pmu_ll_hp_set_dbg_atten (ctx->hal->dev, mode, anlg->bias.dbg_atten);
|
||||
pmu_ll_hp_set_current_power_off (ctx->hal->dev, mode, anlg->bias.pd_cur);
|
||||
pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, mode, anlg->bias.bias_sleep);
|
||||
if (mode == PMU_MODE_HP_ACTIVE) {
|
||||
pmu_ll_hp_set_regulator_lp_dbias_voltage(ctx->hal->dev, mode, anlg->regulator0.lp_dbias_vol);
|
||||
pmu_ll_hp_set_regulator_hp_dbias_voltage(ctx->hal->dev, mode, anlg->regulator0.hp_dbias_vol);
|
||||
pmu_ll_hp_set_regulator_dbias_select (ctx->hal->dev, mode, anlg->regulator0.dbias_sel);
|
||||
pmu_ll_hp_set_regulator_dbias_init (ctx->hal->dev, mode, anlg->regulator0.dig_dbias_init);
|
||||
}
|
||||
pmu_ll_hp_set_regulator_sleep_memory_xpd (ctx->hal->dev, mode, anlg->regulator0.slp_mem_xpd);
|
||||
pmu_ll_hp_set_regulator_sleep_memory_dbias(ctx->hal->dev, mode, anlg->regulator0.slp_mem_dbias);
|
||||
pmu_ll_hp_set_regulator_sleep_logic_xpd (ctx->hal->dev, mode, anlg->regulator0.slp_logic_xpd);
|
||||
pmu_ll_hp_set_regulator_sleep_logic_dbias (ctx->hal->dev, mode, anlg->regulator0.slp_logic_dbias);
|
||||
pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, mode, anlg->regulator0.dbias);
|
||||
pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, mode, anlg->regulator0.xpd);
|
||||
pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, mode, anlg->regulator1.drv_b);
|
||||
|
||||
/* Default configuration of hp-system retention sub-system in active, modem
|
||||
* and sleep modes */
|
||||
pmu_ll_hp_set_retention_param(ctx->hal->dev, mode, ret->retention.val);
|
||||
pmu_ll_hp_set_backup_icg_func(ctx->hal->dev, mode, ret->backup_clk[0], ret->backup_clk[1]);
|
||||
|
||||
/* Some PMU initial parameter configuration */
|
||||
pmu_ll_imm_update_dig_icg_modem_code(ctx->hal->dev, true);
|
||||
pmu_ll_imm_update_dig_icg_switch(ctx->hal->dev, true);
|
||||
|
||||
pmu_ll_hp_set_sleep_protect_mode(ctx->hal->dev, PMU_SLEEP_PROTECT_HP_LP_SLEEP);
|
||||
}
|
||||
|
||||
void pmu_lp_system_init(pmu_context_t *ctx, pmu_lp_mode_t mode, pmu_lp_system_param_t *param)
|
||||
{
|
||||
const pmu_lp_system_power_param_t *power = param->power;
|
||||
const pmu_lp_system_analog_param_t *anlg = param->analog;
|
||||
|
||||
assert(ctx->hal);
|
||||
/* Default configuration of lp-system power in active and sleep modes */
|
||||
pmu_ll_lp_set_dig_power(ctx->hal->dev, mode, power->dig_power.val);
|
||||
pmu_ll_lp_set_clk_power(ctx->hal->dev, mode, power->clk_power.val);
|
||||
pmu_ll_lp_set_xtal_xpd (ctx->hal->dev, PMU_MODE_LP_SLEEP, power->xtal.xpd_xtal);
|
||||
|
||||
/* Default configuration of lp-system analog sub-system in active and
|
||||
* sleep modes */
|
||||
pmu_ll_lp_set_bias_xpd (ctx->hal->dev, PMU_MODE_LP_SLEEP, anlg->bias.xpd_bias);
|
||||
pmu_ll_lp_set_dbg_atten (ctx->hal->dev, PMU_MODE_LP_SLEEP, anlg->bias.dbg_atten);
|
||||
pmu_ll_lp_set_current_power_off (ctx->hal->dev, PMU_MODE_LP_SLEEP, anlg->bias.pd_cur);
|
||||
pmu_ll_lp_set_bias_sleep_enable (ctx->hal->dev, PMU_MODE_LP_SLEEP, anlg->bias.bias_sleep);
|
||||
pmu_ll_lp_set_regulator_xpd (ctx->hal->dev, mode, anlg->regulator0.xpd);
|
||||
pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, mode, anlg->regulator0.dbias);
|
||||
pmu_ll_lp_set_regulator_slp_xpd (ctx->hal->dev, mode, anlg->regulator0.slp_xpd);
|
||||
pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, mode, anlg->regulator0.slp_dbias);
|
||||
pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, mode, anlg->regulator1.drv_b);
|
||||
}
|
||||
|
||||
static inline void pmu_power_domain_force_default(pmu_context_t *ctx)
|
||||
{
|
||||
assert(ctx);
|
||||
// for bypass reserved power domain
|
||||
const pmu_hp_power_domain_t pmu_hp_domains[] = {
|
||||
PMU_HP_PD_TOP,
|
||||
PMU_HP_PD_HPALIVE,
|
||||
PMU_HP_PD_MODEMPWR,
|
||||
PMU_HP_PD_HPCPU,
|
||||
PMU_HP_PD_HPCNNT,
|
||||
PMU_HP_PD_MODEM
|
||||
};
|
||||
|
||||
for (uint8_t idx = 0; idx < (sizeof(pmu_hp_domains) / sizeof(pmu_hp_power_domain_t)); idx++) {
|
||||
pmu_ll_hp_set_power_force_power_up (ctx->hal->dev, pmu_hp_domains[idx], false);
|
||||
pmu_ll_hp_set_power_force_no_reset (ctx->hal->dev, pmu_hp_domains[idx], false);
|
||||
pmu_ll_hp_set_power_force_no_isolate(ctx->hal->dev, pmu_hp_domains[idx], false);
|
||||
pmu_ll_hp_set_power_force_power_down(ctx->hal->dev, pmu_hp_domains[idx], false);
|
||||
pmu_ll_hp_set_power_force_isolate (ctx->hal->dev, pmu_hp_domains[idx], false);
|
||||
pmu_ll_hp_set_power_force_reset (ctx->hal->dev, pmu_hp_domains[idx], false);
|
||||
}
|
||||
/* Isolate all memory banks while sleeping, avoid memory leakage current */
|
||||
pmu_ll_hp_set_memory_no_isolate (ctx->hal->dev, 0);
|
||||
|
||||
pmu_ll_lp_set_power_force_power_up (ctx->hal->dev, false);
|
||||
pmu_ll_lp_set_power_force_no_reset (ctx->hal->dev, false);
|
||||
pmu_ll_lp_set_power_force_no_isolate(ctx->hal->dev, false);
|
||||
pmu_ll_lp_set_power_force_power_down(ctx->hal->dev, false);
|
||||
pmu_ll_lp_set_power_force_isolate (ctx->hal->dev, false);
|
||||
pmu_ll_lp_set_power_force_reset (ctx->hal->dev, false);
|
||||
}
|
||||
|
||||
static inline void pmu_hp_system_param_default(pmu_hp_mode_t mode, pmu_hp_system_param_t *param)
|
||||
{
|
||||
param->power = pmu_hp_system_power_param_default(mode);
|
||||
param->clock = pmu_hp_system_clock_param_default(mode);
|
||||
param->digital = pmu_hp_system_digital_param_default(mode);
|
||||
param->analog = pmu_hp_system_analog_param_default(mode);
|
||||
param->retent = pmu_hp_system_retention_param_default(mode);
|
||||
}
|
||||
|
||||
static void pmu_hp_system_init_default(pmu_context_t *ctx)
|
||||
{
|
||||
assert(ctx);
|
||||
pmu_hp_system_param_t param = { 0 };
|
||||
for (pmu_hp_mode_t mode = PMU_MODE_HP_ACTIVE; mode < PMU_MODE_HP_MAX; mode++) {
|
||||
pmu_hp_system_param_default(mode, ¶m);
|
||||
pmu_hp_system_init(ctx, mode, ¶m);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void pmu_lp_system_param_default(pmu_lp_mode_t mode, pmu_lp_system_param_t *param)
|
||||
{
|
||||
param->power = pmu_lp_system_power_param_default(mode);
|
||||
param->analog = pmu_lp_system_analog_param_default(mode);
|
||||
}
|
||||
|
||||
static void pmu_lp_system_init_default(pmu_context_t *ctx)
|
||||
{
|
||||
assert(ctx);
|
||||
pmu_lp_system_param_t param;
|
||||
for (pmu_lp_mode_t mode = PMU_MODE_LP_ACTIVE; mode < PMU_MODE_LP_MAX; mode++) {
|
||||
pmu_lp_system_param_default(mode, ¶m);
|
||||
pmu_lp_system_init(ctx, mode, ¶m);
|
||||
}
|
||||
}
|
||||
|
||||
void pmu_init(void)
|
||||
{
|
||||
pmu_hp_system_init_default(PMU_instance());
|
||||
pmu_lp_system_init_default(PMU_instance());
|
||||
pmu_power_domain_force_default(PMU_instance());
|
||||
}
|
||||
@@ -0,0 +1,431 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <esp_types.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "soc/soc.h"
|
||||
#include "pmu_param.h"
|
||||
#include "soc/pmu_icg_mapping.h"
|
||||
#include "esp_private/esp_pmu.h"
|
||||
#include "hal/efuse_ll.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "esp_hw_log.h"
|
||||
#include "soc/clk_tree_defs.h"
|
||||
|
||||
ESP_HW_LOG_ATTR_TAG(TAG, "pmu_param");
|
||||
|
||||
#ifndef ARRAY_SIZE
|
||||
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
|
||||
#endif
|
||||
|
||||
#define PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT() { \
|
||||
.dig_power = { \
|
||||
.vdd_spi_pd_en = 0, \
|
||||
.pd_hp_alive_pd_en = 0, \
|
||||
.hp_mem_dslp = 0, \
|
||||
.hp_mem_pd_en = 0, \
|
||||
.modem_top_pd_en = 0, \
|
||||
.hp_cnnt_pd_en = 0, \
|
||||
.hp_cpu_pd_en = 0, \
|
||||
.modem_pwr_pd_en = 0, \
|
||||
.top_pd_en = 0 \
|
||||
}, \
|
||||
.clk_power = { \
|
||||
.i2c_iso_en = 0, \
|
||||
.i2c_retention = 0, \
|
||||
.xpd_bb_i2c = 1, \
|
||||
.xpd_pll_i2c = 0xf, \
|
||||
.xpd_pll = 0xf \
|
||||
}, \
|
||||
.xtal = { \
|
||||
.xpd_xtal = 1 \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PMU_HP_MODEM_POWER_CONFIG_DEFAULT() { \
|
||||
.dig_power = { \
|
||||
.vdd_spi_pd_en = 0, \
|
||||
.pd_hp_alive_pd_en = 0, \
|
||||
.hp_mem_dslp = 0, \
|
||||
.hp_mem_pd_en = 0, \
|
||||
.modem_top_pd_en = 0, \
|
||||
.hp_cnnt_pd_en = 0, \
|
||||
.hp_cpu_pd_en = 1, \
|
||||
.modem_pwr_pd_en = 0, \
|
||||
.top_pd_en = 0 \
|
||||
}, \
|
||||
.clk_power = { \
|
||||
.i2c_iso_en = 0, \
|
||||
.i2c_retention = 0, \
|
||||
.xpd_bb_i2c = 1, \
|
||||
.xpd_pll_i2c = 0xf, \
|
||||
.xpd_pll = 0xf \
|
||||
}, \
|
||||
.xtal = { \
|
||||
.xpd_xtal = 1 \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PMU_HP_SLEEP_POWER_CONFIG_DEFAULT() { \
|
||||
.dig_power = { \
|
||||
.vdd_spi_pd_en = 1, \
|
||||
.pd_hp_alive_pd_en = 1, \
|
||||
.hp_mem_dslp = 1, \
|
||||
.hp_mem_pd_en = 0, \
|
||||
.modem_top_pd_en = 1, \
|
||||
.hp_cnnt_pd_en = 1, \
|
||||
.hp_cpu_pd_en = 1, \
|
||||
.modem_pwr_pd_en = 0, \
|
||||
.top_pd_en = 1 \
|
||||
}, \
|
||||
.clk_power = { \
|
||||
.i2c_iso_en = 0, \
|
||||
.i2c_retention = 0, \
|
||||
.xpd_bb_i2c = 1, \
|
||||
.xpd_pll_i2c = 0xf, \
|
||||
.xpd_pll = 0xf \
|
||||
}, \
|
||||
.xtal = { \
|
||||
.xpd_xtal = 0 \
|
||||
} \
|
||||
}
|
||||
|
||||
const pmu_hp_system_power_param_t * pmu_hp_system_power_param_default(pmu_hp_mode_t mode)
|
||||
{
|
||||
static const pmu_hp_system_power_param_t hp_power[] = {
|
||||
PMU_HP_ACTIVE_POWER_CONFIG_DEFAULT(),
|
||||
PMU_HP_MODEM_POWER_CONFIG_DEFAULT(),
|
||||
PMU_HP_SLEEP_POWER_CONFIG_DEFAULT()
|
||||
};
|
||||
assert(mode < ARRAY_SIZE(hp_power));
|
||||
return &hp_power[mode];
|
||||
}
|
||||
|
||||
#define PMU_HP_ACTIVE_CLOCK_CONFIG_DEFAULT() { \
|
||||
.icg_func.clock[0] = 0xffffffff, \
|
||||
.icg_func.clock[1] = 0xffffffff, \
|
||||
.icg_apb.clock[0] = 0xffffffff, \
|
||||
.icg_apb.clock[1] = 0xffffffff, \
|
||||
.icg_modem.code = PMU_HP_ICG_MODEM_CODE_ACTIVE, \
|
||||
.sysclk = { \
|
||||
.dig_sysclk_nodiv = 0, \
|
||||
.icg_sysclk_en = 1, \
|
||||
.sysclk_slp_sel = 0, \
|
||||
.icg_slp_sel = 0, \
|
||||
.dig_sysclk_sel = SOC_CPU_CLK_SRC_XTAL \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PMU_HP_MODEM_CLOCK_CONFIG_DEFAULT() { \
|
||||
.icg_func.clock[0] = 0, \
|
||||
.icg_func.clock[1] = 0, \
|
||||
.icg_apb.clock[0] = 0, \
|
||||
.icg_apb.clock[1] = 0, \
|
||||
.icg_modem.code = PMU_HP_ICG_MODEM_CODE_MODEM, \
|
||||
.sysclk = { \
|
||||
.dig_sysclk_nodiv = 0, \
|
||||
.icg_sysclk_en = 1, \
|
||||
.sysclk_slp_sel = 1, \
|
||||
.icg_slp_sel = 1, \
|
||||
.dig_sysclk_sel = SOC_CPU_CLK_SRC_XTAL \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PMU_HP_SLEEP_CLOCK_CONFIG_DEFAULT() { \
|
||||
.icg_func.clock[0] = 0, \
|
||||
.icg_func.clock[1] = 0, \
|
||||
.icg_apb.clock[0] = 0, \
|
||||
.icg_apb.clock[1] = 0, \
|
||||
.icg_modem.code = PMU_HP_ICG_MODEM_CODE_SLEEP, \
|
||||
.sysclk = { \
|
||||
.dig_sysclk_nodiv = 0, \
|
||||
.icg_sysclk_en = 0, \
|
||||
.sysclk_slp_sel = 1, \
|
||||
.icg_slp_sel = 1, \
|
||||
.dig_sysclk_sel = SOC_CPU_CLK_SRC_XTAL \
|
||||
} \
|
||||
}
|
||||
|
||||
const pmu_hp_system_clock_param_t * pmu_hp_system_clock_param_default(pmu_hp_mode_t mode)
|
||||
{
|
||||
static const pmu_hp_system_clock_param_t hp_clock[] = {
|
||||
PMU_HP_ACTIVE_CLOCK_CONFIG_DEFAULT(),
|
||||
PMU_HP_MODEM_CLOCK_CONFIG_DEFAULT(),
|
||||
PMU_HP_SLEEP_CLOCK_CONFIG_DEFAULT()
|
||||
};
|
||||
assert(mode < ARRAY_SIZE(hp_clock));
|
||||
return &hp_clock[mode];
|
||||
}
|
||||
|
||||
#define PMU_HP_ACTIVE_DIGITAL_CONFIG_DEFAULT() { \
|
||||
.syscntl = { \
|
||||
.c_channel = 1, \
|
||||
.uart_wakeup_en = 0, \
|
||||
.lp_pad_hold_all = 0, \
|
||||
.hp_pad_hold_all = 0, \
|
||||
.dig_pad_slp_sel = 0, \
|
||||
.dig_pause_wdt = 0, \
|
||||
.dig_cpu_stall = 0 \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PMU_HP_MODEM_DIGITAL_CONFIG_DEFAULT() { \
|
||||
.syscntl = { \
|
||||
.c_channel = 1, \
|
||||
.uart_wakeup_en = 0, \
|
||||
.lp_pad_hold_all = 0, \
|
||||
.hp_pad_hold_all = 0, \
|
||||
.dig_pad_slp_sel = 1, \
|
||||
.dig_pause_wdt = 1, \
|
||||
.dig_cpu_stall = 1 \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PMU_HP_SLEEP_DIGITAL_CONFIG_DEFAULT() { \
|
||||
.syscntl = { \
|
||||
.c_channel = 1, \
|
||||
.uart_wakeup_en = 1, \
|
||||
.lp_pad_hold_all = 0, \
|
||||
.hp_pad_hold_all = 0, \
|
||||
.dig_pad_slp_sel = 0, \
|
||||
.dig_pause_wdt = 1, \
|
||||
.dig_cpu_stall = 1 \
|
||||
} \
|
||||
}
|
||||
|
||||
const pmu_hp_system_digital_param_t * pmu_hp_system_digital_param_default(pmu_hp_mode_t mode)
|
||||
{
|
||||
static const pmu_hp_system_digital_param_t hp_digital[] = {
|
||||
PMU_HP_ACTIVE_DIGITAL_CONFIG_DEFAULT(),
|
||||
PMU_HP_MODEM_DIGITAL_CONFIG_DEFAULT(),
|
||||
PMU_HP_SLEEP_DIGITAL_CONFIG_DEFAULT()
|
||||
};
|
||||
assert(mode < ARRAY_SIZE(hp_digital));
|
||||
return &hp_digital[mode];
|
||||
}
|
||||
|
||||
#define PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \
|
||||
.bias = { \
|
||||
.xpd_bias = 1, \
|
||||
.dbg_atten = 0x0, \
|
||||
.pd_cur = 0, \
|
||||
.bias_sleep = 0 \
|
||||
}, \
|
||||
.regulator0 = { \
|
||||
.dig_dbias_init = 1, \
|
||||
.lp_dbias_vol = 0xd, \
|
||||
.hp_dbias_vol = 0x1c, \
|
||||
.dbias_sel = 1, \
|
||||
.slp_connect_en = 0, \
|
||||
.slp_mem_xpd = 0, \
|
||||
.slp_logic_xpd = 0, \
|
||||
.xpd = 1, \
|
||||
.slp_mem_dbias = 0, \
|
||||
.slp_logic_dbias = 0, \
|
||||
.dbias = HP_CALI_DBIAS_DEFAULT\
|
||||
}, \
|
||||
.regulator1 = { \
|
||||
.drv_b = 0x0 \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PMU_HP_MODEM_ANALOG_CONFIG_DEFAULT() { \
|
||||
.bias = { \
|
||||
.xpd_bias = 0, \
|
||||
.dbg_atten = 0x0, \
|
||||
.pd_cur = 0, \
|
||||
.bias_sleep = 0 \
|
||||
}, \
|
||||
.regulator0 = { \
|
||||
.slp_connect_en = 0, \
|
||||
.slp_mem_xpd = 0, \
|
||||
.slp_logic_xpd = 0, \
|
||||
.xpd = 1, \
|
||||
.slp_mem_dbias = 0, \
|
||||
.slp_logic_dbias = 0, \
|
||||
.dbias = HP_CALI_DBIAS_DEFAULT\
|
||||
}, \
|
||||
.regulator1 = { \
|
||||
.drv_b = 0x0 \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT() { \
|
||||
.bias = { \
|
||||
.xpd_bias = 0, \
|
||||
.dbg_atten = 0x0, \
|
||||
.pd_cur = 0, \
|
||||
.bias_sleep = 0 \
|
||||
}, \
|
||||
.regulator0 = { \
|
||||
.slp_connect_en = 0, \
|
||||
.slp_mem_xpd = 0, \
|
||||
.slp_logic_xpd = 0, \
|
||||
.xpd = 1, \
|
||||
.slp_mem_dbias = 1, \
|
||||
.slp_logic_dbias = 0, \
|
||||
.dbias = 1 \
|
||||
}, \
|
||||
.regulator1 = { \
|
||||
.drv_b = 0x0 \
|
||||
} \
|
||||
}
|
||||
|
||||
const pmu_hp_system_analog_param_t * pmu_hp_system_analog_param_default(pmu_hp_mode_t mode)
|
||||
{
|
||||
static const pmu_hp_system_analog_param_t hp_analog[] = {
|
||||
PMU_HP_ACTIVE_ANALOG_CONFIG_DEFAULT(),
|
||||
PMU_HP_MODEM_ANALOG_CONFIG_DEFAULT(),
|
||||
PMU_HP_SLEEP_ANALOG_CONFIG_DEFAULT()
|
||||
};
|
||||
assert(mode < ARRAY_SIZE(hp_analog));
|
||||
return &hp_analog[mode];
|
||||
}
|
||||
|
||||
#define PMU_HP_RETENTION_REGDMA_CONFIG(dir, entry) ((((dir)<<4) | (entry & 0xf)) & 0x1f)
|
||||
|
||||
#define PMU_HP_ACTIVE_RETENTION_CONFIG_DEFAULT() { \
|
||||
.retention = { \
|
||||
.hp_sleep2active_backup_modem_clk_code = 2, \
|
||||
.hp_modem2active_backup_modem_clk_code = 2, \
|
||||
.hp_active_retention_mode = 0, \
|
||||
.hp_sleep2active_retention_en = 0, \
|
||||
.hp_modem2active_retention_en = 0, \
|
||||
.hp_sleep2active_backup_clk_sel = 0, \
|
||||
.hp_modem2active_backup_clk_sel = 0, \
|
||||
.hp_sleep2active_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 0), \
|
||||
.hp_modem2active_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 2), \
|
||||
.hp_sleep2active_backup_en = 0, \
|
||||
.hp_modem2active_backup_en = 0, \
|
||||
}, \
|
||||
.backup_clk[0] = 0xffffffff, \
|
||||
.backup_clk[1] = 0xffffffff, \
|
||||
}
|
||||
|
||||
#define PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT() { \
|
||||
.retention = { \
|
||||
.hp_sleep2modem_backup_modem_clk_code = 1, \
|
||||
.hp_modem_retention_mode = 0, \
|
||||
.hp_sleep2modem_retention_en = 0, \
|
||||
.hp_sleep2modem_backup_clk_sel = SOC_CPU_CLK_SRC_XTAL, \
|
||||
.hp_sleep2modem_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(0, 1), \
|
||||
.hp_sleep2modem_backup_en = 0, \
|
||||
}, \
|
||||
.backup_clk[0] = 0xffffffff, \
|
||||
.backup_clk[1] = 0xffffffff, \
|
||||
}
|
||||
|
||||
#define PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT() { \
|
||||
.retention = { \
|
||||
.hp_modem2sleep_backup_modem_clk_code = 0, \
|
||||
.hp_active2sleep_backup_modem_clk_code = 2, \
|
||||
.hp_sleep_retention_mode = 0, \
|
||||
.hp_modem2sleep_retention_en = 0, \
|
||||
.hp_active2sleep_retention_en = 0, \
|
||||
.hp_modem2sleep_backup_clk_sel = 0, \
|
||||
.hp_active2sleep_backup_clk_sel = 0, \
|
||||
.hp_modem2sleep_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(1, 1), \
|
||||
.hp_active2sleep_backup_mode = PMU_HP_RETENTION_REGDMA_CONFIG(1, 0), \
|
||||
.hp_modem2sleep_backup_en = 0, \
|
||||
.hp_active2sleep_backup_en = 0, \
|
||||
}, \
|
||||
.backup_clk[0] = 0xffffffff, \
|
||||
.backup_clk[1] = 0xffffffff, \
|
||||
}
|
||||
|
||||
const pmu_hp_system_retention_param_t * pmu_hp_system_retention_param_default(pmu_hp_mode_t mode)
|
||||
{
|
||||
static const pmu_hp_system_retention_param_t hp_retention[] = {
|
||||
PMU_HP_ACTIVE_RETENTION_CONFIG_DEFAULT(),
|
||||
PMU_HP_MODEM_RETENTION_CONFIG_DEFAULT(),
|
||||
PMU_HP_SLEEP_RETENTION_CONFIG_DEFAULT()
|
||||
};
|
||||
assert(mode < ARRAY_SIZE(hp_retention));
|
||||
return &hp_retention[mode];
|
||||
}
|
||||
|
||||
|
||||
/** LP system default parameter */
|
||||
#define PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT() { \
|
||||
.dig_power = { \
|
||||
.mem_dslp = 0, \
|
||||
.peri_pd_en = 0, \
|
||||
}, \
|
||||
.clk_power = { \
|
||||
.xpd_xtal32k = 1, \
|
||||
.xpd_rc32k = 1, \
|
||||
.xpd_fosc = 1, \
|
||||
.pd_osc = 0 \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PMU_LP_SLEEP_POWER_CONFIG_DEFAULT() { \
|
||||
.dig_power = { \
|
||||
.mem_dslp = 0, \
|
||||
.peri_pd_en = 0, \
|
||||
}, \
|
||||
.clk_power = { \
|
||||
.xpd_xtal32k = 0, \
|
||||
.xpd_rc32k = 0, \
|
||||
.xpd_fosc = 0, \
|
||||
.pd_osc = 0 \
|
||||
}, \
|
||||
.xtal = { \
|
||||
.xpd_xtal = 0 \
|
||||
} \
|
||||
}
|
||||
|
||||
const pmu_lp_system_power_param_t * pmu_lp_system_power_param_default(pmu_lp_mode_t mode)
|
||||
{
|
||||
static const pmu_lp_system_power_param_t lp_power[] = {
|
||||
PMU_LP_ACTIVE_POWER_CONFIG_DEFAULT(),
|
||||
PMU_LP_SLEEP_POWER_CONFIG_DEFAULT()
|
||||
};
|
||||
assert(mode < ARRAY_SIZE(lp_power));
|
||||
return &lp_power[mode];
|
||||
}
|
||||
|
||||
#define PMU_LP_ACTIVE_ANALOG_CONFIG_DEFAULT() { \
|
||||
.regulator0 = { \
|
||||
.slp_xpd = 0, \
|
||||
.xpd = 1, \
|
||||
.slp_dbias = 0, \
|
||||
.dbias = LP_CALI_DBIAS_DEFAULT \
|
||||
}, \
|
||||
.regulator1 = { \
|
||||
.drv_b = 0x0 \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PMU_LP_SLEEP_ANALOG_CONFIG_DEFAULT() { \
|
||||
.bias = { \
|
||||
.xpd_bias = 0, \
|
||||
.dbg_atten = 0, \
|
||||
.pd_cur = 1, \
|
||||
.bias_sleep = 1, \
|
||||
}, \
|
||||
.regulator0 = { \
|
||||
.slp_xpd = 0, \
|
||||
.xpd = 1, \
|
||||
.slp_dbias = 0, \
|
||||
.dbias = 12 \
|
||||
}, \
|
||||
.regulator1 = { \
|
||||
.drv_b = 0x0 \
|
||||
} \
|
||||
}
|
||||
|
||||
const pmu_lp_system_analog_param_t * pmu_lp_system_analog_param_default(pmu_lp_mode_t mode)
|
||||
{
|
||||
static const pmu_lp_system_analog_param_t lp_analog[] = {
|
||||
PMU_LP_ACTIVE_ANALOG_CONFIG_DEFAULT(),
|
||||
PMU_LP_SLEEP_ANALOG_CONFIG_DEFAULT()
|
||||
};
|
||||
assert(mode < ARRAY_SIZE(lp_analog));
|
||||
return &lp_analog[mode];
|
||||
}
|
||||
@@ -0,0 +1,361 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <sys/param.h>
|
||||
#include <esp_types.h>
|
||||
#include "sdkconfig.h"
|
||||
#include "esp_err.h"
|
||||
#include "esp_attr.h"
|
||||
#include "soc/soc.h"
|
||||
#include "soc/rtc.h"
|
||||
#include "soc/pmu_struct.h"
|
||||
#include "esp_private/esp_pmu.h"
|
||||
#include "pmu_param.h"
|
||||
#include "hal/lp_aon_hal.h"
|
||||
#include "hal/efuse_ll.h"
|
||||
#include "hal/efuse_hal.h"
|
||||
#include "esp_hw_log.h"
|
||||
|
||||
ESP_HW_LOG_ATTR_TAG(TAG, "pmu_sleep");
|
||||
|
||||
#define HP(state) (PMU_MODE_HP_ ## state)
|
||||
#define LP(state) (PMU_MODE_LP_ ## state)
|
||||
|
||||
|
||||
static bool s_pmu_sleep_regdma_backup_enabled;
|
||||
|
||||
void pmu_sleep_enable_regdma_backup(void)
|
||||
{
|
||||
if(!s_pmu_sleep_regdma_backup_enabled){
|
||||
assert(PMU_instance()->hal);
|
||||
/* entry 0, 1, 2 is used by pmu HP_SLEEP and HP_ACTIVE, HP_SLEEP
|
||||
* and HP_MODEM or HP_MODEM and HP_ACTIVE states switching,
|
||||
* respectively. entry 3 is reserved, not used yet! */
|
||||
pmu_hal_hp_set_sleep_active_backup_enable(PMU_instance()->hal);
|
||||
pmu_hal_hp_set_sleep_modem_backup_enable(PMU_instance()->hal);
|
||||
pmu_hal_hp_set_modem_active_backup_enable(PMU_instance()->hal);
|
||||
s_pmu_sleep_regdma_backup_enabled = true;
|
||||
}
|
||||
}
|
||||
|
||||
void pmu_sleep_disable_regdma_backup(void)
|
||||
{
|
||||
if(s_pmu_sleep_regdma_backup_enabled){
|
||||
assert(PMU_instance()->hal);
|
||||
pmu_hal_hp_set_sleep_active_backup_disable(PMU_instance()->hal);
|
||||
pmu_hal_hp_set_sleep_modem_backup_disable(PMU_instance()->hal);
|
||||
pmu_hal_hp_set_modem_active_backup_disable(PMU_instance()->hal);
|
||||
s_pmu_sleep_regdma_backup_enabled = false;
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t pmu_sleep_calculate_lp_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period)
|
||||
{
|
||||
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
|
||||
/* LP core hardware wait time, microsecond */
|
||||
const int lp_wakeup_wait_time_us = rtc_time_slowclk_to_us(mc->lp.wakeup_wait_cycle, slowclk_period);
|
||||
const int lp_clk_switch_time_us = rtc_time_slowclk_to_us(mc->lp.clk_switch_cycle, slowclk_period);
|
||||
/* If XTAL is used as RTC_FAST clock source, it is started in LP_SLEEP -> LP_ACTIVE stage and the clock waiting time is counted into lp_hw_wait_time */
|
||||
const int lp_clk_power_on_wait_time_us = ((sleep_flags & PMU_SLEEP_PD_XTAL) && (sleep_flags & RTC_SLEEP_XTAL_AS_RTC_FAST)) \
|
||||
? mc->lp.xtal_wait_stable_time_us \
|
||||
: rtc_time_slowclk_to_us(mc->lp.clk_power_on_wait_cycle, slowclk_period);
|
||||
const int lp_control_wait_time_us = mc->lp.isolate_wait_time_us + mc->lp.reset_wait_time_us;
|
||||
const int lp_hw_wait_time_us = mc->lp.min_slp_time_us + mc->lp.analog_wait_time_us + lp_clk_power_on_wait_time_us \
|
||||
+ lp_wakeup_wait_time_us + lp_clk_switch_time_us + mc->lp.power_supply_wait_time_us \
|
||||
+ mc->lp.power_up_wait_time_us + lp_control_wait_time_us;
|
||||
|
||||
return (uint32_t)lp_hw_wait_time_us;
|
||||
}
|
||||
|
||||
uint32_t pmu_sleep_calculate_hp_hw_wait_time(uint32_t sleep_flags, uint32_t slowclk_period, uint32_t fastclk_period)
|
||||
{
|
||||
pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
|
||||
/* HP core hardware wait time, microsecond */
|
||||
const int hp_digital_power_up_wait_time_us = mc->hp.power_supply_wait_time_us + mc->hp.power_up_wait_time_us;
|
||||
const int hp_control_wait_time_us = mc->hp.isolate_wait_time_us + mc->hp.reset_wait_time_us;
|
||||
const int hp_regdma_wait_time_us = s_pmu_sleep_regdma_backup_enabled ? mc->hp.regdma_s2a_work_time_us : 0;
|
||||
/* If XTAL is not used as RTC_FAST clock source, it is started in HP_SLEEP -> HP_ACTIVE stage and the clock waiting time is counted into hp_hw_wait_time */
|
||||
const int hp_clock_wait_time_us = ((sleep_flags & PMU_SLEEP_PD_XTAL) && !(sleep_flags & RTC_SLEEP_XTAL_AS_RTC_FAST)) \
|
||||
? mc->hp.xtal_wait_stable_time_us + mc->hp.pll_wait_stable_time_us \
|
||||
: mc->hp.pll_wait_stable_time_us;
|
||||
|
||||
const int hp_hw_wait_time_us = mc->hp.analog_wait_time_us + hp_digital_power_up_wait_time_us + hp_regdma_wait_time_us \
|
||||
+ hp_clock_wait_time_us + hp_control_wait_time_us;
|
||||
return (uint32_t)hp_hw_wait_time_us;
|
||||
}
|
||||
|
||||
uint32_t pmu_sleep_calculate_hw_wait_time(uint32_t sleep_flags, soc_rtc_slow_clk_src_t slowclk_src, uint32_t slowclk_period, uint32_t fastclk_period)
|
||||
{
|
||||
const uint32_t lp_hw_wait_time_us = pmu_sleep_calculate_lp_hw_wait_time(sleep_flags, slowclk_period, fastclk_period);
|
||||
const uint32_t hp_hw_wait_time_us = pmu_sleep_calculate_hp_hw_wait_time(sleep_flags, slowclk_period, fastclk_period);
|
||||
|
||||
/* When the SOC wakeup (lp timer or GPIO wakeup) and Modem wakeup (Beacon wakeup) complete, the soc
|
||||
* wakeup will be delayed until the RF is turned on in Modem state.
|
||||
*
|
||||
* modem wakeup TBTT, RF on by HW
|
||||
* | |
|
||||
* \|/ \|/
|
||||
* PMU_HP_ACTIVE /------
|
||||
* PMU_HP_MODEM /------------//////////////////
|
||||
* PMU_HP_SLEEP ----------------------//////////////////
|
||||
* /|\ /|\ /|\ /|\ /|\ /|\
|
||||
* |<- some hw wait ->| | | |<- M2A switch ->|
|
||||
* | slow cycles & | soc wakeup | |
|
||||
* | FOSC cycles |<- S2M switch ->| |
|
||||
* | |
|
||||
* |<-- PMU guard time, also the maximum time for the SOC -->|
|
||||
* | wake-up delay |
|
||||
*/
|
||||
#if SOC_PM_SUPPORT_PMU_MODEM_STATE && CONFIG_ESP_WIFI_ENHANCED_LIGHT_SLEEP
|
||||
pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
|
||||
int min_slp_time_adjustment_us = 0;
|
||||
#if SOC_PM_PMU_MIN_SLP_SLOW_CLK_CYCLE_FIXED
|
||||
if (slowclk_src == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) {
|
||||
const uint32_t slowclk_period_fixed = rtc_clk_freq_to_period(SOC_CLK_RC_SLOW_FREQ_APPROX);
|
||||
const int min_slp_cycle_fixed = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period_fixed);
|
||||
const int min_slp_cycle_calib = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
|
||||
const int min_slp_cycle_diff = (min_slp_cycle_calib > min_slp_cycle_fixed) ? \
|
||||
(min_slp_cycle_calib - min_slp_cycle_fixed) : (min_slp_cycle_fixed - min_slp_cycle_calib);
|
||||
const int min_slp_time_diff = rtc_time_slowclk_to_us(min_slp_cycle_diff, slowclk_period_fixed);
|
||||
min_slp_time_adjustment_us = (min_slp_cycle_calib > min_slp_cycle_fixed) ? min_slp_time_diff : -min_slp_time_diff;
|
||||
}
|
||||
#endif
|
||||
const int rf_on_protect_time_us = mc->hp.regdma_rf_on_work_time_us;
|
||||
const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us + mc->hp.clock_domain_sync_time_us + min_slp_time_adjustment_us;
|
||||
#else
|
||||
const int rf_on_protect_time_us = 0;
|
||||
const int total_hw_wait_time_us = lp_hw_wait_time_us + hp_hw_wait_time_us;
|
||||
#endif
|
||||
return total_hw_wait_time_us + rf_on_protect_time_us;
|
||||
}
|
||||
|
||||
#define rtc_time_us_to_fastclk(time_us, period) rtc_time_us_to_slowclk((time_us), (period))
|
||||
|
||||
static inline pmu_sleep_param_config_t * pmu_sleep_param_config_default(
|
||||
pmu_sleep_param_config_t *param,
|
||||
pmu_sleep_power_config_t *power, /* We'll use the runtime power parameter to determine some hardware parameters */
|
||||
const uint32_t sleep_flags,
|
||||
const uint32_t adjustment,
|
||||
soc_rtc_slow_clk_src_t slowclk_src,
|
||||
const uint32_t slowclk_period,
|
||||
const uint32_t fastclk_period
|
||||
)
|
||||
{
|
||||
const pmu_sleep_machine_constant_t *mc = (pmu_sleep_machine_constant_t *)PMU_instance()->mc;
|
||||
|
||||
param->hp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->hp.min_slp_time_us, slowclk_period);
|
||||
param->hp_sys.analog_wait_target_cycle = rtc_time_us_to_fastclk(mc->hp.analog_wait_time_us, fastclk_period);
|
||||
param->hp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_supply_wait_time_us, fastclk_period);
|
||||
param->hp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->hp.power_up_wait_time_us, fastclk_period);
|
||||
param->hp_sys.pll_stable_wait_cycle = rtc_time_us_to_fastclk(mc->hp.pll_wait_stable_time_us, fastclk_period);
|
||||
param->hp_sys.isolate_wait_cycle = rtc_time_us_to_fastclk(mc->hp.isolate_wait_time_us, fastclk_period);
|
||||
param->hp_sys.reset_wait_cycle = rtc_time_us_to_fastclk(mc->hp.reset_wait_time_us, fastclk_period);
|
||||
|
||||
param->lp_sys.min_slp_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.min_slp_time_us, slowclk_period);
|
||||
param->lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(mc->lp.analog_wait_time_us, slowclk_period);
|
||||
param->lp_sys.digital_power_supply_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_supply_wait_time_us, fastclk_period);
|
||||
param->lp_sys.digital_power_up_wait_cycle = rtc_time_us_to_fastclk(mc->lp.power_up_wait_time_us, fastclk_period);
|
||||
param->lp_sys.isolate_wait_cycle = rtc_time_us_to_fastclk(mc->lp.isolate_wait_time_us, fastclk_period);
|
||||
param->lp_sys.reset_wait_cycle = rtc_time_us_to_fastclk(mc->lp.reset_wait_time_us, fastclk_period);
|
||||
|
||||
if (power->hp_sys.xtal.xpd_xtal) {
|
||||
param->hp_lp.xtal_stable_wait_slow_clk_cycle = rtc_time_us_to_slowclk(mc->lp.xtal_wait_stable_time_us, slowclk_period);
|
||||
} else {
|
||||
param->hp_lp.xtal_stable_wait_cycle = rtc_time_us_to_fastclk(mc->hp.xtal_wait_stable_time_us, fastclk_period);
|
||||
}
|
||||
return param;
|
||||
}
|
||||
|
||||
const pmu_sleep_config_t* pmu_sleep_config_default(
|
||||
pmu_sleep_config_t *config,
|
||||
uint32_t sleep_flags,
|
||||
uint32_t clk_flags,
|
||||
uint32_t adjustment,
|
||||
soc_rtc_slow_clk_src_t slowclk_src,
|
||||
uint32_t slowclk_period,
|
||||
uint32_t fastclk_period,
|
||||
bool dslp
|
||||
)
|
||||
{
|
||||
pmu_sleep_power_config_t power_default = PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags);
|
||||
|
||||
if (dslp) {
|
||||
config->param.lp_sys.analog_wait_target_cycle = rtc_time_us_to_slowclk(PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US, slowclk_period);
|
||||
|
||||
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags);
|
||||
config->digital = digital_default;
|
||||
|
||||
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags);
|
||||
config->analog = analog_default;
|
||||
} else {
|
||||
// Get light sleep digital_default
|
||||
pmu_sleep_digital_config_t digital_default = PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags);
|
||||
config->digital = digital_default;
|
||||
|
||||
// Get light sleep analog default
|
||||
pmu_sleep_analog_config_t analog_default = PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags);
|
||||
|
||||
if (!(sleep_flags & PMU_SLEEP_PD_XTAL))
|
||||
{
|
||||
// Analog parameters in HP_SLEEP
|
||||
analog_default.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
|
||||
analog_default.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
|
||||
analog_default.hp_sys.analog.dbg_atten = PMU_DBG_ATTEN_ACTIVE_DEFAULT;
|
||||
analog_default.hp_sys.analog.dbias = HP_CALI_ACTIVE_DBIAS_DEFAULT;
|
||||
|
||||
// Analog parameters in LP_SLEEP
|
||||
analog_default.lp_sys[LP(SLEEP)].analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
|
||||
analog_default.lp_sys[LP(SLEEP)].analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
|
||||
analog_default.lp_sys[LP(SLEEP)].analog.dbg_atten = PMU_DBG_ATTEN_ACTIVE_DEFAULT;
|
||||
}
|
||||
config->analog = analog_default;
|
||||
}
|
||||
|
||||
if (sleep_flags & RTC_SLEEP_XTAL_AS_RTC_FAST) {
|
||||
// Keep XTAL on in HP_SLEEP state if it is the clock source of RTC_FAST
|
||||
power_default.hp_sys.xtal.xpd_xtal = 1;
|
||||
config->analog.hp_sys.analog.pd_cur = PMU_PD_CUR_SLEEP_ON;
|
||||
config->analog.hp_sys.analog.bias_sleep = PMU_BIASSLP_SLEEP_ON;
|
||||
config->analog.hp_sys.analog.dbg_atten = PMU_DBG_ATTEN_ACTIVE_DEFAULT;
|
||||
config->analog.hp_sys.analog.dbias = HP_CALI_ACTIVE_DBIAS_DEFAULT;
|
||||
}
|
||||
|
||||
config->power = power_default;
|
||||
pmu_sleep_param_config_t param_default = PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags);
|
||||
config->param = *pmu_sleep_param_config_default(¶m_default, &power_default, sleep_flags, adjustment, slowclk_src, slowclk_period, fastclk_period);
|
||||
|
||||
return config;
|
||||
}
|
||||
|
||||
static void pmu_sleep_power_init(pmu_context_t *ctx, const pmu_sleep_power_config_t *power, bool dslp)
|
||||
{
|
||||
pmu_ll_hp_set_dig_power(ctx->hal->dev, HP(SLEEP), power->hp_sys.dig_power.val);
|
||||
pmu_ll_hp_set_clk_power(ctx->hal->dev, HP(SLEEP), power->hp_sys.clk_power.val);
|
||||
pmu_ll_hp_set_xtal_xpd (ctx->hal->dev, HP(SLEEP), power->hp_sys.xtal.xpd_xtal);
|
||||
|
||||
pmu_ll_lp_set_dig_power(ctx->hal->dev, LP(ACTIVE), power->lp_sys[LP(ACTIVE)].dig_power.val);
|
||||
pmu_ll_lp_set_clk_power(ctx->hal->dev, LP(ACTIVE), power->lp_sys[LP(ACTIVE)].clk_power.val);
|
||||
|
||||
pmu_ll_lp_set_dig_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].dig_power.val);
|
||||
pmu_ll_lp_set_clk_power(ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].clk_power.val);
|
||||
pmu_ll_lp_set_xtal_xpd (ctx->hal->dev, LP(SLEEP), power->lp_sys[LP(SLEEP)].xtal.xpd_xtal);
|
||||
}
|
||||
|
||||
static void pmu_sleep_digital_init(pmu_context_t *ctx, const pmu_sleep_digital_config_t *dig)
|
||||
{
|
||||
pmu_ll_hp_set_dig_pad_slp_sel (ctx->hal->dev, HP(SLEEP), dig->syscntl.dig_pad_slp_sel);
|
||||
pmu_ll_hp_set_hold_all_lp_pad (ctx->hal->dev, HP(SLEEP), dig->syscntl.lp_pad_hold_all);
|
||||
pmu_ll_hp_set_c_channel_enable (ctx->hal->dev, HP(SLEEP), dig->syscntl.c_channel);
|
||||
}
|
||||
|
||||
static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_config_t *analog, bool dslp)
|
||||
{
|
||||
assert(ctx->hal);
|
||||
pmu_ll_hp_set_current_power_off (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.pd_cur);
|
||||
pmu_ll_hp_set_bias_sleep_enable (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.bias_sleep);
|
||||
pmu_ll_hp_set_regulator_sleep_memory_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_mem_xpd);
|
||||
pmu_ll_hp_set_regulator_sleep_logic_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_logic_xpd);
|
||||
pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd);
|
||||
pmu_ll_hp_set_regulator_sleep_logic_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.slp_logic_dbias);
|
||||
pmu_ll_hp_set_dbg_atten (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbg_atten);
|
||||
pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias);
|
||||
pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b);
|
||||
|
||||
pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.slp_dbias);
|
||||
pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.dbias);
|
||||
pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.drv_b);
|
||||
|
||||
pmu_ll_lp_set_current_power_off (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur);
|
||||
pmu_ll_lp_set_bias_sleep_enable (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.bias_sleep);
|
||||
pmu_ll_lp_set_regulator_xpd (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.xpd);
|
||||
pmu_ll_lp_set_regulator_slp_xpd (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.slp_xpd);
|
||||
pmu_ll_lp_set_regulator_sleep_dbias(ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.slp_dbias);
|
||||
pmu_ll_lp_set_regulator_dbias (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbias);
|
||||
pmu_ll_lp_set_dbg_atten (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbg_atten);
|
||||
pmu_ll_lp_set_regulator_driver_bar (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.drv_b);
|
||||
|
||||
pmu_ll_lp_set_regulator_slp_xpd (ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.slp_xpd);
|
||||
pmu_ll_lp_set_regulator_xpd (ctx->hal->dev, LP(ACTIVE), analog->lp_sys[LP(ACTIVE)].analog.xpd);
|
||||
}
|
||||
|
||||
static void pmu_sleep_param_init(pmu_context_t *ctx, const pmu_sleep_param_config_t *param, bool dslp)
|
||||
{
|
||||
assert(ctx->hal);
|
||||
pmu_ll_hp_set_min_sleep_cycle(ctx->hal->dev, param->hp_sys.min_slp_slow_clk_cycle);
|
||||
pmu_ll_lp_set_min_sleep_cycle(ctx->hal->dev, param->lp_sys.min_slp_slow_clk_cycle);
|
||||
|
||||
pmu_ll_hp_set_analog_wait_target_cycle(ctx->hal->dev, param->hp_sys.analog_wait_target_cycle);
|
||||
pmu_ll_lp_set_analog_wait_target_cycle(ctx->hal->dev, param->lp_sys.analog_wait_target_cycle);
|
||||
|
||||
pmu_hal_hp_set_digital_power_up_wait_cycle(ctx->hal, param->hp_sys.digital_power_supply_wait_cycle, param->hp_sys.digital_power_up_wait_cycle);
|
||||
pmu_hal_lp_set_digital_power_up_wait_cycle(ctx->hal, param->lp_sys.digital_power_supply_wait_cycle, param->lp_sys.digital_power_up_wait_cycle);
|
||||
|
||||
pmu_hal_hp_set_control_ready_wait_cycle(ctx->hal, param->hp_sys.isolate_wait_cycle, param->hp_sys.reset_wait_cycle);
|
||||
pmu_hal_lp_set_control_ready_wait_cycle(ctx->hal, param->lp_sys.isolate_wait_cycle, param->lp_sys.reset_wait_cycle);
|
||||
|
||||
pmu_ll_set_xtal_stable_wait_cycle(ctx->hal->dev, param->hp_lp.xtal_stable_wait_slow_clk_cycle);
|
||||
pmu_ll_set_pll_stable_wait_cycle(ctx->hal->dev, param->hp_sys.pll_stable_wait_cycle);
|
||||
}
|
||||
|
||||
bool pmu_sleep_pll_already_enabled(void)
|
||||
{
|
||||
return (pmu_ll_get_sysclk_sleep_select_state(PMU_instance()->hal->dev) != 0);
|
||||
}
|
||||
|
||||
void pmu_sleep_init(const pmu_sleep_config_t *config, bool dslp)
|
||||
{
|
||||
assert(PMU_instance());
|
||||
pmu_sleep_power_init(PMU_instance(), &config->power, dslp);
|
||||
pmu_sleep_digital_init(PMU_instance(), &config->digital);
|
||||
pmu_sleep_analog_init(PMU_instance(), &config->analog, dslp);
|
||||
pmu_sleep_param_init(PMU_instance(), &config->param, dslp);
|
||||
}
|
||||
|
||||
IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
|
||||
{
|
||||
lp_aon_hal_inform_wakeup_type(dslp);
|
||||
|
||||
pmu_ll_hp_set_wakeup_enable(&PMU, wakeup_opt);
|
||||
pmu_ll_hp_set_reject_enable(&PMU, reject_opt);
|
||||
|
||||
pmu_ll_hp_clear_wakeup_intr_status(&PMU);
|
||||
pmu_ll_hp_clear_reject_intr_status(&PMU);
|
||||
pmu_ll_hp_clear_reject_cause(&PMU);
|
||||
|
||||
/* Start entry into sleep mode */
|
||||
pmu_ll_hp_set_sleep_enable(&PMU);
|
||||
|
||||
while (!pmu_ll_hp_is_sleep_wakeup(&PMU) &&
|
||||
!pmu_ll_hp_is_sleep_reject(&PMU)) {
|
||||
;
|
||||
}
|
||||
return pmu_sleep_finish(dslp);
|
||||
}
|
||||
|
||||
IRAM_ATTR uint32_t pmu_sleep_get_wakeup_cause(void)
|
||||
{
|
||||
return pmu_ll_hp_get_wakeup_cause(PMU_instance()->hal->dev);
|
||||
}
|
||||
IRAM_ATTR uint32_t pmu_sleep_get_reject_cause(void)
|
||||
{
|
||||
return pmu_ll_hp_get_reject_cause(PMU_instance()->hal->dev);
|
||||
}
|
||||
|
||||
IRAM_ATTR bool pmu_sleep_finish(bool dslp)
|
||||
{
|
||||
#ifndef CONFIG_IDF_ENV_FPGA
|
||||
// Wait eFuse memory update done.
|
||||
while(efuse_ll_get_controller_state() != EFUSE_CONTROLLER_STATE_IDLE);
|
||||
#endif
|
||||
return pmu_ll_hp_is_sleep_reject(&PMU);
|
||||
}
|
||||
|
||||
uint32_t pmu_sleep_get_wakup_retention_cost(void)
|
||||
{
|
||||
return 685;
|
||||
}
|
||||
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define PMU_SDIO_WAKEUP_EN BIT(0)
|
||||
#define PMU_LP_CORE_WAKEUP_EN BIT(1)
|
||||
#define PMU_GPIO_WAKEUP_EN BIT(2)
|
||||
#define PMU_USB_WAKEUP_EN BIT(3)
|
||||
#define PMU_UART4_WAKEUP_EN BIT(4)
|
||||
#define PMU_UART3_WAKEUP_EN BIT(5)
|
||||
#define PMU_UART2_WAKEUP_EN BIT(6)
|
||||
#define PMU_UART1_WAKEUP_EN BIT(7)
|
||||
#define PMU_UART0_WAKEUP_EN BIT(8)
|
||||
#define PMU_LP_GPIO_WAKEUP_EN BIT(9)
|
||||
#define PMU_LP_UART_WAKEUP_EN BIT(10)
|
||||
#define PMU_TOUCH_WAKEUP_EN BIT(11)
|
||||
#define PMU_EXT1_WAKEUP_EN BIT(12)
|
||||
#define PMU_RTC_TIMER_WAKEUP_EN BIT(13)
|
||||
#define PMU_BOD_WAKEUP_EN BIT(14)
|
||||
#define PMU_VBAT_UNDERVOLT_WAKEUP_EN BIT(15)
|
||||
#define PMU_LP_CORE_TRAP_WAKEUP_EN BIT(16)
|
||||
#define PMU_ETM_WAKEUP_EN BIT(17)
|
||||
#define PMU_LP_TIMER1_WAKEUP_EN BIT(18)
|
||||
#define PMU_LP_I2S_WAKEUP_EN BIT(19)
|
||||
#define PMU_WIFI_SOC_WAKEUP_EN BIT(22)
|
||||
#define PMU_WIFI_BEACON_WAKEUP_EN BIT(23)
|
||||
#define PMU_BLE_SOC_WAKEUP_EN BIT(24)
|
||||
|
||||
|
||||
// BIT order in PLL control registers in PMU
|
||||
#define PMU_CPLL_CTRL BIT(0)
|
||||
#define PMU_SPLL_CTRL BIT(1)
|
||||
#define PMU_APLL_CTRL BIT(2)
|
||||
#define PMU_SDIOPLL_CTRL BIT(3)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,526 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <esp_types.h>
|
||||
#include "soc/pmu_struct.h"
|
||||
#include "hal/pmu_hal.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define HP_CALI_DBIAS_DEFAULT 28
|
||||
#define LP_CALI_DBIAS_DEFAULT 28
|
||||
#define HP_CALI_DBIAS_SLP_1V1 22
|
||||
#define LP_CALI_DBIAS_SLP_1V1 22
|
||||
|
||||
#define HP_CALI_ACTIVE_DBIAS_DEFAULT 24 // For HP regulator
|
||||
|
||||
// FOR XTAL FORCE PU IN SLEEP
|
||||
#define PMU_PD_CUR_SLEEP_ON 0
|
||||
#define PMU_BIASSLP_SLEEP_ON 0
|
||||
|
||||
// FOR BOTH LIGHTSLEEP & DEEPSLEEP
|
||||
#define PMU_PD_CUR_SLEEP_DEFAULT 1
|
||||
#define PMU_BIASSLP_SLEEP_DEFAULT 1
|
||||
#define PMU_LP_XPD_SLEEP_DEFAULT 1
|
||||
#define PMU_LP_SLP_XPD_SLEEP_DEFAULT 0
|
||||
#define PMU_LP_SLP_DBIAS_SLEEP_DEFAULT 0
|
||||
|
||||
// FOR LIGHTSLEEP
|
||||
#define PMU_HP_DRVB_LIGHTSLEEP 0
|
||||
#define PMU_LP_DRVB_LIGHTSLEEP 0
|
||||
#define PMU_HP_XPD_LIGHTSLEEP 1
|
||||
|
||||
#define PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT 0
|
||||
#define PMU_HP_DBIAS_LIGHTSLEEP_0V6 1
|
||||
#define PMU_LP_DBIAS_LIGHTSLEEP_0V7 12
|
||||
|
||||
// FOR LIGHTSLEEP: XTAL FORCE PU
|
||||
#define PMU_DBG_ATTEN_ACTIVE_DEFAULT 0
|
||||
|
||||
// FOR DEEPSLEEP
|
||||
#define PMU_DBG_HP_DEEPSLEEP 0
|
||||
#define PMU_HP_XPD_DEEPSLEEP 0
|
||||
#define PMU_LP_DRVB_DEEPSLEEP 0
|
||||
|
||||
#define PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT 12
|
||||
#define PMU_LP_DBIAS_DEEPSLEEP_0V7 23
|
||||
|
||||
typedef struct {
|
||||
pmu_hp_dig_power_reg_t dig_power;
|
||||
pmu_hp_clk_power_reg_t clk_power;
|
||||
pmu_hp_xtal_reg_t xtal;
|
||||
} pmu_hp_system_power_param_t;
|
||||
|
||||
const pmu_hp_system_power_param_t* pmu_hp_system_power_param_default(pmu_hp_mode_t mode);
|
||||
|
||||
typedef struct {
|
||||
struct {
|
||||
uint32_t clock[2];
|
||||
} icg_func;
|
||||
struct {
|
||||
uint32_t clock[2];
|
||||
} icg_apb;
|
||||
pmu_hp_icg_modem_reg_t icg_modem;
|
||||
pmu_hp_sysclk_reg_t sysclk;
|
||||
} pmu_hp_system_clock_param_t;
|
||||
|
||||
const pmu_hp_system_clock_param_t* pmu_hp_system_clock_param_default(pmu_hp_mode_t mode);
|
||||
|
||||
typedef struct {
|
||||
pmu_hp_sys_cntl_reg_t syscntl;
|
||||
} pmu_hp_system_digital_param_t;
|
||||
|
||||
const pmu_hp_system_digital_param_t* pmu_hp_system_digital_param_default(pmu_hp_mode_t mode);
|
||||
|
||||
typedef struct {
|
||||
pmu_hp_bias_reg_t bias;
|
||||
pmu_hp_regulator0_reg_t regulator0;
|
||||
pmu_hp_regulator1_reg_t regulator1;
|
||||
} pmu_hp_system_analog_param_t;
|
||||
|
||||
const pmu_hp_system_analog_param_t* pmu_hp_system_analog_param_default(pmu_hp_mode_t mode);
|
||||
|
||||
typedef struct {
|
||||
pmu_hp_backup_reg_t retention;
|
||||
uint32_t backup_clk[2];
|
||||
} pmu_hp_system_retention_param_t;
|
||||
|
||||
const pmu_hp_system_retention_param_t* pmu_hp_system_retention_param_default(pmu_hp_mode_t mode);
|
||||
|
||||
typedef struct {
|
||||
pmu_lp_dig_power_reg_t dig_power;
|
||||
pmu_lp_clk_power_reg_t clk_power;
|
||||
pmu_lp_xtal_reg_t xtal;
|
||||
} pmu_lp_system_power_param_t;
|
||||
|
||||
const pmu_lp_system_power_param_t* pmu_lp_system_power_param_default(pmu_lp_mode_t mode);
|
||||
|
||||
typedef struct {
|
||||
pmu_lp_bias_reg_t bias;
|
||||
pmu_lp_regulator0_reg_t regulator0;
|
||||
pmu_lp_regulator1_reg_t regulator1;
|
||||
} pmu_lp_system_analog_param_t;
|
||||
|
||||
const pmu_lp_system_analog_param_t* pmu_lp_system_analog_param_default(pmu_lp_mode_t mode);
|
||||
|
||||
|
||||
/* Following software configuration instance type from pmu_struct.h used for the PMU state machine in sleep flow*/
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0 : 20;
|
||||
uint32_t vdd_spi_pd_en : 1;
|
||||
uint32_t pd_hp_alive_pd_en : 1;
|
||||
uint32_t mem_dslp : 1;
|
||||
uint32_t pd_hp_mem_pd_en : 4;
|
||||
uint32_t pd_modem_top_pd_en: 1;
|
||||
uint32_t pd_hp_cnnt_pd_en : 1;
|
||||
uint32_t pd_hp_cpu_pd_en : 1;
|
||||
uint32_t pd_modem_pwr_pd_en: 1;
|
||||
uint32_t pd_top_pd_en : 1;
|
||||
};
|
||||
struct {
|
||||
uint32_t reserved_1 : 19;
|
||||
uint32_t xpd_xtalx2 : 1;
|
||||
uint32_t i2c_iso_en : 1;
|
||||
uint32_t i2c_retention : 1;
|
||||
uint32_t xpd_bb_i2c : 1;
|
||||
uint32_t xpd_pll_i2c : 4;
|
||||
uint32_t xpd_pll : 4;
|
||||
uint32_t reserved_2 : 1;
|
||||
};
|
||||
struct {
|
||||
uint32_t reserved_3 : 31;
|
||||
uint32_t xpd_xtal : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_hp_power_t;
|
||||
|
||||
typedef union {
|
||||
struct {
|
||||
uint32_t reserved_0 : 30;
|
||||
uint32_t mem_dslp : 1;
|
||||
uint32_t peri_pd_en : 1;
|
||||
};
|
||||
struct {
|
||||
uint32_t reserved_1 : 28;
|
||||
uint32_t xpd_xtal32k: 1;
|
||||
uint32_t xpd_rc32k : 1;
|
||||
uint32_t xpd_fosc : 1;
|
||||
uint32_t pd_osc : 1;
|
||||
};
|
||||
struct {
|
||||
uint32_t reserved_2 : 31;
|
||||
uint32_t xpd_xtal : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pmu_lp_power_t;
|
||||
|
||||
typedef struct {
|
||||
struct {
|
||||
uint32_t reserved_0 : 25;
|
||||
uint32_t xpd_bias : 1;
|
||||
uint32_t dbg_atten : 4;
|
||||
uint32_t pd_cur : 1;
|
||||
uint32_t bias_sleep : 1;
|
||||
};
|
||||
struct {
|
||||
uint32_t reserved_1 : 15;
|
||||
uint32_t slp_connect_en : 1;
|
||||
uint32_t slp_mem_xpd : 1;
|
||||
uint32_t slp_logic_xpd : 1;
|
||||
uint32_t xpd : 1;
|
||||
uint32_t slp_mem_dbias : 4;
|
||||
uint32_t slp_logic_dbias: 4;
|
||||
uint32_t dbias : 5;
|
||||
};
|
||||
struct {
|
||||
uint32_t reserved_2 : 8;
|
||||
uint32_t drv_b : 24;
|
||||
};
|
||||
} pmu_hp_analog_t;
|
||||
|
||||
typedef struct {
|
||||
struct {
|
||||
uint32_t reserved_0: 25;
|
||||
uint32_t xpd_bias : 1;
|
||||
uint32_t dbg_atten : 4;
|
||||
uint32_t pd_cur : 1;
|
||||
uint32_t bias_sleep: 1;
|
||||
};
|
||||
struct {
|
||||
uint32_t reserved_1: 21;
|
||||
uint32_t slp_xpd : 1;
|
||||
uint32_t xpd : 1;
|
||||
uint32_t slp_dbias : 4;
|
||||
uint32_t dbias : 5;
|
||||
};
|
||||
struct {
|
||||
uint32_t reserved_2: 28;
|
||||
uint32_t drv_b : 4;
|
||||
};
|
||||
} pmu_lp_analog_t;
|
||||
|
||||
typedef struct {
|
||||
uint32_t modem_wakeup_wait_cycle;
|
||||
uint16_t analog_wait_target_cycle;
|
||||
uint16_t digital_power_down_wait_cycle;
|
||||
uint16_t digital_power_supply_wait_cycle;
|
||||
uint16_t digital_power_up_wait_cycle;
|
||||
uint16_t pll_stable_wait_cycle;
|
||||
uint8_t modify_icg_cntl_wait_cycle;
|
||||
uint8_t switch_icg_cntl_wait_cycle;
|
||||
uint8_t min_slp_slow_clk_cycle;
|
||||
uint8_t isolate_wait_cycle;
|
||||
uint8_t reset_wait_cycle;
|
||||
} pmu_hp_param_t;
|
||||
|
||||
typedef struct {
|
||||
uint16_t digital_power_supply_wait_cycle;
|
||||
uint8_t min_slp_slow_clk_cycle;
|
||||
uint8_t analog_wait_target_cycle;
|
||||
uint8_t digital_power_down_wait_cycle;
|
||||
uint8_t digital_power_up_wait_cycle;
|
||||
uint8_t isolate_wait_cycle;
|
||||
uint8_t reset_wait_cycle;
|
||||
} pmu_lp_param_t;
|
||||
|
||||
typedef struct {
|
||||
union {
|
||||
uint16_t xtal_stable_wait_slow_clk_cycle;
|
||||
uint16_t xtal_stable_wait_cycle;
|
||||
};
|
||||
} pmu_hp_lp_param_t;
|
||||
|
||||
#define PMU_HP_SLEEP_MIN_SLOW_CLK_CYCLES (10)
|
||||
#define PMU_LP_SLEEP_MIN_SLOW_CLK_CYCLES (10)
|
||||
|
||||
#define PMU_HP_WAKEUP_DELAY_CYCLES (0)
|
||||
#define PMU_HP_XTAL_STABLE_WAIT_CYCLES (3155) /* Not used, Fast OSC as PMU work clock source is about 201 us, corresponding to PMU_LP_XTAL_STABLE_WAIT_SLOW_CLK_CYCLES */
|
||||
#define PMU_HP_PLL_STABLE_WAIT_CYCLES (2)
|
||||
#define PMU_HP_ANALOG_WAIT_TARGET_CYCLES (23) /* Slow OSC as PMU work clock source is about 400 us */
|
||||
#define PMU_HP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES (32)
|
||||
#define PMU_HP_DIGITAL_POWER_UP_WAIT_CYCLES (32)
|
||||
#define PMU_HP_MODEM_WAKEUP_WAIT_CYCLES (20700) /* Fast OSC as PMU work clock source is about 1318.6 us */
|
||||
|
||||
#define PMU_LP_WAKEUP_DELAY_CYCLES (0)
|
||||
#define PMU_LP_XTAL_STABLE_WAIT_SLOW_CLK_CYCLES (30) /* Slow OSC as PMU slow clock source is about 201 us */
|
||||
#define PMU_LP_ANALOG_WAIT_TARGET_CYCLES (23) /* Slow OSC as PMU slow clock source is about 154 us */
|
||||
#define PMU_LP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES (32) /* Fast OSC as PMU work clock source is about 2 us */
|
||||
#define PMU_LP_DIGITAL_POWER_UP_WAIT_CYCLES (32) /* Fast OSC as PMU work clock source is about 2 us */
|
||||
|
||||
#define PMU_LP_ANALOG_WAIT_TARGET_TIME_DSLP_US (500) /* Slow OSC as PMU slow clock source in deepsleep is about 500 us */
|
||||
|
||||
typedef struct {
|
||||
struct {
|
||||
pmu_hp_power_t dig_power;
|
||||
pmu_hp_power_t clk_power;
|
||||
pmu_hp_power_t xtal;
|
||||
} hp_sys;
|
||||
struct {
|
||||
pmu_lp_power_t dig_power;
|
||||
pmu_lp_power_t clk_power;
|
||||
pmu_lp_power_t xtal;
|
||||
} lp_sys[PMU_MODE_LP_MAX];
|
||||
} pmu_sleep_power_config_t;
|
||||
|
||||
#define PMU_SLEEP_POWER_CONFIG_DEFAULT(sleep_flags) { \
|
||||
.hp_sys = { \
|
||||
.dig_power = { \
|
||||
.vdd_spi_pd_en = ((sleep_flags) & PMU_SLEEP_PD_VDDSDIO) ? 1 : 0, \
|
||||
.pd_hp_alive_pd_en = 0, \
|
||||
.pd_modem_top_pd_en = ((sleep_flags) & PMU_SLEEP_PD_MODEM) ? 1 : 0, \
|
||||
.pd_hp_cnnt_pd_en = ((sleep_flags) & PMU_SLEEP_PD_CNNT) ? 1 : 0, \
|
||||
.pd_hp_cpu_pd_en = ((sleep_flags) & PMU_SLEEP_PD_CPU) ? 1 : 0, \
|
||||
.pd_modem_pwr_pd_en = 0, \
|
||||
.pd_top_pd_en = ((sleep_flags) & PMU_SLEEP_PD_TOP) ? 1 : 0, \
|
||||
.pd_hp_mem_pd_en = 0, \
|
||||
.mem_dslp = 0, \
|
||||
}, \
|
||||
.clk_power = { \
|
||||
.xpd_xtalx2 = 0, \
|
||||
.i2c_iso_en = 1, \
|
||||
.i2c_retention = 1, \
|
||||
.xpd_bb_i2c = 0, \
|
||||
.xpd_pll_i2c = 0, \
|
||||
.xpd_pll = 0 \
|
||||
}, \
|
||||
.xtal = { \
|
||||
.xpd_xtal = ((sleep_flags) & PMU_SLEEP_PD_XTAL) ? 0 : 1, \
|
||||
} \
|
||||
}, \
|
||||
.lp_sys[PMU_MODE_LP_ACTIVE] = { \
|
||||
.dig_power = { \
|
||||
.peri_pd_en = 0, \
|
||||
.mem_dslp = 0 \
|
||||
}, \
|
||||
.clk_power = { \
|
||||
.xpd_xtal32k = ((sleep_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1, \
|
||||
.xpd_rc32k = ((sleep_flags) & PMU_SLEEP_PD_RC32K) ? 0 : 1, \
|
||||
.xpd_fosc = 1 \
|
||||
} \
|
||||
}, \
|
||||
.lp_sys[PMU_MODE_LP_SLEEP] = { \
|
||||
.dig_power = { \
|
||||
.peri_pd_en = ((sleep_flags) & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
|
||||
.mem_dslp = 0 \
|
||||
}, \
|
||||
.clk_power = { \
|
||||
.xpd_xtal32k = ((sleep_flags) & PMU_SLEEP_PD_XTAL32K) ? 0 : 1, \
|
||||
.xpd_rc32k = ((sleep_flags) & PMU_SLEEP_PD_RC32K) ? 0 : 1, \
|
||||
.xpd_fosc = ((sleep_flags) & PMU_SLEEP_PD_RC_FAST) ? 0 : 1 \
|
||||
}, \
|
||||
.xtal = { \
|
||||
.xpd_xtal = ((sleep_flags) & PMU_SLEEP_PD_XTAL) ? 0 : 1, \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
pmu_hp_sys_cntl_reg_t syscntl;
|
||||
} pmu_sleep_digital_config_t;
|
||||
|
||||
|
||||
#define PMU_SLEEP_DIGITAL_DSLP_CONFIG_DEFAULT(sleep_flags) { \
|
||||
.syscntl = { \
|
||||
.dig_pad_slp_sel = 0, \
|
||||
.lp_pad_hold_all = (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
|
||||
.c_channel = (sleep_flags & PMU_SLEEP_PD_TOP) ? 0 : 1 \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PMU_SLEEP_DIGITAL_LSLP_CONFIG_DEFAULT(sleep_flags) { \
|
||||
.syscntl = { \
|
||||
.dig_pad_slp_sel = 0, \
|
||||
.lp_pad_hold_all = (sleep_flags & PMU_SLEEP_PD_LP_PERIPH) ? 1 : 0, \
|
||||
.c_channel = (sleep_flags & PMU_SLEEP_PD_TOP) ? 0 : 1 \
|
||||
} \
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
struct {
|
||||
pmu_hp_analog_t analog;
|
||||
} hp_sys;
|
||||
struct {
|
||||
pmu_lp_analog_t analog;
|
||||
} lp_sys[PMU_MODE_LP_MAX];
|
||||
} pmu_sleep_analog_config_t;
|
||||
|
||||
#define PMU_SLEEP_ANALOG_LSLP_CONFIG_DEFAULT(sleep_flags) { \
|
||||
.hp_sys = { \
|
||||
.analog = { \
|
||||
.drv_b = PMU_HP_DRVB_LIGHTSLEEP, \
|
||||
.pd_cur = PMU_PD_CUR_SLEEP_DEFAULT, \
|
||||
.bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \
|
||||
.xpd = PMU_HP_XPD_LIGHTSLEEP, \
|
||||
.dbg_atten = PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT, \
|
||||
.dbias = PMU_HP_DBIAS_LIGHTSLEEP_0V6 \
|
||||
} \
|
||||
}, \
|
||||
.lp_sys[PMU_MODE_LP_ACTIVE] = { \
|
||||
.analog = { \
|
||||
.slp_xpd = 0, \
|
||||
.slp_dbias = 0, \
|
||||
.xpd = 1, \
|
||||
.dbias = 29, \
|
||||
.drv_b = 0x0 \
|
||||
} \
|
||||
}, \
|
||||
.lp_sys[PMU_MODE_LP_SLEEP] = { \
|
||||
.analog = { \
|
||||
.drv_b = PMU_LP_DRVB_LIGHTSLEEP, \
|
||||
.pd_cur = PMU_PD_CUR_SLEEP_DEFAULT, \
|
||||
.bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \
|
||||
.slp_xpd = PMU_LP_SLP_XPD_SLEEP_DEFAULT, \
|
||||
.slp_dbias = PMU_LP_SLP_DBIAS_SLEEP_DEFAULT, \
|
||||
.xpd = PMU_LP_XPD_SLEEP_DEFAULT, \
|
||||
.dbg_atten = PMU_DBG_ATTEN_LIGHTSLEEP_DEFAULT, \
|
||||
.dbias = PMU_LP_DBIAS_LIGHTSLEEP_0V7 \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
|
||||
#define PMU_SLEEP_ANALOG_DSLP_CONFIG_DEFAULT(sleep_flags) { \
|
||||
.hp_sys = { \
|
||||
.analog = { \
|
||||
.pd_cur = PMU_PD_CUR_SLEEP_DEFAULT, \
|
||||
.bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \
|
||||
.xpd = PMU_HP_XPD_DEEPSLEEP, \
|
||||
.dbg_atten = PMU_DBG_HP_DEEPSLEEP \
|
||||
} \
|
||||
}, \
|
||||
.lp_sys[PMU_MODE_LP_ACTIVE] = { \
|
||||
.analog = { \
|
||||
.xpd = 1, \
|
||||
.dbias = 0x1a, \
|
||||
.slp_xpd = 0, \
|
||||
.slp_dbias = 0, \
|
||||
.drv_b = 0x7 \
|
||||
} \
|
||||
}, \
|
||||
.lp_sys[PMU_MODE_LP_SLEEP] = { \
|
||||
.analog = { \
|
||||
.drv_b = PMU_LP_DRVB_DEEPSLEEP, \
|
||||
.pd_cur = PMU_PD_CUR_SLEEP_DEFAULT, \
|
||||
.bias_sleep = PMU_BIASSLP_SLEEP_DEFAULT, \
|
||||
.slp_xpd = PMU_LP_SLP_XPD_SLEEP_DEFAULT, \
|
||||
.slp_dbias = PMU_LP_SLP_DBIAS_SLEEP_DEFAULT, \
|
||||
.xpd = PMU_LP_XPD_SLEEP_DEFAULT, \
|
||||
.dbg_atten = PMU_DBG_ATTEN_DEEPSLEEP_DEFAULT, \
|
||||
.dbias = PMU_LP_DBIAS_DEEPSLEEP_0V7 \
|
||||
} \
|
||||
} \
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
pmu_hp_param_t hp_sys;
|
||||
pmu_lp_param_t lp_sys;
|
||||
pmu_hp_lp_param_t hp_lp;
|
||||
} pmu_sleep_param_config_t;
|
||||
|
||||
#define PMU_SLEEP_PARAM_CONFIG_DEFAULT(sleep_flags) { \
|
||||
.hp_sys = { \
|
||||
.min_slp_slow_clk_cycle = PMU_HP_SLEEP_MIN_SLOW_CLK_CYCLES, \
|
||||
.analog_wait_target_cycle = PMU_HP_ANALOG_WAIT_TARGET_CYCLES, \
|
||||
.digital_power_supply_wait_cycle = PMU_HP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES, \
|
||||
.digital_power_up_wait_cycle = PMU_HP_DIGITAL_POWER_UP_WAIT_CYCLES, \
|
||||
.modem_wakeup_wait_cycle = PMU_HP_MODEM_WAKEUP_WAIT_CYCLES, \
|
||||
.pll_stable_wait_cycle = PMU_HP_PLL_STABLE_WAIT_CYCLES \
|
||||
}, \
|
||||
.lp_sys = { \
|
||||
.min_slp_slow_clk_cycle = PMU_LP_SLEEP_MIN_SLOW_CLK_CYCLES, \
|
||||
.analog_wait_target_cycle = PMU_LP_ANALOG_WAIT_TARGET_CYCLES, \
|
||||
.digital_power_supply_wait_cycle = PMU_LP_DIGITAL_POWER_SUPPLY_WAIT_CYCLES, \
|
||||
.digital_power_up_wait_cycle = PMU_LP_DIGITAL_POWER_UP_WAIT_CYCLES \
|
||||
}, \
|
||||
.hp_lp = { \
|
||||
.xtal_stable_wait_slow_clk_cycle = PMU_LP_XTAL_STABLE_WAIT_SLOW_CLK_CYCLES \
|
||||
} \
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
pmu_sleep_power_config_t power;
|
||||
pmu_sleep_digital_config_t digital;
|
||||
pmu_sleep_analog_config_t analog;
|
||||
pmu_sleep_param_config_t param;
|
||||
} pmu_sleep_config_t;
|
||||
|
||||
typedef struct pmu_sleep_machine_constant {
|
||||
struct {
|
||||
uint16_t min_slp_time_us; /* Minimum sleep protection time (unit: microsecond) */
|
||||
uint8_t wakeup_wait_cycle; /* Modem wakeup signal (WiFi MAC and BEACON wakeup) waits for the slow & fast clock domain synchronization and the wakeup signal triggers the PMU FSM switching wait cycle (unit: slow clock cycle) */
|
||||
uint8_t reserved0;
|
||||
uint16_t reserved1;
|
||||
uint16_t analog_wait_time_us; /* LP LDO power up wait time (unit: microsecond) */
|
||||
uint16_t xtal_wait_stable_time_us; /* Main XTAL stabilization wait time (unit: microsecond) */
|
||||
uint8_t clk_switch_cycle; /* Clock switch to FOSC (unit: slow clock cycle) */
|
||||
uint8_t clk_power_on_wait_cycle; /* Clock power on wait cycle (unit: slow clock cycle) */
|
||||
uint8_t isolate_wait_time_us; /* Waiting for all isolate signals to be ready (unit: microsecond) */
|
||||
uint8_t reset_wait_time_us; /* Waiting for all reset signals to be ready (unit: microsecond) */
|
||||
uint16_t power_supply_wait_time_us; /* (unit: microsecond) */
|
||||
uint16_t power_up_wait_time_us; /* (unit: microsecond) */
|
||||
} lp;
|
||||
struct {
|
||||
uint16_t min_slp_time_us; /* Minimum sleep protection time (unit: microsecond) */
|
||||
uint16_t clock_domain_sync_time_us; /* The Slow OSC clock domain synchronizes time with the Fast OSC domain, at least 4 slow clock cycles (unit: microsecond) */
|
||||
uint16_t system_dfs_up_work_time_us; /* System DFS up scaling work time (unit: microsecond) */
|
||||
uint16_t analog_wait_time_us; /* HP LDO power up wait time (unit: microsecond) */
|
||||
uint8_t isolate_wait_time_us; /* Waiting for all isolate signals to be ready (unit: microsecond) */
|
||||
uint8_t reset_wait_time_us; /* Waiting for all reset signals to be ready (unit: microsecond) */
|
||||
uint16_t power_supply_wait_time_us; /* (unit: microsecond) */
|
||||
uint16_t power_up_wait_time_us; /* (unit: microsecond) */
|
||||
uint16_t regdma_s2m_work_time_us; /* Modem Subsystem (S2M switch) REGDMA restore time (unit: microsecond) */
|
||||
uint16_t regdma_s2a_work_time_us; /* SOC System (Digital Peripheral + Modem Subsystem) REGDMA (S2A switch) restore time (unit: microsecond) */
|
||||
uint16_t regdma_m2a_work_time_us; /* Digital Peripheral (M2A switch) REGDMA restore time (unit: microsecond) */
|
||||
uint16_t regdma_a2s_work_time_us; /* SOC System (Digital Peripheral + Modem Subsystem) REGDMA (A2S switch) backup time (unit: microsecond) */
|
||||
uint16_t regdma_rf_on_work_time_us; /* The REGDMA work time of RF enable (unit: microsecond) */
|
||||
uint16_t regdma_rf_off_work_time_us; /* The REGDMA work time of RF disable (unit: microsecond) */
|
||||
uint16_t xtal_wait_stable_time_us; /* Main XTAL stabilization wait time (unit: microsecond) */
|
||||
uint16_t pll_wait_stable_time_us; /* PLL stabilization wait time (unit: microsecond) */
|
||||
} hp;
|
||||
} pmu_sleep_machine_constant_t;
|
||||
|
||||
#define PMU_SLEEP_MC_DEFAULT() { \
|
||||
.lp = { \
|
||||
.min_slp_time_us = 450, \
|
||||
.wakeup_wait_cycle = 4, \
|
||||
.analog_wait_time_us = 154, \
|
||||
.xtal_wait_stable_time_us = 250, \
|
||||
.clk_switch_cycle = 1, \
|
||||
.clk_power_on_wait_cycle = 1, \
|
||||
.isolate_wait_time_us = 1, \
|
||||
.reset_wait_time_us = 1, \
|
||||
.power_supply_wait_time_us = 2, \
|
||||
.power_up_wait_time_us = 2 \
|
||||
}, \
|
||||
.hp = { \
|
||||
.min_slp_time_us = 450, \
|
||||
.clock_domain_sync_time_us = 150, \
|
||||
.system_dfs_up_work_time_us = 124, \
|
||||
.analog_wait_time_us = 154, \
|
||||
.isolate_wait_time_us = 1, \
|
||||
.reset_wait_time_us = 1, \
|
||||
.power_supply_wait_time_us = 2, \
|
||||
.power_up_wait_time_us = 2, \
|
||||
.regdma_s2m_work_time_us = 172, \
|
||||
.regdma_s2a_work_time_us = 685, \
|
||||
.regdma_m2a_work_time_us = 278, \
|
||||
.regdma_a2s_work_time_us = 382, \
|
||||
.regdma_rf_on_work_time_us = 70, \
|
||||
.regdma_rf_off_work_time_us = 23, \
|
||||
.xtal_wait_stable_time_us = 250, \
|
||||
.pll_wait_stable_time_us = 50 \
|
||||
} \
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1525,10 +1525,12 @@ esp_err_t esp_light_sleep_start(void)
|
||||
#endif
|
||||
int sleep_time_hw_adjustment = pmu_sleep_calculate_hw_wait_time(sleep_flags, rtc_clk_slow_src_get(), s_config.rtc_clk_cal_period, s_config.fast_clk_cal_period);
|
||||
s_config.sleep_time_adjustment = sleep_time_sw_adjustment + sleep_time_hw_adjustment;
|
||||
#else
|
||||
const int64_t min_sleep_duration_us = ((pmu_sleep_machine_constant_t *)PMU_instance()->mc)->lp.min_slp_time_us;
|
||||
#else // RTC_CNTL supported
|
||||
uint32_t rtc_cntl_xtl_buf_wait_slp_cycles = rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, s_config.rtc_clk_cal_period);
|
||||
s_config.sleep_time_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US + sleep_time_overhead_in + s_config.sleep_time_overhead_out
|
||||
+ rtc_time_slowclk_to_us(rtc_cntl_xtl_buf_wait_slp_cycles + RTC_CNTL_CK8M_WAIT_SLP_CYCLES + RTC_CNTL_WAKEUP_DELAY_CYCLES, s_config.rtc_clk_cal_period);
|
||||
const int64_t min_sleep_duration_us = rtc_time_slowclk_to_us(RTC_CNTL_MIN_SLP_VAL_MIN, s_config.rtc_clk_cal_period);
|
||||
#endif
|
||||
|
||||
// Decide if VDD_SDIO needs to be powered down;
|
||||
@@ -1553,7 +1555,11 @@ esp_err_t esp_light_sleep_start(void)
|
||||
* min_protect(2);
|
||||
* 4. All the adjustment time which is s_config.sleep_time_adjustment below.
|
||||
*/
|
||||
#if SOC_PMU_SUPPORTED
|
||||
uint32_t rtc_slowclk_us = rtc_time_slowclk_to_us(RTC_MODULE_SLEEP_PREPARE_CYCLES, s_config.rtc_clk_cal_period) + min_sleep_duration_us;
|
||||
#else
|
||||
uint32_t rtc_slowclk_us = rtc_time_slowclk_to_us(RTC_MODULE_SLEEP_PREPARE_CYCLES + RTC_CNTL_MIN_SLP_VAL_MIN, s_config.rtc_clk_cal_period);
|
||||
#endif
|
||||
const uint32_t vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US,
|
||||
flash_enable_time_us + s_config.sleep_time_adjustment + rtc_slowclk_us);
|
||||
|
||||
@@ -1603,7 +1609,6 @@ esp_err_t esp_light_sleep_start(void)
|
||||
|
||||
esp_err_t err = ESP_OK;
|
||||
int64_t final_sleep_duration_us = (int64_t)s_config.sleep_duration - (int64_t)s_config.sleep_time_adjustment;
|
||||
int64_t min_sleep_duration_us = rtc_time_slowclk_to_us(RTC_CNTL_MIN_SLP_VAL_MIN, s_config.rtc_clk_cal_period);
|
||||
|
||||
// reset light sleep wakeup flag before a new light sleep
|
||||
s_light_sleep_wakeup = false;
|
||||
|
||||
@@ -247,7 +247,7 @@ static void start_freq(soc_rtc_slow_clk_src_t required_src, uint32_t start_delay
|
||||
printf("PASS. Time measurement...");
|
||||
}
|
||||
uint32_t fail_measure = 0;
|
||||
#if SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#if !SOC_RTC_TIMER_V1
|
||||
uint64_t clk_rtc_time;
|
||||
for (int j = 0; j < 3; ++j) {
|
||||
clk_rtc_time = esp_clk_rtc_time();
|
||||
@@ -338,7 +338,7 @@ TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[rtc_
|
||||
#endif // !defined(CONFIG_IDF_CI_BUILD) || !CONFIG_SPIRAM_BANKSWITCH_ENABLE
|
||||
#endif // SOC_CLK_XTAL32K_SUPPORTED
|
||||
|
||||
#if SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#if !SOC_RTC_TIMER_V1
|
||||
TEST_CASE("Test rtc clk calibration compensation", "[rtc_clk]")
|
||||
{
|
||||
int64_t t1 = esp_rtc_get_time_us();
|
||||
|
||||
@@ -4,15 +4,19 @@
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef _ROM_RTC_H_
|
||||
#define _ROM_RTC_H_
|
||||
#pragma once
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
#include "esp_assert.h"
|
||||
|
||||
#include "soc/soc.h"
|
||||
#include "soc/lp_system_reg.h"
|
||||
#include "soc/lp_clkrst_reg.h"
|
||||
#include "soc/reset_reasons.h"
|
||||
|
||||
/** \defgroup rtc_apis, rtc registers and memory related apis
|
||||
* @brief rtc apis
|
||||
@@ -44,22 +48,16 @@ extern "C" {
|
||||
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
|
||||
*************************************************************************************
|
||||
*/
|
||||
#define RTC_CNTL_STORE0_REG LP_SYSTEM_REG_LP_STORE0_REG
|
||||
#define RTC_CNTL_STORE1_REG LP_SYSTEM_REG_LP_STORE1_REG
|
||||
#define RTC_CNTL_STORE2_REG LP_SYSTEM_REG_LP_STORE2_REG
|
||||
#define RTC_CNTL_STORE3_REG LP_SYSTEM_REG_LP_STORE3_REG
|
||||
#define RTC_CNTL_STORE4_REG LP_SYSTEM_REG_LP_STORE4_REG
|
||||
#define RTC_CNTL_STORE5_REG LP_SYSTEM_REG_LP_STORE5_REG
|
||||
#define RTC_CNTL_STORE6_REG LP_SYSTEM_REG_LP_STORE6_REG
|
||||
#define RTC_CNTL_STORE7_REG LP_SYSTEM_REG_LP_STORE7_REG
|
||||
#define RTC_CNTL_STORE8_REG LP_SYSTEM_REG_LP_STORE8_REG
|
||||
#define RTC_CNTL_STORE9_REG LP_SYSTEM_REG_LP_STORE9_REG
|
||||
#define RTC_CNTL_STORE10_REG LP_SYSTEM_REG_LP_STORE10_REG
|
||||
#define RTC_CNTL_STORE11_REG LP_SYSTEM_REG_LP_STORE11_REG
|
||||
#define RTC_CNTL_STORE12_REG LP_SYSTEM_REG_LP_STORE12_REG
|
||||
#define RTC_CNTL_STORE13_REG LP_SYSTEM_REG_LP_STORE13_REG
|
||||
#define RTC_CNTL_STORE14_REG LP_SYSTEM_REG_LP_STORE14_REG
|
||||
#define RTC_CNTL_STORE15_REG LP_SYSTEM_REG_LP_STORE15_REG
|
||||
|
||||
#define RTC_SLOW_CLK_CAL_REG LP_SYSTEM_REG_LP_STORE1_REG
|
||||
#define RTC_BOOT_TIME_LOW_REG LP_SYSTEM_REG_LP_STORE2_REG
|
||||
#define RTC_BOOT_TIME_HIGH_REG LP_SYSTEM_REG_LP_STORE3_REG
|
||||
#define RTC_XTAL_FREQ_REG LP_SYSTEM_REG_LP_STORE4_REG
|
||||
#define RTC_ENTRY_LENGTH_REG LP_SYSTEM_REG_LP_STORE5_REG
|
||||
#define RTC_ENTRY_ADDR_REG LP_SYSTEM_REG_LP_STORE6_REG
|
||||
#define RTC_RESET_CAUSE_REG LP_SYSTEM_REG_LP_STORE6_REG
|
||||
#define RTC_MEMORY_CRC_REG LP_SYSTEM_REG_LP_STORE7_REG
|
||||
|
||||
// light sleep
|
||||
/* use LP_SYS_LP_STORE8_REG to store light sleep wake stub addr and sleep mode for dualcore
|
||||
*
|
||||
@@ -71,53 +69,120 @@ extern "C" {
|
||||
/* this MACRO is common to hpcore and lpcore
|
||||
* they use different bitmask to check same value
|
||||
*/
|
||||
#define SLEEP_MODE_LIGHT_SLEEP 0
|
||||
// hpcore use bit0 to check the mode
|
||||
#define SLEEP_MODE_MASK BIT(0)
|
||||
#define RTC_SLEEP_WAKE_STUB_ADDR_REG LP_SYSTEM_REG_LP_STORE8_REG
|
||||
#define RTC_SLEEP_MODE_REG LP_SYSTEM_REG_LP_STORE8_REG
|
||||
|
||||
#define RTC_LIGHT_SLEEP_WAKE_STUB_ADDR_REG RTC_CNTL_STORE8_REG
|
||||
#define RTC_LIGHT_SLEEP_RESTORE_FUNC_ADDR_MASK 0xFFFFFFFC
|
||||
#define SLEEP_MODE_REG RTC_CNTL_STORE8_REG
|
||||
// system
|
||||
#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
|
||||
#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
|
||||
#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
|
||||
#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
|
||||
// deep sleep
|
||||
#define RTC_ENTRY_LENGTH_REG RTC_CNTL_STORE5_REG
|
||||
#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG
|
||||
/* use RTC_ENTRY_ADDR_REG[0] to store if we need do stub crc check
|
||||
* 0: we do not need do crc check, then RTC_MEMORY_CRC_REG and RTC_ENTRY_LENGTH_REG can be freed
|
||||
* 1: we need do crc check
|
||||
*/
|
||||
#define RTC_DEEP_SLEEP_STUB_CHECK_CRC 0x1
|
||||
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
|
||||
#define ROM_LOG_CTRL_REG RTC_XTAL_FREQ_REG
|
||||
#define ROM_LOG_CTRL_REG LP_SYSTEM_REG_LP_STORE4_REG
|
||||
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
|
||||
|
||||
/* Reset reason hint register - same as RTC_ENTRY_ADDR_REG, can be used for both
|
||||
* deep sleep wake stub entry address and reset reason hint, since wake stub
|
||||
* is only used for deep sleep reset.
|
||||
*/
|
||||
#define RTC_RESET_CAUSE_REG RTC_ENTRY_ADDR_REG
|
||||
|
||||
// used to check if app core need hot boot in start.S
|
||||
#define APP_CORE_BOOT_ADDR_REG LP_SYS_BOOT_ADDR_HP_CORE1_REG
|
||||
// used to check if we need do software retention in start.S
|
||||
#define RESET_REASON_REG LP_AONCLKRST_HPCORE0_RESET_CAUSE_REG
|
||||
#define RESET_REASON_MASK LP_AONCLKRST_HPCORE0_RESET_CAUSE
|
||||
#define CORE0_RESET_REASON_POS LP_AONCLKRST_HPCORE0_RESET_CAUSE_S
|
||||
|
||||
#define RESET_REASON1_REG LP_AONCLKRST_HPCORE0_RESET_CAUSE_REG
|
||||
#define RESET_REASON1_MASK LP_AONCLKRST_HPCORE0_RESET_CAUSE
|
||||
#define CORE1_RESET_REASON_POS LP_AONCLKRST_HPCORE1_RESET_CAUSE_S
|
||||
typedef enum {
|
||||
AWAKE = 0, //<CPU ON
|
||||
LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
|
||||
DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
|
||||
} SLEEP_MODE;
|
||||
|
||||
typedef enum {
|
||||
SW_CLR = 0,
|
||||
POWERON_RESET = 1, /**<1, Vbat power on reset*/
|
||||
SW_SYS_RESET = 3, /**<3, Software reset digital core*/
|
||||
PMU_SYS_PWR_DOWN_RESET = 5, /**<5, PMU HP system power down reset*/
|
||||
PMU_CPU_PWR_DOWN_RESET = 6, /**<6, PMU CPU system power down reset*/
|
||||
HP_SYS_HP_WDT0_RESET = 7, /**<7, HP system reset from HP watchdog0*/
|
||||
HP_SYS_HP_WDT1_RESET = 8, /**<8, HP system reset from HP watchdog1*/
|
||||
HP_SYS_LP_WDT_RESET = 9, /**<9, HP system reset from LP watchdog*/
|
||||
HP_CORE_HP_WDT_RESET = 11, /**<11, HP core reset from HP watchdog*/
|
||||
SW_CPU_RESET = 12, /**<12, software reset cpu*/
|
||||
HP_CORE_LP_WDT_RESET = 13, /**<13, HP core reset from LP watchdog*/
|
||||
BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
|
||||
CHIP_LP_WDT_RESET = 16, /**<16, LP watchdog chip reset*/
|
||||
SUPER_WDT_RESET = 18, /**<18, super watchdog reset*/
|
||||
GLITCH_RTC_RESET = 19, /**<19, glitch reset*/
|
||||
EFUSE_CRC_ERR_RESET = 20, /**<20, efuse ecc error reset*/
|
||||
CHIP_USB_JTAG_RESET = 22, /**<22, HP usb jtag chip reset*/
|
||||
CHIP_USB_UART_RESET = 23, /**<23, HP usb uart chip reset*/
|
||||
JTAG_RESET = 24, /**<24, jtag reset*/
|
||||
CPU_LOCKUP_RESET = 26, /**<26, cpu lockup reset*/
|
||||
} RESET_REASON;
|
||||
|
||||
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)SW_SYS_RESET == RESET_REASON_CORE_SW, "SW_SYS_RESET != RESET_REASON_CORE_SW");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)PMU_SYS_PWR_DOWN_RESET == RESET_REASON_CORE_DEEP_SLEEP, "PMU_SYS_PWR_DOWN_RESET != RESET_REASON_CORE_DEEP_SLEEP");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)PMU_SYS_PWR_DOWN_RESET == RESET_REASON_CORE_PMU_PWR_DOWN, "PMU_SYS_PWR_DOWN_RESET != RESET_REASON_CORE_PMU_PWR_DOWN");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)PMU_CPU_PWR_DOWN_RESET == RESET_REASON_CPU_PMU_PWR_DOWN, "PMU_CPU_PWR_DOWN_RESET != RESET_REASON_CPU_PMU_PWR_DOWN");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_SYS_HP_WDT0_RESET == RESET_REASON_CORE_MWDT0, "HP_SYS_HP_WDT0_RESET != RESET_REASON_CORE_MWDT0");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_SYS_HP_WDT1_RESET == RESET_REASON_CORE_MWDT1, "HP_SYS_HP_WDT1_RESET != RESET_REASON_CORE_MWDT1");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_SYS_LP_WDT_RESET == RESET_REASON_CORE_RWDT, "HP_SYS_LP_WDT_RESET != RESET_REASON_CORE_RWDT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_CORE_HP_WDT_RESET == RESET_REASON_CPU_MWDT, "HP_CORE_HP_WDT_RESET != RESET_REASON_CPU_MWDT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)SW_CPU_RESET == RESET_REASON_CPU_SW, "SW_CPU_RESET != RESET_REASON_CPU_SW");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)HP_CORE_LP_WDT_RESET == RESET_REASON_CPU_RWDT, "HP_CORE_LP_WDT_RESET != RESET_REASON_CPU_RWDT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)CHIP_LP_WDT_RESET == RESET_REASON_SYS_RWDT, "CHIP_LP_WDT_RESET != RESET_REASON_SYS_RWDT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_CORE_PWR_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_CORE_PWR_GLITCH");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_CRC_ERR_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_CRC_ERR_RESET != RESET_REASON_CORE_EFUSE_CRC");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)CHIP_USB_JTAG_RESET == RESET_REASON_CORE_USB_JTAG, "CHIP_USB_JTAG_RESET != RESET_REASON_CORE_USB_JTAG");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)CHIP_USB_UART_RESET == RESET_REASON_CORE_USB_UART, "CHIP_USB_UART_RESET != RESET_REASON_CORE_USB_UART");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU_JTAG, "JTAG_RESET != RESET_REASON_CPU_JTAG");
|
||||
ESP_STATIC_ASSERT((soc_reset_reason_t)CPU_LOCKUP_RESET == RESET_REASON_CPU_LOCKUP, "CPU_LOCKUP_RESET != RESET_REASON_CPU_LOCKUP");
|
||||
|
||||
/**
|
||||
* start.S check reset reason and sleep mode register to decide if doing software retention
|
||||
*/
|
||||
#define RESET_REASON_TOP_SLEEP_WAKEUP 5
|
||||
#define RESET_REASON_CPU_SLEEP_WAKEUP 6 // wake up from CPU domain power-down sleep
|
||||
* @brief Get the reset reason for CPU.
|
||||
*
|
||||
* @param int cpu_no : CPU no.
|
||||
*
|
||||
* @return RESET_REASON
|
||||
*/
|
||||
RESET_REASON rtc_get_reset_reason(int cpu_no);
|
||||
|
||||
/**
|
||||
* @brief Suppress ROM log by setting specific RTC control register.
|
||||
* @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void rtc_suppress_rom_log(void)
|
||||
{
|
||||
/* To disable logging in the ROM, only the least significant bit of the register is used,
|
||||
* but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
|
||||
* you need to write to this register in the same format.
|
||||
* Namely, the upper 16 bits and lower should be the same.
|
||||
*/
|
||||
REG_SET_BIT(LP_SYSTEM_REG_LP_STORE4_REG, RTC_DISABLE_ROM_LOG);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Software Reset digital core.
|
||||
*
|
||||
* It is not recommended to use this function in esp-idf, use
|
||||
* esp_restart() instead.
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void software_reset(void);
|
||||
|
||||
/**
|
||||
* @brief Software Reset digital core.
|
||||
*
|
||||
* It is not recommended to use this function in esp-idf, use
|
||||
* esp_restart() instead.
|
||||
*
|
||||
* @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
void software_reset_cpu(int cpu_no);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _ROM_RTC_H_ */
|
||||
|
||||
@@ -33,6 +33,7 @@
|
||||
#include "esp_private/esp_sleep_internal.h"
|
||||
#include "esp_private/periph_ctrl.h"
|
||||
#include "esp_private/esp_clk.h"
|
||||
#include "esp_private/esp_pmu.h"
|
||||
#include "esp_rom_serial_output.h"
|
||||
#include "esp_rom_sys.h"
|
||||
|
||||
|
||||
@@ -0,0 +1,19 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "hal/lp_sys_ll.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define lp_aon_hal_inform_wakeup_type(dslp) lp_sys_ll_inform_wakeup_type(dslp)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,66 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The LL layer for ESP32-S31 LP_SYS register operations
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "esp_attr.h"
|
||||
#include "soc/soc.h"
|
||||
#include "soc/lp_system_struct.h"
|
||||
#include "hal/misc.h"
|
||||
#include "esp32s31/rom/rtc.h"
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief ROM obtains the wake-up type through LP_SYS_STORE9_REG[0].
|
||||
* Set the flag to inform
|
||||
* @param true: deepsleep false: lightsleep
|
||||
*/
|
||||
FORCE_INLINE_ATTR void lp_sys_ll_inform_wakeup_type(bool dslp)
|
||||
{
|
||||
if (dslp) {
|
||||
REG_SET_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run deep sleep wake stub */
|
||||
|
||||
} else {
|
||||
REG_CLR_BIT(RTC_SLEEP_MODE_REG, BIT(0)); /* Tell rom to run light sleep wake stub */
|
||||
}
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void lp_sys_ll_set_pau_aon_bypass(bool bypass)
|
||||
{
|
||||
LP_SYS.backup_dma_cfg1.aon_bypass = bypass ? 1 : 0;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_tout_thres(uint32_t tout)
|
||||
{
|
||||
LP_SYS.backup_dma_cfg1.link_wait_tout_thres_aon = tout;
|
||||
LP_SYS.backup_dma_cfg1.link_work_tout_thres_aon = tout;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_backup_tout_thres(uint32_t tout)
|
||||
{
|
||||
LP_SYS.backup_dma_cfg0.link_backup_tout_thres_aon = tout;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void lp_sys_ll_set_pau_reg_read_interval(uint32_t val)
|
||||
{
|
||||
LP_SYS.backup_dma_cfg0.read_interval_aon = val;
|
||||
}
|
||||
|
||||
FORCE_INLINE_ATTR void lp_sys_ll_set_pau_link_addr(uint32_t addr)
|
||||
{
|
||||
LP_SYS.backup_dma_cfg2.link_addr_aon = addr;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,49 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
// The HAL layer for PMU
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc_caps.h"
|
||||
#include "hal/pmu_ll.h"
|
||||
#include "hal/pmu_types.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
pmu_dev_t *dev;
|
||||
} pmu_hal_context_t;
|
||||
|
||||
void pmu_hal_hp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_hp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_lp_set_digital_power_up_wait_cycle(pmu_hal_context_t *hal, uint32_t power_supply_wait_cycle, uint32_t power_up_wait_cycle);
|
||||
|
||||
uint32_t pmu_hal_lp_get_digital_power_up_wait_cycle(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle);
|
||||
|
||||
void pmu_hal_lp_set_control_ready_wait_cycle(pmu_hal_context_t *hal, uint32_t isolate_wait_cycle, uint32_t reset_wait_cycle);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_active_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_sleep_modem_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_enable(pmu_hal_context_t *hal);
|
||||
|
||||
void pmu_hal_hp_set_modem_active_backup_disable(pmu_hal_context_t *hal);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -83,7 +83,7 @@ config SOC_RTC_MEM_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTC_TIMER_V1_SUPPORTED
|
||||
config SOC_RTC_TIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -519,6 +519,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_RTC_TIMER_V1
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TOUCH_SENSOR_VERSION
|
||||
int
|
||||
default 1
|
||||
|
||||
@@ -86,7 +86,7 @@
|
||||
#define SOC_RTC_FAST_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_V1_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_SUPPORTED 1
|
||||
#define SOC_I2S_SUPPORTED 1
|
||||
#define SOC_I2S_I80_LCD_SUPPORTED 1
|
||||
#define SOC_LCD_I80_SUPPORTED 1
|
||||
@@ -262,7 +262,7 @@
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V1_SUPPORTED
|
||||
#define SOC_RTC_TIMER_V1 1
|
||||
|
||||
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
|
||||
#define SOC_TOUCH_SENSOR_VERSION (1U) /*!<Hardware version of touch sensor */
|
||||
|
||||
@@ -99,7 +99,7 @@ config SOC_BOD_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTC_TIMER_V1_SUPPORTED
|
||||
config SOC_RTC_TIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -487,6 +487,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_RTC_TIMER_V1
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MWDT_SUPPORT_XTAL
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -47,7 +47,7 @@
|
||||
#define SOC_SECURE_BOOT_SUPPORTED 1
|
||||
#define SOC_SYSTIMER_SUPPORTED 1
|
||||
#define SOC_BOD_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_V1_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_SUPPORTED 1
|
||||
#define SOC_CLK_TREE_SUPPORTED 1
|
||||
#define SOC_ASSIST_DEBUG_SUPPORTED 1
|
||||
#define SOC_WDT_SUPPORTED 1
|
||||
@@ -229,7 +229,7 @@
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V1_SUPPORTED
|
||||
#define SOC_RTC_TIMER_V1 1
|
||||
|
||||
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
|
||||
#define SOC_MWDT_SUPPORT_XTAL (1)
|
||||
|
||||
@@ -87,7 +87,7 @@ config SOC_RTC_MEM_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTC_TIMER_V1_SUPPORTED
|
||||
config SOC_RTC_TIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -675,6 +675,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_RTC_TIMER_V1
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_MWDT_SUPPORT_XTAL
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -44,7 +44,7 @@
|
||||
#define SOC_EFUSE_SUPPORTED 1
|
||||
#define SOC_RTC_FAST_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_V1_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_SUPPORTED 1
|
||||
#define SOC_I2S_SUPPORTED 1
|
||||
#define SOC_RMT_SUPPORTED 1
|
||||
#define SOC_SDM_SUPPORTED 1
|
||||
@@ -305,7 +305,7 @@
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V1_SUPPORTED
|
||||
#define SOC_RTC_TIMER_V1 1
|
||||
|
||||
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
|
||||
#define SOC_MWDT_SUPPORT_XTAL (1)
|
||||
|
||||
@@ -203,7 +203,7 @@ config SOC_PAU_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTC_TIMER_V2_SUPPORTED
|
||||
config SOC_RTC_TIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -1047,6 +1047,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_RTC_TIMER_V2
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TIMER_SUPPORT_ETM
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -73,7 +73,7 @@
|
||||
#define SOC_PMU_SUPPORTED 1
|
||||
#define SOC_PMU_PVT_SUPPORTED 1
|
||||
#define SOC_PAU_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_V2_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_SUPPORTED 1
|
||||
#define SOC_LP_AON_SUPPORTED 1
|
||||
#define SOC_LP_PERIPHERALS_SUPPORTED 1
|
||||
#define SOC_LP_I2C_SUPPORTED 1
|
||||
@@ -432,7 +432,7 @@
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#define SOC_RTC_TIMER_V2 1
|
||||
|
||||
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
|
||||
#define SOC_TIMER_SUPPORT_ETM (1)
|
||||
|
||||
@@ -195,7 +195,7 @@ config SOC_PAU_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTC_TIMER_V2_SUPPORTED
|
||||
config SOC_RTC_TIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -875,6 +875,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_RTC_TIMER_V2
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TIMER_SUPPORT_ETM
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -71,7 +71,7 @@
|
||||
#define SOC_PMU_SUPPORTED 1
|
||||
#define SOC_PMU_PVT_SUPPORTED 1
|
||||
#define SOC_PAU_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_V2_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_SUPPORTED 1
|
||||
#define SOC_LP_AON_SUPPORTED 1
|
||||
#define SOC_LP_PERIPHERALS_SUPPORTED 1
|
||||
#define SOC_LP_I2C_SUPPORTED 1
|
||||
@@ -371,7 +371,7 @@
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#define SOC_RTC_TIMER_V2 1
|
||||
|
||||
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
|
||||
#define SOC_TIMER_SUPPORT_ETM (1)
|
||||
|
||||
@@ -123,7 +123,7 @@ config SOC_PMU_PVT_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTC_TIMER_V2_SUPPORTED
|
||||
config SOC_RTC_TIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -807,6 +807,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_RTC_TIMER_V2
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TIMER_SUPPORT_SLEEP_RETENTION
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -54,7 +54,7 @@
|
||||
#define SOC_APM_SUPPORTED 1 /*!< Support for APM peripheral */
|
||||
#define SOC_PMU_SUPPORTED 1
|
||||
#define SOC_PMU_PVT_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_V2_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_SUPPORTED 1
|
||||
#define SOC_LP_AON_SUPPORTED 1
|
||||
#define SOC_CLK_TREE_SUPPORTED 1
|
||||
#define SOC_ASSIST_DEBUG_SUPPORTED 1
|
||||
@@ -339,7 +339,7 @@
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#define SOC_RTC_TIMER_V2 1
|
||||
|
||||
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
|
||||
#define SOC_TIMER_SUPPORT_SLEEP_RETENTION (1)
|
||||
|
||||
@@ -199,7 +199,7 @@ config SOC_PMU_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTC_TIMER_V2_SUPPORTED
|
||||
config SOC_RTC_TIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -879,6 +879,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_RTC_TIMER_V2
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TIMER_SUPPORT_ETM
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -88,7 +88,7 @@
|
||||
#define SOC_VBAT_SUPPORTED 1
|
||||
#define SOC_APM_SUPPORTED 1 /*!< Support for APM peripheral */
|
||||
#define SOC_PMU_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_V2_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_SUPPORTED 1
|
||||
#define SOC_LP_AON_SUPPORTED 1
|
||||
#define SOC_PAU_SUPPORTED 1
|
||||
#define SOC_CLK_TREE_SUPPORTED 1
|
||||
@@ -389,7 +389,7 @@
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#define SOC_RTC_TIMER_V2 1
|
||||
|
||||
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
|
||||
#define SOC_TIMER_SUPPORT_ETM (1)
|
||||
|
||||
@@ -111,7 +111,7 @@ config SOC_PMU_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTC_TIMER_V2_SUPPORTED
|
||||
config SOC_RTC_TIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -703,6 +703,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_RTC_TIMER_V2
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TIMER_SUPPORT_ETM
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -61,7 +61,7 @@
|
||||
// #define SOC_BOD_SUPPORTED 1 //TODO: [ESP32H21] IDF-11530
|
||||
// #define SOC_APM_SUPPORTED 1 //TODO: [ESP32H21] IDF-11494
|
||||
#define SOC_PMU_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_V2_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_SUPPORTED 1
|
||||
#define SOC_LP_AON_SUPPORTED 1
|
||||
// #define SOC_LP_PERIPHERALS_SUPPORTED 1
|
||||
#define SOC_CLK_TREE_SUPPORTED 1
|
||||
@@ -366,7 +366,7 @@
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#define SOC_RTC_TIMER_V2 1
|
||||
|
||||
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
|
||||
#define SOC_TIMER_SUPPORT_ETM (1)
|
||||
|
||||
@@ -139,7 +139,7 @@ config SOC_PAU_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTC_TIMER_V2_SUPPORTED
|
||||
config SOC_RTC_TIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -779,6 +779,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_RTC_TIMER_V2
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TIMER_SUPPORT_ETM
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -77,7 +77,7 @@
|
||||
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12256
|
||||
#define SOC_PMU_SUPPORTED 1 // TODO: [ESP32H4] IDF-12286
|
||||
#define SOC_PAU_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_V2_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_SUPPORTED 1
|
||||
#define SOC_LP_AON_SUPPORTED 1
|
||||
#define SOC_TOUCH_SENSOR_SUPPORTED 1
|
||||
// #define SOC_LP_PERIPHERALS_SUPPORTED 1
|
||||
@@ -388,7 +388,7 @@
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#define SOC_RTC_TIMER_V2 1
|
||||
|
||||
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
|
||||
#define SOC_TIMER_SUPPORT_ETM (1)
|
||||
|
||||
@@ -267,7 +267,7 @@ config SOC_PAU_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTC_TIMER_V2_SUPPORTED
|
||||
config SOC_RTC_TIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -1427,6 +1427,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_RTC_TIMER_V2
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TIMER_SUPPORT_ETM
|
||||
bool
|
||||
default y
|
||||
@@ -1699,10 +1703,6 @@ config SOC_PM_EXT1_WAKEUP_BY_PMU
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_WIFI_WAKEUP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -89,7 +89,7 @@
|
||||
#define SOC_PVT_RETENTION_BY_REGDMA 1
|
||||
#define SOC_DCDC_SUPPORTED 1
|
||||
#define SOC_PAU_SUPPORTED 1 //TODO: IDF-7531
|
||||
#define SOC_RTC_TIMER_V2_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_SUPPORTED 1
|
||||
#define SOC_ULP_LP_UART_SUPPORTED 1
|
||||
#define SOC_LP_GPIO_MATRIX_SUPPORTED 1
|
||||
#define SOC_LP_PERIPHERALS_SUPPORTED 1
|
||||
@@ -547,7 +547,7 @@
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#define SOC_RTC_TIMER_V2 1
|
||||
|
||||
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
|
||||
#define SOC_TIMER_SUPPORT_ETM 1
|
||||
@@ -653,7 +653,6 @@
|
||||
#define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
|
||||
#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
|
||||
#define SOC_PM_EXT1_WAKEUP_BY_PMU (1)
|
||||
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
|
||||
#define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP (1) /*!<Supports waking up from touch pad trigger */
|
||||
#define SOC_PM_SUPPORT_LP_UART_WAKEUP (1)
|
||||
#define SOC_PM_SUPPORT_CPU_PD (1)
|
||||
|
||||
@@ -99,7 +99,7 @@ config SOC_RTC_MEM_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTC_TIMER_V1_SUPPORTED
|
||||
config SOC_RTC_TIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -587,6 +587,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_RTC_TIMER_V1
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TOUCH_SENSOR_VERSION
|
||||
int
|
||||
default 2
|
||||
|
||||
@@ -67,7 +67,7 @@
|
||||
#define SOC_RTC_FAST_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_V1_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_SUPPORTED 1
|
||||
#define SOC_PSRAM_DMA_CAPABLE 1
|
||||
#define SOC_XT_WDT_SUPPORTED 1
|
||||
#define SOC_I2S_SUPPORTED 1
|
||||
@@ -275,7 +275,7 @@
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V1_SUPPORTED
|
||||
#define SOC_RTC_TIMER_V1 1
|
||||
|
||||
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
|
||||
#define SOC_TOUCH_SENSOR_VERSION (2) /*!< Hardware version of touch sensor */
|
||||
|
||||
@@ -135,7 +135,7 @@ config SOC_RTC_MEM_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTC_TIMER_V1_SUPPORTED
|
||||
config SOC_RTC_TIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -699,6 +699,10 @@ config SOC_LP_TIMER_BIT_WIDTH_HI
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_RTC_TIMER_V1
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_TOUCH_SENSOR_VERSION
|
||||
int
|
||||
default 2
|
||||
|
||||
@@ -61,7 +61,7 @@
|
||||
#define SOC_RTC_FAST_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_SLOW_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_MEM_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_V1_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_SUPPORTED 1
|
||||
#define SOC_PSRAM_DMA_CAPABLE 1
|
||||
#define SOC_XT_WDT_SUPPORTED 1
|
||||
#define SOC_I2S_SUPPORTED 1
|
||||
@@ -296,7 +296,7 @@
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
#define SOC_RTC_TIMER_SUPPORTED SOC_RTC_TIMER_V1_SUPPORTED
|
||||
#define SOC_RTC_TIMER_V1 1
|
||||
|
||||
/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
|
||||
#define SOC_TOUCH_SENSOR_VERSION (2) /*!< Hardware version of touch sensor */
|
||||
|
||||
@@ -51,6 +51,14 @@ config SOC_SYSTIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PMU_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_RTC_TIMER_SUPPORTED
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PSRAM_DMA_CAPABLE
|
||||
bool
|
||||
default y
|
||||
@@ -410,3 +418,115 @@ config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
|
||||
config SOC_RCC_IS_INDEPENDENT
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_EXT1_WAKEUP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_EXT1_WAKEUP_BY_PMU
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_WIFI_WAKEUP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_BEACON_WAKEUP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_XTAL32K_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_RC32K_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_RC_FAST_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_VDDSDIO_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_TOP_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_HP_AON_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_CNNT_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_RTC_PERIPH_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_MODEM_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_MAC_BB_PD
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_CPU_RETENTION_BY_SW
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_CACHE_RETENTION_BY_PAU
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_PAU_LINK_NUM
|
||||
int
|
||||
default 5
|
||||
|
||||
config SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
|
||||
int
|
||||
default 4
|
||||
|
||||
config SOC_PM_MODEM_RETENTION_BY_REGDMA
|
||||
bool
|
||||
default y
|
||||
|
||||
config SOC_PM_RETENTION_MODULE_NUM
|
||||
int
|
||||
default 64
|
||||
|
||||
config SOC_LP_TIMER_BIT_WIDTH_LO
|
||||
int
|
||||
default 32
|
||||
|
||||
config SOC_LP_TIMER_BIT_WIDTH_HI
|
||||
int
|
||||
default 16
|
||||
|
||||
config SOC_RTC_TIMER_V3
|
||||
bool
|
||||
default y
|
||||
|
||||
@@ -72,8 +72,9 @@
|
||||
// #define SOC_SECURE_BOOT_SUPPORTED 1 // TODO: [ESP32S31] IDF-14629
|
||||
// #define SOC_BOD_SUPPORTED 1 // TODO: [ESP32S31] IDF-14658
|
||||
// #define SOC_APM_SUPPORTED 1 // TODO: [ESP32S31] IDF-14620
|
||||
// #define SOC_PMU_SUPPORTED 1 // TODO: [ESP32S31] IDF-14642
|
||||
// #define SOC_RTC_TIMER_V2_SUPPORTED 1 // TODO: [ESP32S31] IDF-14638
|
||||
// #define SOC_PAU_SUPPORTED 1 // TODO: [ESP32S31] IDF-14582
|
||||
#define SOC_PMU_SUPPORTED 1
|
||||
#define SOC_RTC_TIMER_SUPPORTED 1
|
||||
// #define SOC_ULP_LP_UART_SUPPORTED 1 // TODO: [ESP32S31] IDF-14634
|
||||
// #define SOC_LP_GPIO_MATRIX_SUPPORTED 1 // TODO: [ESP32S31] IDF-14785
|
||||
// #define SOC_LP_PERIPHERALS_SUPPORTED 1 // TODO: [ESP32S31] IDF-14785
|
||||
@@ -284,3 +285,42 @@
|
||||
#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (1) /*!< Any regi2c operation needs enable the analog i2c master clock first */
|
||||
|
||||
#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control has own registers for each module */
|
||||
|
||||
/*-------------------------- Power Management CAPS ----------------------------*/
|
||||
#define SOC_PM_SUPPORT_EXT1_WAKEUP (1)
|
||||
#define SOC_PM_SUPPORT_EXT1_WAKEUP_MODE_PER_PIN (1) /*!<Supports one bit per pin to configure the EXT1 trigger level */
|
||||
#define SOC_PM_EXT1_WAKEUP_BY_PMU (1)
|
||||
#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
|
||||
#define SOC_PM_SUPPORT_BEACON_WAKEUP (1)
|
||||
#define SOC_PM_SUPPORT_TOUCH_SENSOR_WAKEUP (1) /*!<Supports waking up from touch pad trigger */
|
||||
// #define SOC_PM_SUPPORT_CPU_PD (1) // TODO: [ESP32S31] IDF-14647
|
||||
#define SOC_PM_SUPPORT_XTAL32K_PD (1)
|
||||
#define SOC_PM_SUPPORT_RC32K_PD (1)
|
||||
#define SOC_PM_SUPPORT_RC_FAST_PD (1)
|
||||
#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
|
||||
#define SOC_PM_SUPPORT_TOP_PD (1)
|
||||
#define SOC_PM_SUPPORT_HP_AON_PD (1)
|
||||
#define SOC_PM_SUPPORT_CNNT_PD (1)
|
||||
#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
|
||||
#define SOC_PM_SUPPORT_MODEM_PD (1) /*!<modem includes BLE and 15.4 and wifi*/
|
||||
#define SOC_PM_SUPPORT_MAC_BB_PD (1)
|
||||
|
||||
#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
|
||||
|
||||
#define SOC_PM_CPU_RETENTION_BY_SW (1)
|
||||
#define SOC_PM_CACHE_RETENTION_BY_PAU (1)
|
||||
#define SOC_EXT_MEM_CACHE_TAG_IN_CPU_DOMAIN (1)
|
||||
|
||||
#define SOC_PM_PAU_LINK_NUM (5)
|
||||
#define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1)
|
||||
#define SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC (4) // The range of values for the link index is [0, SOC_PM_PAU_LINK_NUM)
|
||||
|
||||
#define SOC_PM_MODEM_RETENTION_BY_REGDMA (1)
|
||||
// #define SOC_PM_SUPPORT_PMU_MODEM_STATE (1) // TODO: [ESP32S31] IDF-14582
|
||||
|
||||
#define SOC_PM_RETENTION_MODULE_NUM (64)
|
||||
|
||||
/*-------------------------- LP_TIMER CAPS ----------------------------------*/
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_LO 32 // Bit width of lp_timer low part
|
||||
#define SOC_LP_TIMER_BIT_WIDTH_HI 16 // Bit width of lp_timer high part
|
||||
#define SOC_RTC_TIMER_V3 1
|
||||
|
||||
@@ -93,8 +93,8 @@ PROVIDE ( LP_IO_MUX = 0x20712000 );
|
||||
PROVIDE ( LP_GPIO = 0x20713000 );
|
||||
PROVIDE ( LP_INTR = 0x20714000 );
|
||||
PROVIDE ( EFUSE = 0x20715000 );
|
||||
PROVIDE ( LP_TIMER = 0x20800000 );
|
||||
PROVIDE ( LP_WDT = 0x20801000 );
|
||||
PROVIDE ( RTC_TIMER = 0x20800000 );
|
||||
PROVIDE ( RTC_WDT = 0x20801000 );
|
||||
PROVIDE ( LP_CLOCK_CALI0 = 0x20802000 );
|
||||
PROVIDE ( LP_CLOCK_CALI1 = 0x20803000 );
|
||||
PROVIDE ( LP_PWR_REG = 0x20804000 );
|
||||
|
||||
@@ -1,336 +0,0 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** LP_WDT_CONFIG0_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_CONFIG0_REG (DR_REG_LP_WDT_BASE + 0x0)
|
||||
/** LP_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_PAUSE_IN_SLP (BIT(9))
|
||||
#define LP_WDT_WDT_PAUSE_IN_SLP_M (LP_WDT_WDT_PAUSE_IN_SLP_V << LP_WDT_WDT_PAUSE_IN_SLP_S)
|
||||
#define LP_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U
|
||||
#define LP_WDT_WDT_PAUSE_IN_SLP_S 9
|
||||
/** LP_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_APPCPU_RESET_EN (BIT(10))
|
||||
#define LP_WDT_WDT_APPCPU_RESET_EN_M (LP_WDT_WDT_APPCPU_RESET_EN_V << LP_WDT_WDT_APPCPU_RESET_EN_S)
|
||||
#define LP_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U
|
||||
#define LP_WDT_WDT_APPCPU_RESET_EN_S 10
|
||||
/** LP_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_PROCPU_RESET_EN (BIT(11))
|
||||
#define LP_WDT_WDT_PROCPU_RESET_EN_M (LP_WDT_WDT_PROCPU_RESET_EN_V << LP_WDT_WDT_PROCPU_RESET_EN_S)
|
||||
#define LP_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U
|
||||
#define LP_WDT_WDT_PROCPU_RESET_EN_S 11
|
||||
/** LP_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12))
|
||||
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_M (LP_WDT_WDT_FLASHBOOT_MOD_EN_V << LP_WDT_WDT_FLASHBOOT_MOD_EN_S)
|
||||
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
|
||||
#define LP_WDT_WDT_FLASHBOOT_MOD_EN_S 12
|
||||
/** LP_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_SYS_RESET_LENGTH 0x00000007U
|
||||
#define LP_WDT_WDT_SYS_RESET_LENGTH_M (LP_WDT_WDT_SYS_RESET_LENGTH_V << LP_WDT_WDT_SYS_RESET_LENGTH_S)
|
||||
#define LP_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U
|
||||
#define LP_WDT_WDT_SYS_RESET_LENGTH_S 13
|
||||
/** LP_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_CPU_RESET_LENGTH 0x00000007U
|
||||
#define LP_WDT_WDT_CPU_RESET_LENGTH_M (LP_WDT_WDT_CPU_RESET_LENGTH_V << LP_WDT_WDT_CPU_RESET_LENGTH_S)
|
||||
#define LP_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U
|
||||
#define LP_WDT_WDT_CPU_RESET_LENGTH_S 16
|
||||
/** LP_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG3 0x00000007U
|
||||
#define LP_WDT_WDT_STG3_M (LP_WDT_WDT_STG3_V << LP_WDT_WDT_STG3_S)
|
||||
#define LP_WDT_WDT_STG3_V 0x00000007U
|
||||
#define LP_WDT_WDT_STG3_S 19
|
||||
/** LP_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG2 0x00000007U
|
||||
#define LP_WDT_WDT_STG2_M (LP_WDT_WDT_STG2_V << LP_WDT_WDT_STG2_S)
|
||||
#define LP_WDT_WDT_STG2_V 0x00000007U
|
||||
#define LP_WDT_WDT_STG2_S 22
|
||||
/** LP_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG1 0x00000007U
|
||||
#define LP_WDT_WDT_STG1_M (LP_WDT_WDT_STG1_V << LP_WDT_WDT_STG1_S)
|
||||
#define LP_WDT_WDT_STG1_V 0x00000007U
|
||||
#define LP_WDT_WDT_STG1_S 25
|
||||
/** LP_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG0 0x00000007U
|
||||
#define LP_WDT_WDT_STG0_M (LP_WDT_WDT_STG0_V << LP_WDT_WDT_STG0_S)
|
||||
#define LP_WDT_WDT_STG0_V 0x00000007U
|
||||
#define LP_WDT_WDT_STG0_S 28
|
||||
/** LP_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_EN (BIT(31))
|
||||
#define LP_WDT_WDT_EN_M (LP_WDT_WDT_EN_V << LP_WDT_WDT_EN_S)
|
||||
#define LP_WDT_WDT_EN_V 0x00000001U
|
||||
#define LP_WDT_WDT_EN_S 31
|
||||
|
||||
/** LP_WDT_CONFIG1_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_CONFIG1_REG (DR_REG_LP_WDT_BASE + 0x4)
|
||||
/** LP_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG0_HOLD 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG0_HOLD_M (LP_WDT_WDT_STG0_HOLD_V << LP_WDT_WDT_STG0_HOLD_S)
|
||||
#define LP_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG0_HOLD_S 0
|
||||
|
||||
/** LP_WDT_CONFIG2_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_CONFIG2_REG (DR_REG_LP_WDT_BASE + 0x8)
|
||||
/** LP_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG1_HOLD 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG1_HOLD_M (LP_WDT_WDT_STG1_HOLD_V << LP_WDT_WDT_STG1_HOLD_S)
|
||||
#define LP_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG1_HOLD_S 0
|
||||
|
||||
/** LP_WDT_CONFIG3_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_CONFIG3_REG (DR_REG_LP_WDT_BASE + 0xc)
|
||||
/** LP_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG2_HOLD 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG2_HOLD_M (LP_WDT_WDT_STG2_HOLD_V << LP_WDT_WDT_STG2_HOLD_S)
|
||||
#define LP_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG2_HOLD_S 0
|
||||
|
||||
/** LP_WDT_CONFIG4_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_CONFIG4_REG (DR_REG_LP_WDT_BASE + 0x10)
|
||||
/** LP_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_STG3_HOLD 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG3_HOLD_M (LP_WDT_WDT_STG3_HOLD_V << LP_WDT_WDT_STG3_HOLD_S)
|
||||
#define LP_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_STG3_HOLD_S 0
|
||||
|
||||
/** LP_WDT_FEED_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_FEED_REG (DR_REG_LP_WDT_BASE + 0x14)
|
||||
/** LP_WDT_FEED : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_FEED (BIT(31))
|
||||
#define LP_WDT_FEED_M (LP_WDT_FEED_V << LP_WDT_FEED_S)
|
||||
#define LP_WDT_FEED_V 0x00000001U
|
||||
#define LP_WDT_FEED_S 31
|
||||
|
||||
/** LP_WDT_WPROTECT_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x18)
|
||||
/** LP_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_WDT_WKEY 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_WKEY_M (LP_WDT_WDT_WKEY_V << LP_WDT_WDT_WKEY_S)
|
||||
#define LP_WDT_WDT_WKEY_V 0xFFFFFFFFU
|
||||
#define LP_WDT_WDT_WKEY_S 0
|
||||
|
||||
/** LP_WDT_SWD_CONFIG_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_CONFIG_REG (DR_REG_LP_WDT_BASE + 0x1c)
|
||||
/** LP_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_RESET_FLAG (BIT(0))
|
||||
#define LP_WDT_SWD_RESET_FLAG_M (LP_WDT_SWD_RESET_FLAG_V << LP_WDT_SWD_RESET_FLAG_S)
|
||||
#define LP_WDT_SWD_RESET_FLAG_V 0x00000001U
|
||||
#define LP_WDT_SWD_RESET_FLAG_S 0
|
||||
/** LP_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN (BIT(18))
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN_M (LP_WDT_SWD_AUTO_FEED_EN_V << LP_WDT_SWD_AUTO_FEED_EN_S)
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN_V 0x00000001U
|
||||
#define LP_WDT_SWD_AUTO_FEED_EN_S 18
|
||||
/** LP_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR (BIT(19))
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR_M (LP_WDT_SWD_RST_FLAG_CLR_V << LP_WDT_SWD_RST_FLAG_CLR_S)
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR_V 0x00000001U
|
||||
#define LP_WDT_SWD_RST_FLAG_CLR_S 19
|
||||
/** LP_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH 0x000003FFU
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH_M (LP_WDT_SWD_SIGNAL_WIDTH_V << LP_WDT_SWD_SIGNAL_WIDTH_S)
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU
|
||||
#define LP_WDT_SWD_SIGNAL_WIDTH_S 20
|
||||
/** LP_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_DISABLE (BIT(30))
|
||||
#define LP_WDT_SWD_DISABLE_M (LP_WDT_SWD_DISABLE_V << LP_WDT_SWD_DISABLE_S)
|
||||
#define LP_WDT_SWD_DISABLE_V 0x00000001U
|
||||
#define LP_WDT_SWD_DISABLE_S 30
|
||||
/** LP_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_FEED (BIT(31))
|
||||
#define LP_WDT_SWD_FEED_M (LP_WDT_SWD_FEED_V << LP_WDT_SWD_FEED_S)
|
||||
#define LP_WDT_SWD_FEED_V 0x00000001U
|
||||
#define LP_WDT_SWD_FEED_S 31
|
||||
|
||||
/** LP_WDT_SWD_WPROTECT_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_WPROTECT_REG (DR_REG_LP_WDT_BASE + 0x20)
|
||||
/** LP_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SWD_WKEY 0xFFFFFFFFU
|
||||
#define LP_WDT_SWD_WKEY_M (LP_WDT_SWD_WKEY_V << LP_WDT_SWD_WKEY_S)
|
||||
#define LP_WDT_SWD_WKEY_V 0xFFFFFFFFU
|
||||
#define LP_WDT_SWD_WKEY_S 0
|
||||
|
||||
/** LP_WDT_INT_RAW_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_INT_RAW_REG (DR_REG_LP_WDT_BASE + 0x24)
|
||||
/** LP_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SUPER_WDT_INT_RAW (BIT(30))
|
||||
#define LP_WDT_SUPER_WDT_INT_RAW_M (LP_WDT_SUPER_WDT_INT_RAW_V << LP_WDT_SUPER_WDT_INT_RAW_S)
|
||||
#define LP_WDT_SUPER_WDT_INT_RAW_V 0x00000001U
|
||||
#define LP_WDT_SUPER_WDT_INT_RAW_S 30
|
||||
/** LP_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_LP_WDT_INT_RAW (BIT(31))
|
||||
#define LP_WDT_LP_WDT_INT_RAW_M (LP_WDT_LP_WDT_INT_RAW_V << LP_WDT_LP_WDT_INT_RAW_S)
|
||||
#define LP_WDT_LP_WDT_INT_RAW_V 0x00000001U
|
||||
#define LP_WDT_LP_WDT_INT_RAW_S 31
|
||||
|
||||
/** LP_WDT_INT_ST_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_INT_ST_REG (DR_REG_LP_WDT_BASE + 0x28)
|
||||
/** LP_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SUPER_WDT_INT_ST (BIT(30))
|
||||
#define LP_WDT_SUPER_WDT_INT_ST_M (LP_WDT_SUPER_WDT_INT_ST_V << LP_WDT_SUPER_WDT_INT_ST_S)
|
||||
#define LP_WDT_SUPER_WDT_INT_ST_V 0x00000001U
|
||||
#define LP_WDT_SUPER_WDT_INT_ST_S 30
|
||||
/** LP_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_LP_WDT_INT_ST (BIT(31))
|
||||
#define LP_WDT_LP_WDT_INT_ST_M (LP_WDT_LP_WDT_INT_ST_V << LP_WDT_LP_WDT_INT_ST_S)
|
||||
#define LP_WDT_LP_WDT_INT_ST_V 0x00000001U
|
||||
#define LP_WDT_LP_WDT_INT_ST_S 31
|
||||
|
||||
/** LP_WDT_INT_ENA_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_INT_ENA_REG (DR_REG_LP_WDT_BASE + 0x2c)
|
||||
/** LP_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SUPER_WDT_INT_ENA (BIT(30))
|
||||
#define LP_WDT_SUPER_WDT_INT_ENA_M (LP_WDT_SUPER_WDT_INT_ENA_V << LP_WDT_SUPER_WDT_INT_ENA_S)
|
||||
#define LP_WDT_SUPER_WDT_INT_ENA_V 0x00000001U
|
||||
#define LP_WDT_SUPER_WDT_INT_ENA_S 30
|
||||
/** LP_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_LP_WDT_INT_ENA (BIT(31))
|
||||
#define LP_WDT_LP_WDT_INT_ENA_M (LP_WDT_LP_WDT_INT_ENA_V << LP_WDT_LP_WDT_INT_ENA_S)
|
||||
#define LP_WDT_LP_WDT_INT_ENA_V 0x00000001U
|
||||
#define LP_WDT_LP_WDT_INT_ENA_S 31
|
||||
|
||||
/** LP_WDT_INT_CLR_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_INT_CLR_REG (DR_REG_LP_WDT_BASE + 0x30)
|
||||
/** LP_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_SUPER_WDT_INT_CLR (BIT(30))
|
||||
#define LP_WDT_SUPER_WDT_INT_CLR_M (LP_WDT_SUPER_WDT_INT_CLR_V << LP_WDT_SUPER_WDT_INT_CLR_S)
|
||||
#define LP_WDT_SUPER_WDT_INT_CLR_V 0x00000001U
|
||||
#define LP_WDT_SUPER_WDT_INT_CLR_S 30
|
||||
/** LP_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_LP_WDT_INT_CLR (BIT(31))
|
||||
#define LP_WDT_LP_WDT_INT_CLR_M (LP_WDT_LP_WDT_INT_CLR_V << LP_WDT_LP_WDT_INT_CLR_S)
|
||||
#define LP_WDT_LP_WDT_INT_CLR_V 0x00000001U
|
||||
#define LP_WDT_LP_WDT_INT_CLR_S 31
|
||||
|
||||
/** LP_WDT_PAUSE_EN_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_PAUSE_EN_REG (DR_REG_LP_WDT_BASE + 0x34)
|
||||
/** LP_WDT_PAUSE_EN : R/W; bitpos: [31]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_PAUSE_EN (BIT(31))
|
||||
#define LP_WDT_PAUSE_EN_M (LP_WDT_PAUSE_EN_V << LP_WDT_PAUSE_EN_S)
|
||||
#define LP_WDT_PAUSE_EN_V 0x00000001U
|
||||
#define LP_WDT_PAUSE_EN_S 31
|
||||
|
||||
/** LP_WDT_DATE_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_DATE_REG (DR_REG_LP_WDT_BASE + 0x3fc)
|
||||
/** LP_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 38818560;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_LP_WDT_DATE 0x7FFFFFFFU
|
||||
#define LP_WDT_LP_WDT_DATE_M (LP_WDT_LP_WDT_DATE_V << LP_WDT_LP_WDT_DATE_S)
|
||||
#define LP_WDT_LP_WDT_DATE_V 0x7FFFFFFFU
|
||||
#define LP_WDT_LP_WDT_DATE_S 0
|
||||
/** LP_WDT_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define LP_WDT_CLK_EN (BIT(31))
|
||||
#define LP_WDT_CLK_EN_M (LP_WDT_CLK_EN_V << LP_WDT_CLK_EN_S)
|
||||
#define LP_WDT_CLK_EN_V 0x00000001U
|
||||
#define LP_WDT_CLK_EN_S 31
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
@@ -3955,7 +3955,7 @@ extern "C" {
|
||||
* used for future potential eco, others don't care
|
||||
*/
|
||||
#define PMU_PUF_MEM_CTRL_REG (DR_REG_PMU_BASE + 0x210)
|
||||
/** PMU_PUF_MEM_PSW : R/W; bitpos: [0]; default: 1;
|
||||
/** PMU_PUF_MEM_PSW : R/W; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define PMU_PUF_MEM_PSW (BIT(0))
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -82,7 +82,7 @@
|
||||
#define DR_REG_HP_PERI1_PMS_BASE 0x2058A000
|
||||
#define DR_REG_LP_SYS_BASE 0x20700000
|
||||
#define DR_REG_LP_CLKRST_BASE 0x20701000
|
||||
#define DR_REG_LP_ANA_PERI_BASE 0x20702000
|
||||
#define DR_REG_LP_ANA_BASE 0x20702000
|
||||
#define DR_REG_HUK_BASE 0x20703000
|
||||
#define DR_REG_PMU_BASE 0x20704000
|
||||
#define DR_REG_TOUCH_AON_BASE 0x20705000
|
||||
@@ -94,8 +94,8 @@
|
||||
#define DR_REG_LP_GPIO_BASE 0x20713000
|
||||
#define DR_REG_LP_INTR_BASE 0x20714000
|
||||
#define DR_REG_EFUSE_BASE 0x20715000
|
||||
#define DR_REG_LP_TIMER_BASE 0x20800000
|
||||
#define DR_REG_LP_WDT_BASE 0x20801000
|
||||
#define DR_REG_RTC_TIMER_BASE 0x20800000
|
||||
#define DR_REG_RTC_WDT_BASE 0x20801000
|
||||
#define DR_REG_RTCLOCKCALI0_BASE 0x20802000
|
||||
#define DR_REG_RTCLOCKCALI1_BASE 0x20803000
|
||||
#define DR_REG_LP_PWR_REG_BASE 0x20804000
|
||||
|
||||
+1
-1
@@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
+36
-123
@@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
@@ -10,68 +10,23 @@
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** Group: configure_register */
|
||||
/** Type of tar0_low register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** main_timer_tar_low0 : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t main_timer_tar_low0:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_timer_tar0_low_reg_t;
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t target_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lo;
|
||||
union {
|
||||
struct {
|
||||
uint32_t target_hi: 16;
|
||||
uint32_t reserved0: 15;
|
||||
uint32_t enable : 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} hi;
|
||||
} rtc_timer_target_reg_t;
|
||||
|
||||
/** Type of tar0_high register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** main_timer_tar_high0 : R/W; bitpos: [15:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t main_timer_tar_high0:16;
|
||||
uint32_t reserved_16:15;
|
||||
/** main_timer_tar_en0 : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t main_timer_tar_en0:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_timer_tar0_high_reg_t;
|
||||
|
||||
/** Type of tar1_low register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** main_timer_tar_low1 : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t main_timer_tar_low1:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_timer_tar1_low_reg_t;
|
||||
|
||||
/** Type of tar1_high register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** main_timer_tar_high1 : R/W; bitpos: [15:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t main_timer_tar_high1:16;
|
||||
uint32_t reserved_16:15;
|
||||
/** main_timer_tar_en1 : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t main_timer_tar_en1:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_timer_tar1_high_reg_t;
|
||||
|
||||
/** Type of update register
|
||||
* need_des
|
||||
@@ -107,59 +62,21 @@ typedef union {
|
||||
uint32_t val;
|
||||
} rtc_timer_update_reg_t;
|
||||
|
||||
/** Type of main_buf0_low register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** main_timer_buf0_low : RO; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t main_timer_buf0_low:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_timer_main_buf0_low_reg_t;
|
||||
|
||||
/** Type of main_buf0_high register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** main_timer_buf0_high : RO; bitpos: [15:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t main_timer_buf0_high:16;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_timer_main_buf0_high_reg_t;
|
||||
|
||||
/** Type of main_buf1_low register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** main_timer_buf1_low : RO; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t main_timer_buf1_low:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_timer_main_buf1_low_reg_t;
|
||||
|
||||
/** Type of main_buf1_high register
|
||||
* need_des
|
||||
*/
|
||||
typedef union {
|
||||
struct {
|
||||
/** main_timer_buf1_high : RO; bitpos: [15:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
uint32_t main_timer_buf1_high:16;
|
||||
uint32_t reserved_16:16;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_timer_main_buf1_high_reg_t;
|
||||
typedef struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t counter_lo: 32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lo;
|
||||
union {
|
||||
struct {
|
||||
uint32_t counter_hi: 16;
|
||||
uint32_t reserved0 : 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} hi;
|
||||
} rtc_timer_counter_reg_t;
|
||||
|
||||
/** Type of main_overflow register
|
||||
* need_des
|
||||
@@ -402,15 +319,9 @@ typedef union {
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile rtc_timer_tar0_low_reg_t tar0_low;
|
||||
volatile rtc_timer_tar0_high_reg_t tar0_high;
|
||||
volatile rtc_timer_tar1_low_reg_t tar1_low;
|
||||
volatile rtc_timer_tar1_high_reg_t tar1_high;
|
||||
volatile rtc_timer_target_reg_t target[2];
|
||||
volatile rtc_timer_update_reg_t update;
|
||||
volatile rtc_timer_main_buf0_low_reg_t main_buf0_low;
|
||||
volatile rtc_timer_main_buf0_high_reg_t main_buf0_high;
|
||||
volatile rtc_timer_main_buf1_low_reg_t main_buf1_low;
|
||||
volatile rtc_timer_main_buf1_high_reg_t main_buf1_high;
|
||||
volatile rtc_timer_counter_reg_t counter[2];
|
||||
volatile rtc_timer_main_overflow_reg_t main_overflow;
|
||||
volatile rtc_timer_int_raw_reg_t int_raw;
|
||||
volatile rtc_timer_int_st_reg_t int_st;
|
||||
@@ -429,6 +340,8 @@ typedef struct {
|
||||
_Static_assert(sizeof(rtc_timer_dev_t) == 0x400, "Invalid size of rtc_timer_dev_t structure");
|
||||
#endif
|
||||
|
||||
extern rtc_timer_dev_t RTC_TIMER;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,336 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/** RTC_WDT_CONFIG0_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_CONFIG0_REG (DR_REG_RTC_WDT_BASE + 0x0)
|
||||
/** RTC_WDT_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_PAUSE_IN_SLP (BIT(9))
|
||||
#define RTC_WDT_WDT_PAUSE_IN_SLP_M (RTC_WDT_WDT_PAUSE_IN_SLP_V << RTC_WDT_WDT_PAUSE_IN_SLP_S)
|
||||
#define RTC_WDT_WDT_PAUSE_IN_SLP_V 0x00000001U
|
||||
#define RTC_WDT_WDT_PAUSE_IN_SLP_S 9
|
||||
/** RTC_WDT_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_APPCPU_RESET_EN (BIT(10))
|
||||
#define RTC_WDT_WDT_APPCPU_RESET_EN_M (RTC_WDT_WDT_APPCPU_RESET_EN_V << RTC_WDT_WDT_APPCPU_RESET_EN_S)
|
||||
#define RTC_WDT_WDT_APPCPU_RESET_EN_V 0x00000001U
|
||||
#define RTC_WDT_WDT_APPCPU_RESET_EN_S 10
|
||||
/** RTC_WDT_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_PROCPU_RESET_EN (BIT(11))
|
||||
#define RTC_WDT_WDT_PROCPU_RESET_EN_M (RTC_WDT_WDT_PROCPU_RESET_EN_V << RTC_WDT_WDT_PROCPU_RESET_EN_S)
|
||||
#define RTC_WDT_WDT_PROCPU_RESET_EN_V 0x00000001U
|
||||
#define RTC_WDT_WDT_PROCPU_RESET_EN_S 11
|
||||
/** RTC_WDT_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_FLASHBOOT_MOD_EN (BIT(12))
|
||||
#define RTC_WDT_WDT_FLASHBOOT_MOD_EN_M (RTC_WDT_WDT_FLASHBOOT_MOD_EN_V << RTC_WDT_WDT_FLASHBOOT_MOD_EN_S)
|
||||
#define RTC_WDT_WDT_FLASHBOOT_MOD_EN_V 0x00000001U
|
||||
#define RTC_WDT_WDT_FLASHBOOT_MOD_EN_S 12
|
||||
/** RTC_WDT_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_SYS_RESET_LENGTH 0x00000007U
|
||||
#define RTC_WDT_WDT_SYS_RESET_LENGTH_M (RTC_WDT_WDT_SYS_RESET_LENGTH_V << RTC_WDT_WDT_SYS_RESET_LENGTH_S)
|
||||
#define RTC_WDT_WDT_SYS_RESET_LENGTH_V 0x00000007U
|
||||
#define RTC_WDT_WDT_SYS_RESET_LENGTH_S 13
|
||||
/** RTC_WDT_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_CPU_RESET_LENGTH 0x00000007U
|
||||
#define RTC_WDT_WDT_CPU_RESET_LENGTH_M (RTC_WDT_WDT_CPU_RESET_LENGTH_V << RTC_WDT_WDT_CPU_RESET_LENGTH_S)
|
||||
#define RTC_WDT_WDT_CPU_RESET_LENGTH_V 0x00000007U
|
||||
#define RTC_WDT_WDT_CPU_RESET_LENGTH_S 16
|
||||
/** RTC_WDT_WDT_STG3 : R/W; bitpos: [21:19]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG3 0x00000007U
|
||||
#define RTC_WDT_WDT_STG3_M (RTC_WDT_WDT_STG3_V << RTC_WDT_WDT_STG3_S)
|
||||
#define RTC_WDT_WDT_STG3_V 0x00000007U
|
||||
#define RTC_WDT_WDT_STG3_S 19
|
||||
/** RTC_WDT_WDT_STG2 : R/W; bitpos: [24:22]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG2 0x00000007U
|
||||
#define RTC_WDT_WDT_STG2_M (RTC_WDT_WDT_STG2_V << RTC_WDT_WDT_STG2_S)
|
||||
#define RTC_WDT_WDT_STG2_V 0x00000007U
|
||||
#define RTC_WDT_WDT_STG2_S 22
|
||||
/** RTC_WDT_WDT_STG1 : R/W; bitpos: [27:25]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG1 0x00000007U
|
||||
#define RTC_WDT_WDT_STG1_M (RTC_WDT_WDT_STG1_V << RTC_WDT_WDT_STG1_S)
|
||||
#define RTC_WDT_WDT_STG1_V 0x00000007U
|
||||
#define RTC_WDT_WDT_STG1_S 25
|
||||
/** RTC_WDT_WDT_STG0 : R/W; bitpos: [30:28]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG0 0x00000007U
|
||||
#define RTC_WDT_WDT_STG0_M (RTC_WDT_WDT_STG0_V << RTC_WDT_WDT_STG0_S)
|
||||
#define RTC_WDT_WDT_STG0_V 0x00000007U
|
||||
#define RTC_WDT_WDT_STG0_S 28
|
||||
/** RTC_WDT_WDT_EN : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_EN (BIT(31))
|
||||
#define RTC_WDT_WDT_EN_M (RTC_WDT_WDT_EN_V << RTC_WDT_WDT_EN_S)
|
||||
#define RTC_WDT_WDT_EN_V 0x00000001U
|
||||
#define RTC_WDT_WDT_EN_S 31
|
||||
|
||||
/** RTC_WDT_CONFIG1_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_CONFIG1_REG (DR_REG_RTC_WDT_BASE + 0x4)
|
||||
/** RTC_WDT_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG0_HOLD 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG0_HOLD_M (RTC_WDT_WDT_STG0_HOLD_V << RTC_WDT_WDT_STG0_HOLD_S)
|
||||
#define RTC_WDT_WDT_STG0_HOLD_V 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG0_HOLD_S 0
|
||||
|
||||
/** RTC_WDT_CONFIG2_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_CONFIG2_REG (DR_REG_RTC_WDT_BASE + 0x8)
|
||||
/** RTC_WDT_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG1_HOLD 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG1_HOLD_M (RTC_WDT_WDT_STG1_HOLD_V << RTC_WDT_WDT_STG1_HOLD_S)
|
||||
#define RTC_WDT_WDT_STG1_HOLD_V 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG1_HOLD_S 0
|
||||
|
||||
/** RTC_WDT_CONFIG3_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_CONFIG3_REG (DR_REG_RTC_WDT_BASE + 0xc)
|
||||
/** RTC_WDT_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG2_HOLD 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG2_HOLD_M (RTC_WDT_WDT_STG2_HOLD_V << RTC_WDT_WDT_STG2_HOLD_S)
|
||||
#define RTC_WDT_WDT_STG2_HOLD_V 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG2_HOLD_S 0
|
||||
|
||||
/** RTC_WDT_CONFIG4_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_CONFIG4_REG (DR_REG_RTC_WDT_BASE + 0x10)
|
||||
/** RTC_WDT_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_STG3_HOLD 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG3_HOLD_M (RTC_WDT_WDT_STG3_HOLD_V << RTC_WDT_WDT_STG3_HOLD_S)
|
||||
#define RTC_WDT_WDT_STG3_HOLD_V 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_STG3_HOLD_S 0
|
||||
|
||||
/** RTC_WDT_FEED_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_FEED_REG (DR_REG_RTC_WDT_BASE + 0x14)
|
||||
/** RTC_WDT_FEED : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_FEED (BIT(31))
|
||||
#define RTC_WDT_FEED_M (RTC_WDT_FEED_V << RTC_WDT_FEED_S)
|
||||
#define RTC_WDT_FEED_V 0x00000001U
|
||||
#define RTC_WDT_FEED_S 31
|
||||
|
||||
/** RTC_WDT_WPROTECT_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WPROTECT_REG (DR_REG_RTC_WDT_BASE + 0x18)
|
||||
/** RTC_WDT_WDT_WKEY : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_WDT_WKEY 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_WKEY_M (RTC_WDT_WDT_WKEY_V << RTC_WDT_WDT_WKEY_S)
|
||||
#define RTC_WDT_WDT_WKEY_V 0xFFFFFFFFU
|
||||
#define RTC_WDT_WDT_WKEY_S 0
|
||||
|
||||
/** RTC_WDT_SWD_CONFIG_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_CONFIG_REG (DR_REG_RTC_WDT_BASE + 0x1c)
|
||||
/** RTC_WDT_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_RESET_FLAG (BIT(0))
|
||||
#define RTC_WDT_SWD_RESET_FLAG_M (RTC_WDT_SWD_RESET_FLAG_V << RTC_WDT_SWD_RESET_FLAG_S)
|
||||
#define RTC_WDT_SWD_RESET_FLAG_V 0x00000001U
|
||||
#define RTC_WDT_SWD_RESET_FLAG_S 0
|
||||
/** RTC_WDT_SWD_AUTO_FEED_EN : R/W; bitpos: [18]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_AUTO_FEED_EN (BIT(18))
|
||||
#define RTC_WDT_SWD_AUTO_FEED_EN_M (RTC_WDT_SWD_AUTO_FEED_EN_V << RTC_WDT_SWD_AUTO_FEED_EN_S)
|
||||
#define RTC_WDT_SWD_AUTO_FEED_EN_V 0x00000001U
|
||||
#define RTC_WDT_SWD_AUTO_FEED_EN_S 18
|
||||
/** RTC_WDT_SWD_RST_FLAG_CLR : WT; bitpos: [19]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_RST_FLAG_CLR (BIT(19))
|
||||
#define RTC_WDT_SWD_RST_FLAG_CLR_M (RTC_WDT_SWD_RST_FLAG_CLR_V << RTC_WDT_SWD_RST_FLAG_CLR_S)
|
||||
#define RTC_WDT_SWD_RST_FLAG_CLR_V 0x00000001U
|
||||
#define RTC_WDT_SWD_RST_FLAG_CLR_S 19
|
||||
/** RTC_WDT_SWD_SIGNAL_WIDTH : R/W; bitpos: [29:20]; default: 300;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_SIGNAL_WIDTH 0x000003FFU
|
||||
#define RTC_WDT_SWD_SIGNAL_WIDTH_M (RTC_WDT_SWD_SIGNAL_WIDTH_V << RTC_WDT_SWD_SIGNAL_WIDTH_S)
|
||||
#define RTC_WDT_SWD_SIGNAL_WIDTH_V 0x000003FFU
|
||||
#define RTC_WDT_SWD_SIGNAL_WIDTH_S 20
|
||||
/** RTC_WDT_SWD_DISABLE : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_DISABLE (BIT(30))
|
||||
#define RTC_WDT_SWD_DISABLE_M (RTC_WDT_SWD_DISABLE_V << RTC_WDT_SWD_DISABLE_S)
|
||||
#define RTC_WDT_SWD_DISABLE_V 0x00000001U
|
||||
#define RTC_WDT_SWD_DISABLE_S 30
|
||||
/** RTC_WDT_SWD_FEED : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_FEED (BIT(31))
|
||||
#define RTC_WDT_SWD_FEED_M (RTC_WDT_SWD_FEED_V << RTC_WDT_SWD_FEED_S)
|
||||
#define RTC_WDT_SWD_FEED_V 0x00000001U
|
||||
#define RTC_WDT_SWD_FEED_S 31
|
||||
|
||||
/** RTC_WDT_SWD_WPROTECT_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_WPROTECT_REG (DR_REG_RTC_WDT_BASE + 0x20)
|
||||
/** RTC_WDT_SWD_WKEY : R/W; bitpos: [31:0]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SWD_WKEY 0xFFFFFFFFU
|
||||
#define RTC_WDT_SWD_WKEY_M (RTC_WDT_SWD_WKEY_V << RTC_WDT_SWD_WKEY_S)
|
||||
#define RTC_WDT_SWD_WKEY_V 0xFFFFFFFFU
|
||||
#define RTC_WDT_SWD_WKEY_S 0
|
||||
|
||||
/** RTC_WDT_INT_RAW_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_INT_RAW_REG (DR_REG_RTC_WDT_BASE + 0x24)
|
||||
/** RTC_WDT_SUPER_WDT_INT_RAW : R/WTC/SS; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SUPER_WDT_INT_RAW (BIT(30))
|
||||
#define RTC_WDT_SUPER_WDT_INT_RAW_M (RTC_WDT_SUPER_WDT_INT_RAW_V << RTC_WDT_SUPER_WDT_INT_RAW_S)
|
||||
#define RTC_WDT_SUPER_WDT_INT_RAW_V 0x00000001U
|
||||
#define RTC_WDT_SUPER_WDT_INT_RAW_S 30
|
||||
/** RTC_WDT_LP_WDT_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_LP_WDT_INT_RAW (BIT(31))
|
||||
#define RTC_WDT_LP_WDT_INT_RAW_M (RTC_WDT_LP_WDT_INT_RAW_V << RTC_WDT_LP_WDT_INT_RAW_S)
|
||||
#define RTC_WDT_LP_WDT_INT_RAW_V 0x00000001U
|
||||
#define RTC_WDT_LP_WDT_INT_RAW_S 31
|
||||
|
||||
/** RTC_WDT_INT_ST_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_INT_ST_REG (DR_REG_RTC_WDT_BASE + 0x28)
|
||||
/** RTC_WDT_SUPER_WDT_INT_ST : RO; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SUPER_WDT_INT_ST (BIT(30))
|
||||
#define RTC_WDT_SUPER_WDT_INT_ST_M (RTC_WDT_SUPER_WDT_INT_ST_V << RTC_WDT_SUPER_WDT_INT_ST_S)
|
||||
#define RTC_WDT_SUPER_WDT_INT_ST_V 0x00000001U
|
||||
#define RTC_WDT_SUPER_WDT_INT_ST_S 30
|
||||
/** RTC_WDT_LP_WDT_INT_ST : RO; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_LP_WDT_INT_ST (BIT(31))
|
||||
#define RTC_WDT_LP_WDT_INT_ST_M (RTC_WDT_LP_WDT_INT_ST_V << RTC_WDT_LP_WDT_INT_ST_S)
|
||||
#define RTC_WDT_LP_WDT_INT_ST_V 0x00000001U
|
||||
#define RTC_WDT_LP_WDT_INT_ST_S 31
|
||||
|
||||
/** RTC_WDT_INT_ENA_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_INT_ENA_REG (DR_REG_RTC_WDT_BASE + 0x2c)
|
||||
/** RTC_WDT_SUPER_WDT_INT_ENA : R/W; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SUPER_WDT_INT_ENA (BIT(30))
|
||||
#define RTC_WDT_SUPER_WDT_INT_ENA_M (RTC_WDT_SUPER_WDT_INT_ENA_V << RTC_WDT_SUPER_WDT_INT_ENA_S)
|
||||
#define RTC_WDT_SUPER_WDT_INT_ENA_V 0x00000001U
|
||||
#define RTC_WDT_SUPER_WDT_INT_ENA_S 30
|
||||
/** RTC_WDT_LP_WDT_INT_ENA : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_LP_WDT_INT_ENA (BIT(31))
|
||||
#define RTC_WDT_LP_WDT_INT_ENA_M (RTC_WDT_LP_WDT_INT_ENA_V << RTC_WDT_LP_WDT_INT_ENA_S)
|
||||
#define RTC_WDT_LP_WDT_INT_ENA_V 0x00000001U
|
||||
#define RTC_WDT_LP_WDT_INT_ENA_S 31
|
||||
|
||||
/** RTC_WDT_INT_CLR_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_INT_CLR_REG (DR_REG_RTC_WDT_BASE + 0x30)
|
||||
/** RTC_WDT_SUPER_WDT_INT_CLR : WT; bitpos: [30]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_SUPER_WDT_INT_CLR (BIT(30))
|
||||
#define RTC_WDT_SUPER_WDT_INT_CLR_M (RTC_WDT_SUPER_WDT_INT_CLR_V << RTC_WDT_SUPER_WDT_INT_CLR_S)
|
||||
#define RTC_WDT_SUPER_WDT_INT_CLR_V 0x00000001U
|
||||
#define RTC_WDT_SUPER_WDT_INT_CLR_S 30
|
||||
/** RTC_WDT_LP_WDT_INT_CLR : WT; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_LP_WDT_INT_CLR (BIT(31))
|
||||
#define RTC_WDT_LP_WDT_INT_CLR_M (RTC_WDT_LP_WDT_INT_CLR_V << RTC_WDT_LP_WDT_INT_CLR_S)
|
||||
#define RTC_WDT_LP_WDT_INT_CLR_V 0x00000001U
|
||||
#define RTC_WDT_LP_WDT_INT_CLR_S 31
|
||||
|
||||
/** RTC_WDT_PAUSE_EN_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_PAUSE_EN_REG (DR_REG_RTC_WDT_BASE + 0x34)
|
||||
/** RTC_WDT_PAUSE_EN : R/W; bitpos: [31]; default: 1;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_PAUSE_EN (BIT(31))
|
||||
#define RTC_WDT_PAUSE_EN_M (RTC_WDT_PAUSE_EN_V << RTC_WDT_PAUSE_EN_S)
|
||||
#define RTC_WDT_PAUSE_EN_V 0x00000001U
|
||||
#define RTC_WDT_PAUSE_EN_S 31
|
||||
|
||||
/** RTC_WDT_DATE_REG register
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_DATE_REG (DR_REG_RTC_WDT_BASE + 0x3fc)
|
||||
/** RTC_WDT_LP_WDT_DATE : R/W; bitpos: [30:0]; default: 38818560;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_LP_WDT_DATE 0x7FFFFFFFU
|
||||
#define RTC_WDT_LP_WDT_DATE_M (RTC_WDT_LP_WDT_DATE_V << RTC_WDT_LP_WDT_DATE_S)
|
||||
#define RTC_WDT_LP_WDT_DATE_V 0x7FFFFFFFU
|
||||
#define RTC_WDT_LP_WDT_DATE_S 0
|
||||
/** RTC_WDT_CLK_EN : R/W; bitpos: [31]; default: 0;
|
||||
* need_des
|
||||
*/
|
||||
#define RTC_WDT_CLK_EN (BIT(31))
|
||||
#define RTC_WDT_CLK_EN_M (RTC_WDT_CLK_EN_V << RTC_WDT_CLK_EN_S)
|
||||
#define RTC_WDT_CLK_EN_V 0x00000001U
|
||||
#define RTC_WDT_CLK_EN_S 31
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
+34
-34
@@ -1,5 +1,5 @@
|
||||
/**
|
||||
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
@@ -63,7 +63,7 @@ typedef union {
|
||||
uint32_t wdt_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_config0_reg_t;
|
||||
} rtc_wdt_config0_reg_t;
|
||||
|
||||
/** Type of config1 register
|
||||
* need_des
|
||||
@@ -76,7 +76,7 @@ typedef union {
|
||||
uint32_t wdt_stg0_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_config1_reg_t;
|
||||
} rtc_wdt_config1_reg_t;
|
||||
|
||||
/** Type of config2 register
|
||||
* need_des
|
||||
@@ -89,7 +89,7 @@ typedef union {
|
||||
uint32_t wdt_stg1_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_config2_reg_t;
|
||||
} rtc_wdt_config2_reg_t;
|
||||
|
||||
/** Type of config3 register
|
||||
* need_des
|
||||
@@ -102,7 +102,7 @@ typedef union {
|
||||
uint32_t wdt_stg2_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_config3_reg_t;
|
||||
} rtc_wdt_config3_reg_t;
|
||||
|
||||
/** Type of config4 register
|
||||
* need_des
|
||||
@@ -115,7 +115,7 @@ typedef union {
|
||||
uint32_t wdt_stg3_hold:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_config4_reg_t;
|
||||
} rtc_wdt_config4_reg_t;
|
||||
|
||||
/** Type of feed register
|
||||
* need_des
|
||||
@@ -129,7 +129,7 @@ typedef union {
|
||||
uint32_t feed:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_feed_reg_t;
|
||||
} rtc_wdt_feed_reg_t;
|
||||
|
||||
/** Type of wprotect register
|
||||
* need_des
|
||||
@@ -142,7 +142,7 @@ typedef union {
|
||||
uint32_t wdt_wkey:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_wprotect_reg_t;
|
||||
} rtc_wdt_wprotect_reg_t;
|
||||
|
||||
/** Type of swd_config register
|
||||
* need_des
|
||||
@@ -176,7 +176,7 @@ typedef union {
|
||||
uint32_t swd_feed:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_swd_config_reg_t;
|
||||
} rtc_wdt_swd_config_reg_t;
|
||||
|
||||
/** Type of swd_wprotect register
|
||||
* need_des
|
||||
@@ -189,7 +189,7 @@ typedef union {
|
||||
uint32_t swd_wkey:32;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_swd_wprotect_reg_t;
|
||||
} rtc_wdt_swd_wprotect_reg_t;
|
||||
|
||||
/** Type of int_raw register
|
||||
* need_des
|
||||
@@ -207,7 +207,7 @@ typedef union {
|
||||
uint32_t lp_wdt_int_raw:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_int_raw_reg_t;
|
||||
} rtc_wdt_int_raw_reg_t;
|
||||
|
||||
/** Type of int_st register
|
||||
* need_des
|
||||
@@ -225,7 +225,7 @@ typedef union {
|
||||
uint32_t lp_wdt_int_st:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_int_st_reg_t;
|
||||
} rtc_wdt_int_st_reg_t;
|
||||
|
||||
/** Type of int_ena register
|
||||
* need_des
|
||||
@@ -243,7 +243,7 @@ typedef union {
|
||||
uint32_t lp_wdt_int_ena:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_int_ena_reg_t;
|
||||
} rtc_wdt_int_ena_reg_t;
|
||||
|
||||
/** Type of int_clr register
|
||||
* need_des
|
||||
@@ -261,7 +261,7 @@ typedef union {
|
||||
uint32_t lp_wdt_int_clr:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_int_clr_reg_t;
|
||||
} rtc_wdt_int_clr_reg_t;
|
||||
|
||||
/** Type of pause_en register
|
||||
* need_des
|
||||
@@ -275,7 +275,7 @@ typedef union {
|
||||
uint32_t pause_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_pause_en_reg_t;
|
||||
} rtc_wdt_pause_en_reg_t;
|
||||
|
||||
/** Type of date register
|
||||
* need_des
|
||||
@@ -292,32 +292,32 @@ typedef union {
|
||||
uint32_t clk_en:1;
|
||||
};
|
||||
uint32_t val;
|
||||
} lp_wdt_date_reg_t;
|
||||
} rtc_wdt_date_reg_t;
|
||||
|
||||
|
||||
typedef struct {
|
||||
volatile lp_wdt_config0_reg_t config0;
|
||||
volatile lp_wdt_config1_reg_t config1;
|
||||
volatile lp_wdt_config2_reg_t config2;
|
||||
volatile lp_wdt_config3_reg_t config3;
|
||||
volatile lp_wdt_config4_reg_t config4;
|
||||
volatile lp_wdt_feed_reg_t feed;
|
||||
volatile lp_wdt_wprotect_reg_t wprotect;
|
||||
volatile lp_wdt_swd_config_reg_t swd_config;
|
||||
volatile lp_wdt_swd_wprotect_reg_t swd_wprotect;
|
||||
volatile lp_wdt_int_raw_reg_t int_raw;
|
||||
volatile lp_wdt_int_st_reg_t int_st;
|
||||
volatile lp_wdt_int_ena_reg_t int_ena;
|
||||
volatile lp_wdt_int_clr_reg_t int_clr;
|
||||
volatile lp_wdt_pause_en_reg_t pause_en;
|
||||
volatile rtc_wdt_config0_reg_t config0;
|
||||
volatile rtc_wdt_config1_reg_t config1;
|
||||
volatile rtc_wdt_config2_reg_t config2;
|
||||
volatile rtc_wdt_config3_reg_t config3;
|
||||
volatile rtc_wdt_config4_reg_t config4;
|
||||
volatile rtc_wdt_feed_reg_t feed;
|
||||
volatile rtc_wdt_wprotect_reg_t wprotect;
|
||||
volatile rtc_wdt_swd_config_reg_t swd_config;
|
||||
volatile rtc_wdt_swd_wprotect_reg_t swd_wprotect;
|
||||
volatile rtc_wdt_int_raw_reg_t int_raw;
|
||||
volatile rtc_wdt_int_st_reg_t int_st;
|
||||
volatile rtc_wdt_int_ena_reg_t int_ena;
|
||||
volatile rtc_wdt_int_clr_reg_t int_clr;
|
||||
volatile rtc_wdt_pause_en_reg_t pause_en;
|
||||
uint32_t reserved_038[241];
|
||||
volatile lp_wdt_date_reg_t date;
|
||||
} lp_wdt_dev_t;
|
||||
volatile rtc_wdt_date_reg_t date;
|
||||
} rtc_wdt_dev_t;
|
||||
|
||||
extern lp_wdt_dev_t LP_WDT;
|
||||
extern rtc_wdt_dev_t RTC_WDT;
|
||||
|
||||
#ifndef __cplusplus
|
||||
_Static_assert(sizeof(lp_wdt_dev_t) == 0x400, "Invalid size of lp_wdt_dev_t structure");
|
||||
_Static_assert(sizeof(rtc_wdt_dev_t) == 0x400, "Invalid size of rtc_wdt_dev_t structure");
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0 OR MIT
|
||||
*/
|
||||
@@ -29,41 +29,46 @@
|
||||
#include "soc/lp_iomux_struct.h"
|
||||
#endif
|
||||
|
||||
// TODO: IDF-5645
|
||||
#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32P4 || CONFIG_IDF_TARGET_ESP32C5 || CONFIG_IDF_TARGET_ESP32C61 || CONFIG_IDF_TARGET_ESP32H4 || CONFIG_IDF_TARGET_ESP32S31
|
||||
#include "soc/lp_analog_peri_reg.h"
|
||||
#include "soc/lp_clkrst_reg.h"
|
||||
#include "soc/lp_clkrst_struct.h"
|
||||
#if SOC_RTC_TIMER_V1
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/rtc_cntl_struct.h"
|
||||
#elif SOC_RTC_TIMER_V2
|
||||
#include "soc/lp_timer_reg.h"
|
||||
#include "soc/lp_timer_struct.h"
|
||||
#elif SOC_RTC_TIMER_V3
|
||||
#include "soc/rtc_timer_reg.h"
|
||||
#include "soc/rtc_timer_struct.h"
|
||||
#endif
|
||||
|
||||
#if SOC_PMU_SUPPORTED
|
||||
#include "soc/pmu_reg.h"
|
||||
#endif
|
||||
|
||||
#if SOC_LP_I2C_SUPPORTED
|
||||
#include "soc/lp_i2c_reg.h"
|
||||
#include "soc/lp_i2c_struct.h"
|
||||
#endif
|
||||
#if SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#include "soc/lp_timer_reg.h"
|
||||
#include "soc/lp_timer_struct.h"
|
||||
#endif
|
||||
|
||||
#if SOC_ULP_LP_UART_SUPPORTED
|
||||
#include "soc/lp_uart_reg.h"
|
||||
#include "soc/lp_uart_struct.h"
|
||||
#endif
|
||||
#include "soc/lp_wdt_reg.h"
|
||||
#include "soc/lp_wdt_struct.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H2
|
||||
// ESP32H2-TODO: IDF-6327
|
||||
|
||||
#if __has_include("soc/lp_analog_peri_reg.h")
|
||||
#include "soc/lp_analog_peri_reg.h"
|
||||
#include "soc/lp_clkrst_reg.h"
|
||||
#include "soc/lp_clkrst_struct.h"
|
||||
#include "soc/lp_timer_reg.h"
|
||||
#include "soc/lp_timer_struct.h"
|
||||
#include "soc/lp_wdt_reg.h"
|
||||
#include "soc/lp_wdt_struct.h"
|
||||
#elif CONFIG_IDF_TARGET_ESP32H21
|
||||
#include "soc/lp_analog_peri_reg.h"
|
||||
#include "soc/lp_clkrst_reg.h"
|
||||
#include "soc/lp_clkrst_struct.h"
|
||||
#include "soc/lp_wdt_reg.h"
|
||||
#include "soc/lp_wdt_struct.h"
|
||||
#else
|
||||
#include "soc/rtc_cntl_reg.h"
|
||||
#include "soc/rtc_cntl_struct.h"
|
||||
#endif
|
||||
|
||||
#if __has_include("soc/lp_clkrst_reg.h")
|
||||
#include "soc/lp_clkrst_reg.h"
|
||||
#include "soc/lp_clkrst_struct.h"
|
||||
#endif
|
||||
|
||||
#if __has_include("soc/lp_wdt_reg.h")
|
||||
#include "soc/lp_wdt_reg.h"
|
||||
#include "soc/lp_wdt_struct.h"
|
||||
#endif
|
||||
|
||||
#if __has_include("soc/rtc_wdt_reg.h")
|
||||
#include "soc/rtc_wdt_reg.h"
|
||||
#include "soc/rtc_wdt_struct.h"
|
||||
#endif
|
||||
|
||||
@@ -65,7 +65,7 @@ if(CONFIG_ULP_COPROC_TYPE_LP_CORE)
|
||||
list(APPEND srcs "lp_core/lp_core_i2c.c")
|
||||
endif()
|
||||
|
||||
if(CONFIG_SOC_RTC_TIMER_V2_SUPPORTED)
|
||||
if(CONFIG_SOC_RTC_TIMER_V2)
|
||||
list(APPEND srcs "lp_core/shared/ulp_lp_core_lp_timer_shared.c")
|
||||
endif()
|
||||
|
||||
|
||||
@@ -127,7 +127,7 @@ esp_err_t ulp_lp_core_run(ulp_lp_core_cfg_t* cfg)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#if SOC_RTC_TIMER_SUPPORTED
|
||||
ulp_lp_core_memory_shared_cfg_t* shared_mem = ulp_lp_core_memory_shared_cfg_get();
|
||||
|
||||
if (cfg->wakeup_source & ULP_LP_CORE_WAKEUP_SOURCE_LP_TIMER) {
|
||||
|
||||
@@ -161,7 +161,7 @@ static inline void ulp_lp_core_sw_intr_clear(void)
|
||||
return ulp_lp_core_sw_intr_from_hp_clear();
|
||||
}
|
||||
|
||||
#if SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#if SOC_RTC_TIMER_SUPPORTED
|
||||
/**
|
||||
* @brief Enable the LP Timer interrupt
|
||||
*
|
||||
|
||||
@@ -28,13 +28,13 @@ void lp_core_startup()
|
||||
|
||||
ulp_lp_core_memory_shared_cfg_t* shared_mem = ulp_lp_core_memory_shared_cfg_get();
|
||||
|
||||
#if SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#if SOC_RTC_TIMER_SUPPORTED
|
||||
uint64_t sleep_duration_ticks = shared_mem->sleep_duration_ticks;
|
||||
|
||||
if (sleep_duration_ticks) {
|
||||
ulp_lp_core_lp_timer_set_wakeup_ticks(sleep_duration_ticks);
|
||||
}
|
||||
#endif // SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#endif // SOC_RTC_TIMER_SUPPORTED
|
||||
|
||||
ulp_lp_core_halt();
|
||||
}
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -19,7 +19,7 @@
|
||||
#include "hal/lp_i2s_ll.h"
|
||||
#endif
|
||||
|
||||
#if SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#if SOC_RTC_TIMER_SUPPORTED
|
||||
#include "hal/rtc_timer_ll.h"
|
||||
#endif
|
||||
|
||||
@@ -82,13 +82,13 @@ void ulp_lp_core_update_wakeup_cause(void)
|
||||
}
|
||||
#endif /* SOC_ETM_SUPPORTED */
|
||||
|
||||
#if SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#if SOC_RTC_TIMER_SUPPORTED
|
||||
if ((lp_core_ll_get_wakeup_source() & LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER) \
|
||||
&& (rtc_timer_ll_get_intr_raw(&LP_TIMER, 1) & LP_TIMER_MAIN_TIMER_LP_INT_RAW)) {
|
||||
lp_wakeup_cause |= LP_CORE_LL_WAKEUP_SOURCE_LP_TIMER;
|
||||
rtc_timer_ll_clear_alarm_intr_status(&LP_TIMER, 1);
|
||||
}
|
||||
#endif /* SOC_RTC_TIMER_V2_SUPPORTED */
|
||||
#endif /* SOC_RTC_TIMER_SUPPORTED */
|
||||
|
||||
}
|
||||
|
||||
@@ -196,7 +196,7 @@ void ulp_lp_core_sw_intr_from_hp_clear(void)
|
||||
pmu_ll_lp_clear_sw_intr_status(&PMU);
|
||||
}
|
||||
|
||||
#if SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#if SOC_RTC_TIMER_SUPPORTED
|
||||
void ulp_lp_core_lp_timer_intr_enable(bool enable)
|
||||
{
|
||||
rtc_timer_ll_alarm_intr_enable(&LP_TIMER, 1, enable);
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
#include "ulp_lp_core_lp_timer_shared.h"
|
||||
#include "soc/soc_caps.h"
|
||||
|
||||
#if SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#if SOC_RTC_TIMER_SUPPORTED
|
||||
#include "hal/rtc_timer_ll.h"
|
||||
#include "hal/clk_tree_ll.h"
|
||||
#include "soc/rtc.h"
|
||||
@@ -45,4 +45,4 @@ uint64_t ulp_lp_core_lp_timer_calculate_sleep_ticks(uint64_t sleep_duration_us)
|
||||
return (sleep_duration_us * (1 << RTC_CLK_CAL_FRACT) / clk_ll_rtc_slow_load_cal());
|
||||
}
|
||||
|
||||
#endif // SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#endif // SOC_RTC_TIMER_SUPPORTED
|
||||
|
||||
@@ -30,7 +30,7 @@ list(APPEND app_sources "test_lp_core_prefix.c")
|
||||
set(lp_core_sources "lp_core/test_main.c")
|
||||
set(lp_core_sources_counter "lp_core/test_main_counter.c")
|
||||
|
||||
if(CONFIG_SOC_RTC_TIMER_V2_SUPPORTED)
|
||||
if(CONFIG_SOC_RTC_TIMER_SUPPORTED)
|
||||
set(lp_core_sources_set_timer_wakeup "lp_core/test_main_set_timer_wakeup.c")
|
||||
endif()
|
||||
|
||||
@@ -71,7 +71,7 @@ ulp_embed_binary(lp_core_test_app "${lp_core_sources}" "${lp_core_exp_dep_srcs}"
|
||||
ulp_embed_binary(lp_core_test_app_counter "${lp_core_sources_counter}" "${lp_core_exp_dep_srcs}")
|
||||
ulp_embed_binary(lp_core_test_app_isr "lp_core/test_main_isr.c" "${lp_core_exp_dep_srcs}")
|
||||
|
||||
if(CONFIG_SOC_RTC_TIMER_V2_SUPPORTED)
|
||||
if(CONFIG_SOC_RTC_TIMER_SUPPORTED)
|
||||
ulp_embed_binary(lp_core_test_app_set_timer_wakeup "${lp_core_sources_set_timer_wakeup}" "${lp_core_exp_dep_srcs}")
|
||||
endif()
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
|
||||
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
@@ -13,7 +13,7 @@
|
||||
#include "lp_core_test_app_counter.h"
|
||||
#include "lp_core_test_app_isr.h"
|
||||
|
||||
#if SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#if SOC_RTC_TIMER_SUPPORTED
|
||||
#include "lp_core_test_app_set_timer_wakeup.h"
|
||||
#endif
|
||||
|
||||
@@ -295,7 +295,7 @@ TEST_CASE("LP core can be stopped and and started again from main CPU", "[ulp]")
|
||||
}
|
||||
}
|
||||
|
||||
#if SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#if SOC_RTC_TIMER_SUPPORTED
|
||||
TEST_CASE("LP core can schedule next wake-up time by itself", "[ulp]")
|
||||
{
|
||||
int64_t start, test_duration;
|
||||
@@ -342,7 +342,7 @@ TEST_CASE("LP core gpio tests", "[ulp]")
|
||||
}
|
||||
#endif //SOC_RTCIO_PIN_COUNT > 0
|
||||
|
||||
#endif // SOC_RTC_TIMER_V2_SUPPORTED
|
||||
#endif // SOC_RTC_TIMER_SUPPORTED
|
||||
|
||||
#define ISR_TEST_ITERATIONS 100
|
||||
#define IO_TEST_PIN 0
|
||||
|
||||
Reference in New Issue
Block a user