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Merge branch 'fix/esp32c61_rom_stack_addr_v6.0' into 'release/v6.0'

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fix(soc): Correct the ESP32-C61 ROM stack start address (v6.0)

See merge request espressif/esp-idf!47150
This commit is contained in:
Jiang Jiang Jian
2026-04-02 13:57:15 +08:00
parent 30c30dddf3 2f0e634586
commit b563fe2766
2 changed files with 14 additions and 14 deletions
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components/bootloader/subproject/main/ld/esp32c61/bootloader.ld.in
+13 -13
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@@ -10,20 +10,20 @@
* Make sure the bootloader can load into main memory without overwriting itself.
*
* ESP32-C61 ROM static data usage is as follows:
* - 0x4083ea70 - 0x4084ca70: Shared buffers, used in UART/USB/SPI download mode only
* - 0x4084ca70 - 0x4084ea70: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x4084ea70 - 0x40850000: ROM .bss and .data (not easily reclaimable)
* - 0x4083e670 - 0x4084c670: Shared buffers, used in UART/USB/SPI download mode only
* - 0x4084c670 - 0x4084e670: PRO CPU stack, can be reclaimed as heap after RTOS startup
* - 0x4084e670 - 0x40850000: ROM .bss and .data (not easily reclaimable)
*
* The 2nd stage bootloader can take space up to the end of ROM shared
* buffers area (0x4084ca70).
* buffers area (0x4084c670).
*/
/* We consider 0x4084ca70 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
/* We consider 0x4084c670 to be the last usable address for 2nd stage bootloader stack overhead, dram_seg,
* and work out iram_seg and iram_loader_seg addresses from there, backwards.
*/
/* These lengths can be adjusted, if necessary: */
bootloader_usable_dram_end = 0x4084ca70;
bootloader_usable_dram_end = 0x4084c670;
bootloader_stack_overhead = 0x2000; /* For safety margin between bootloader data section and startup stacks */
bootloader_dram_seg_len = 0x5000;
bootloader_iram_loader_seg_len = 0x7000;
@@ -48,7 +48,7 @@ MEMORY
* 2. Update the value in this assert.
* 3. Update SRAM_DRAM_END in components/esp_system/ld/esp32c61/memory.ld.in to the same value.
*/
ASSERT(bootloader_iram_loader_seg_start == 0x4083ea70, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
ASSERT(bootloader_iram_loader_seg_start == 0x4083e670, "bootloader_iram_loader_seg_start inconsistent with SRAM_DRAM_END");
/* Default entry point: */
ENTRY(call_start_cpu0);
@@ -293,32 +293,32 @@ SECTIONS
/**
* Appendix: Memory Usage of ROM bootloader
*
* 0x4083ea70 ------------------> _dram0_0_start
* 0x4083e670 ------------------> _dram0_0_start
* | |
* | |
* | | 1. Large buffers that are only used in certain boot modes, see shared_buffers.h
* | |
* | |
* 0x4084ca70 ------------------> __stack_sentry
* 0x4084c670 ------------------> _stack_sentry
* | |
* | | 2. Startup pro cpu stack (freed when IDF app is running)
* | |
* 0x4084ea70 ------------------> __stack (pro cpu)
* 0x4084e670 ------------------> __stack (pro cpu)
* | |
* | |
* | | 3. Shared memory only used in startup code or nonos/early boot*
* | | (can be freed when IDF runs)
* | |
* | |
* 0x4084f5d0 ------------------> _dram0_rtos_reserved_start
* 0x4084f5c8 ------------------> _dram0_rtos_reserved_start
* | |
* | |
* | | 4. Shared memory used in startup code and when IDF runs
* | |
* | |
* 0x4084fc58 ------------------> _dram0_rtos_reserved_end
* 0x4084fba0 ------------------> _dram0_rtos_reserved_end
* | |
* 0x4084fc6c ------------------> _data_start_interface
* 0x4084fc5a ------------------> _data_start_interface
* | |
* | | 5. End of DRAM is the 'interface' data with constant addresses (ECO compatible)
* | |
components/soc/esp32c61/include/soc/soc.h
+1 -1
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@@ -193,7 +193,7 @@
#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
// Start (highest address) of ROM boot stack, only relevant during early boot
#define SOC_ROM_STACK_START 0x4084ea70
#define SOC_ROM_STACK_START 0x4084e670
#define SOC_ROM_STACK_SIZE 0x2000
//On RISC-V CPUs, the interrupt sources are all external interrupts, whose type, source and priority are configured by SW.