refactor(i2c): cleanup I2C definitions in soc_caps.h

components/driver/i2c/i2c.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -189,7 +189,7 @@ typedef struct {
     int cmd_idx;                     /*!< record current command index, for master mode */
     int status;                      /*!< record current command status, for master mode */
     int rx_cnt;                      /*!< record current read index, for master mode */
-    uint8_t data_buf[SOC_I2C_FIFO_LEN ];  /*!< a buffer to store i2c fifo data */
+    uint8_t data_buf[I2C_LL_GET(FIFO_LEN)];  /*!< a buffer to store i2c fifo data */
 
     i2c_cmd_desc_t cmd_link;         /*!< I2C command link */
     QueueHandle_t cmd_evt_queue;     /*!< I2C command event queue */
@@ -214,7 +214,7 @@ typedef struct {
     i2c_hal_context_t hal;      /*!< I2C hal context */
     portMUX_TYPE spinlock;
     bool hw_enabled;
-#if !SOC_I2C_SUPPORT_HW_CLR_BUS
+#if !I2C_LL_SUPPORT_HW_CLR_BUS
     int scl_io_num;
     int sda_io_num;
 #endif
@@ -672,7 +672,7 @@ esp_err_t i2c_get_data_mode(i2c_port_t i2c_num, i2c_trans_mode_t *tx_trans_mode,
 static esp_err_t i2c_master_clear_bus(i2c_port_t i2c_num)
 {
     esp_err_t ret = ESP_OK;
-#if !SOC_I2C_SUPPORT_HW_CLR_BUS
+#if !I2C_LL_SUPPORT_HW_CLR_BUS
     const int scl_half_period = I2C_CLR_BUS_HALF_PERIOD_US; // use standard 100kHz data rate
     int i = 0;
     int scl_io = i2c_context[i2c_num].scl_io_num;
@@ -726,7 +726,7 @@ static esp_err_t i2c_hw_fsm_reset(i2c_port_t i2c_num)
 {
 // A workaround for avoiding cause timeout issue when using
 // hardware reset.
-#if !SOC_I2C_SUPPORT_HW_FSM_RST
+#if !I2C_LL_SUPPORT_HW_FSM_RST
     i2c_hal_timing_config_t timing_config;
     uint8_t filter_cfg;
 
@@ -1046,7 +1046,7 @@ esp_err_t i2c_set_pin(i2c_port_t i2c_num, gpio_num_t sda_io_num, gpio_num_t scl_
             gpio_set_pull_mode(scl_io_num, GPIO_FLOATING);
         }
     }
-#if !SOC_I2C_SUPPORT_HW_CLR_BUS
+#if !I2C_LL_SUPPORT_HW_CLR_BUS
     i2c_context[i2c_num].scl_io_num = scl_io_num;
     i2c_context[i2c_num].sda_io_num = sda_io_num;
 #endif
@@ -1484,7 +1484,7 @@ static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num, BaseType_t
 
             //TODO: to reduce interrupt number
             if (!i2c_cmd_is_single_byte(cmd)) {
-                fifo_fill = MIN(remaining_bytes, SOC_I2C_FIFO_LEN);
+                fifo_fill = MIN(remaining_bytes, I2C_LL_FIFO_LEN);
                 /* cmd->data shall not be altered!
                  * Else it would not be possible to reuse the commands list. */
                 write_pr = cmd->data + cmd->bytes_used;
@@ -1514,7 +1514,7 @@ static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num, BaseType_t
             break;
         } else if (cmd->hw_cmd.op_code == I2C_LL_CMD_READ) {
             //TODO: to reduce interrupt number
-            fifo_fill = MIN(remaining_bytes, SOC_I2C_FIFO_LEN);
+            fifo_fill = MIN(remaining_bytes, I2C_LL_FIFO_LEN);
             p_i2c->rx_cnt = fifo_fill;
             hw_cmd.byte_num = fifo_fill;
             i2c_ll_master_write_cmd_reg(i2c_context[i2c_num].hal.dev, hw_cmd, p_i2c->cmd_idx);
@@ -1527,7 +1527,7 @@ static void IRAM_ATTR i2c_master_cmd_begin_static(i2c_port_t i2c_num, BaseType_t
         }
         p_i2c->cmd_idx++;
         p_i2c->cmd_link.head = p_i2c->cmd_link.head->next;
-        if (p_i2c->cmd_link.head == NULL || p_i2c->cmd_idx >= (SOC_I2C_CMD_REG_NUM - 1)) {
+        if (p_i2c->cmd_link.head == NULL || p_i2c->cmd_idx >= (I2C_LL_GET(CMD_REG_NUM) - 1)) {
             p_i2c->cmd_idx = 0;
             break;
         }

components/esp_driver_i2c/i2c_master.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,32 +8,24 @@
 #include <inttypes.h>
 #include <sys/param.h>
 #include <sys/lock.h>
-#include "esp_rom_sys.h"
 #include "sdkconfig.h"
-#include "esp_types.h"
-#include "esp_attr.h"
-#include "esp_check.h"
 #if CONFIG_I2C_ENABLE_DEBUG_LOG
 // The local log level must be defined before including esp_log.h
 // Set the maximum log level for this source file
 #define LOG_LOCAL_LEVEL ESP_LOG_VERBOSE
 #endif
+#include "esp_check.h"
+#include "esp_err.h"
 #include "esp_log.h"
-#include "esp_intr_alloc.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/semphr.h"
-#include "hal/i2c_periph.h"
-#include "esp_private/periph_ctrl.h"
-#include "esp_private/esp_clk.h"
-#include "esp_rom_gpio.h"
-#include "driver/i2c_master.h"
-#include "i2c_private.h"
-#include "driver/gpio.h"
-#include "clk_ctrl_os.h"
-#include "hal/i2c_types.h"
-#include "hal/i2c_hal.h"
+#include "esp_heap_caps.h"
 #include "esp_memory_utils.h"
 #include "freertos/idf_additions.h"
+#include "driver/gpio.h"
+#include "soc/soc_caps.h"
+#include "hal/i2c_ll.h"
+#include "hal/i2c_periph.h"
+#include "driver/i2c_master.h"
+#include "i2c_private.h"
 
 static const char *TAG = "i2c.master";
 
@@ -42,9 +34,9 @@ static const char *TAG = "i2c.master";
 #define I2C_ADDRESS_TRANS_READ(device_address)    (((device_address) << 1) | 1)
 
 #if SOC_LP_I2C_SUPPORTED
-#define I2C_FIFO_LEN(port_num) (((port_num) < SOC_HP_I2C_NUM) ? SOC_I2C_FIFO_LEN : SOC_LP_I2C_FIFO_LEN)
+#define I2C_FIFO_LEN(port_num) (((port_num) < SOC_HP_I2C_NUM) ? I2C_LL_GET(FIFO_LEN) : I2C_LL_GET(LP_FIFO_LEN))
 #else
-#define I2C_FIFO_LEN(port_num) (SOC_I2C_FIFO_LEN)
+#define I2C_FIFO_LEN(port_num) (I2C_LL_GET(FIFO_LEN))
 #endif
 
 #define I2C_CLR_BUS_TIMEOUT_MS        (50)  // 50ms is sufficient for clearing the bus
@@ -61,7 +53,7 @@ static i2c_master_bus_platform_t s_platform;
 static esp_err_t s_i2c_master_clear_bus(i2c_bus_handle_t handle)
 {
     esp_err_t ret = ESP_OK;
-#if !SOC_I2C_SUPPORT_HW_CLR_BUS
+#if !I2C_LL_SUPPORT_HW_CLR_BUS
     const int scl_half_period = 5; // use standard 100kHz data rate
     int i = 0;
     gpio_set_direction(handle->scl_num, GPIO_MODE_OUTPUT_OD);
@@ -117,7 +109,7 @@ static esp_err_t s_i2c_hw_fsm_reset(i2c_master_bus_handle_t i2c_master, bool cle
 {
     esp_err_t ret = ESP_OK;
     i2c_hal_context_t *hal = &i2c_master->base->hal;
-#if !SOC_I2C_SUPPORT_HW_FSM_RST
+#if !I2C_LL_SUPPORT_HW_FSM_RST
     i2c_hal_timing_config_t timing_config;
     uint8_t filter_cfg;
 
@@ -1270,12 +1262,12 @@ esp_err_t i2c_master_get_bus_handle(i2c_port_num_t port_num, i2c_master_bus_hand
 esp_err_t i2c_master_multi_buffer_transmit(i2c_master_dev_handle_t i2c_dev, i2c_master_transmit_multi_buffer_info_t *buffer_info_array, size_t array_size, int xfer_timeout_ms)
 {
     ESP_RETURN_ON_FALSE(i2c_dev != NULL, ESP_ERR_INVALID_ARG, TAG, "i2c handle not initialized");
-    ESP_RETURN_ON_FALSE(array_size <= (SOC_I2C_CMD_REG_NUM - 2), ESP_ERR_INVALID_ARG, TAG, "i2c command list cannot contain so many commands");
+    ESP_RETURN_ON_FALSE(array_size <= (I2C_LL_GET(CMD_REG_NUM) - 2), ESP_ERR_INVALID_ARG, TAG, "i2c command list cannot contain so many commands");
     ESP_RETURN_ON_FALSE(buffer_info_array != NULL, ESP_ERR_INVALID_ARG, TAG, "buffer info array is empty");
 
     esp_err_t ret = ESP_OK;
     size_t op_index = 0;
-    i2c_operation_t i2c_ops[SOC_I2C_CMD_REG_NUM] = {};
+    i2c_operation_t i2c_ops[I2C_LL_GET(CMD_REG_NUM)] = {};
     i2c_ops[op_index++].hw_cmd.op_code = I2C_LL_CMD_RESTART;
     for (int i = 0; i < array_size; i++) {
         if (buffer_info_array[i].buffer_size == 0) {
@@ -1442,7 +1434,7 @@ esp_err_t i2c_master_execute_defined_operations(i2c_master_dev_handle_t i2c_dev,
 {
     ESP_RETURN_ON_FALSE(i2c_dev != NULL, ESP_ERR_INVALID_ARG, TAG, "i2c handle not initialized");
     ESP_RETURN_ON_FALSE(i2c_operation != NULL, ESP_ERR_INVALID_ARG, TAG, "i2c operation pointer is invalid");
-    ESP_RETURN_ON_FALSE(operation_list_num <= (SOC_I2C_CMD_REG_NUM), ESP_ERR_INVALID_ARG, TAG, "i2c command list cannot contain so many commands");
+    ESP_RETURN_ON_FALSE(operation_list_num <= (I2C_LL_GET(CMD_REG_NUM)), ESP_ERR_INVALID_ARG, TAG, "i2c command list cannot contain so many commands");
 
     esp_err_t ret = ESP_OK;
     i2c_operation_t i2c_ops[operation_list_num];
@@ -1491,6 +1483,7 @@ esp_err_t i2c_master_execute_defined_operations(i2c_master_dev_handle_t i2c_dev,
 esp_err_t i2c_master_register_event_callbacks(i2c_master_dev_handle_t i2c_dev, const i2c_master_event_callbacks_t *cbs, void *user_data)
 {
     ESP_RETURN_ON_FALSE(i2c_dev != NULL, ESP_ERR_INVALID_ARG, TAG, "i2c handle not initialized");
+    ESP_RETURN_ON_FALSE(cbs != NULL, ESP_ERR_INVALID_ARG, TAG, "callbacks pointer is invalid");
 
     if (i2c_dev->master_bus->async_trans == false) {
         ESP_LOGE(TAG, "I2C transaction queue is not initialized, so you can't use callback here, please resister the bus again with trans_queue_depth != 0");

components/esp_driver_i2c/i2c_private.h

@@ -66,7 +66,7 @@ extern "C" {
 
 #define I2C_ALLOW_INTR_PRIORITY_MASK ESP_INTR_FLAG_LOWMED
 
-#define I2C_STATIC_OPERATION_ARRAY_MAX SOC_I2C_CMD_REG_NUM
+#define I2C_STATIC_OPERATION_ARRAY_MAX I2C_LL_GET(CMD_REG_NUM)
 
 #define I2C_TRANS_READ_COMMAND(ack_value)    {.ack_val = (ack_value), .op_code = I2C_LL_CMD_READ}
 #define I2C_TRANS_WRITE_COMMAND(ack_check)   {.ack_en = (ack_check), .op_code = I2C_LL_CMD_WRITE}

components/esp_driver_i2c/i2c_slave.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -8,27 +8,26 @@
 #include <stdbool.h>
 #include <string.h>
 #include "sdkconfig.h"
-#include "soc/soc_caps.h"
-#include "esp_attr.h"
-#include "esp_rom_gpio.h"
-#include "driver/gpio.h"
-#include "hal/gpio_ll.h"
-#include "esp_err.h"
-#include "freertos/FreeRTOS.h"
-#include "freertos/semphr.h"
-#include "freertos/ringbuf.h"
-#include "esp_intr_alloc.h"
-#include "hal/i2c_ll.h"
-#include "i2c_private.h"
-#include "driver/i2c_slave.h"
-#include "esp_memory_utils.h"
 #if CONFIG_I2C_ENABLE_DEBUG_LOG
 // The local log level must be defined before including esp_log.h
 // Set the maximum log level for this source file
 #define LOG_LOCAL_LEVEL ESP_LOG_DEBUG
 #endif
-#include "esp_log.h"
 #include "esp_check.h"
+#include "esp_err.h"
+#include "esp_log.h"
+#include "esp_intr_alloc.h"
+#include "esp_heap_caps.h"
+#include "esp_memory_utils.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/semphr.h"
+#include "freertos/ringbuf.h"
+#include "driver/gpio.h"
+#include "soc/soc_caps.h"
+#include "hal/i2c_ll.h"
+#include "hal/i2c_periph.h"
+#include "driver/i2c_slave.h"
+#include "i2c_private.h"
 
 static const char *TAG = "i2c.slave";
 
@@ -92,7 +91,7 @@ IRAM_ATTR static bool i2c_slave_handle_tx_fifo(i2c_slave_dev_t *i2c_slave)
 IRAM_ATTR static bool i2c_slave_handle_rx_fifo(i2c_slave_dev_t *i2c_slave, uint32_t len)
 {
     i2c_hal_context_t *hal = &i2c_slave->base->hal;
-    uint8_t data[SOC_I2C_FIFO_LEN];
+    uint8_t data[I2C_LL_GET(FIFO_LEN)];
     BaseType_t xTaskWoken = pdFALSE;
     xSemaphoreTakeFromISR(i2c_slave->operation_mux, &xTaskWoken);
     if (len) {
@@ -316,8 +315,8 @@ esp_err_t i2c_new_slave_device(const i2c_slave_config_t *slave_config, i2c_slave
     i2c_ll_slave_broadcast_enable(hal->dev, slave_config->flags.broadcast_en);
 #endif
 
-    i2c_ll_set_txfifo_empty_thr(hal->dev, SOC_I2C_FIFO_LEN / 2);
-    i2c_ll_set_rxfifo_full_thr(hal->dev, SOC_I2C_FIFO_LEN / 2);
+    i2c_ll_set_txfifo_empty_thr(hal->dev, I2C_LL_GET(FIFO_LEN) / 2);
+    i2c_ll_set_rxfifo_full_thr(hal->dev, I2C_LL_GET(FIFO_LEN) / 2);
     i2c_ll_set_sda_timing(hal->dev, 10, 10);
 
 #if CONFIG_IDF_TARGET_ESP32S3 || CONFIG_IDF_TARGET_ESP32C3
@@ -379,7 +378,7 @@ esp_err_t i2c_slave_write(i2c_slave_dev_handle_t i2c_slave, const uint8_t *data,
     i2c_ll_slave_disable_tx_it(hal->dev);
     uint32_t txfifo_len = 0;
     i2c_ll_get_txfifo_len(hal->dev, &txfifo_len);
-    if (txfifo_len < SOC_I2C_FIFO_LEN) {
+    if (txfifo_len < I2C_LL_GET(FIFO_LEN)) {
         // For the target (esp32) cannot stretch, reset the fifo when there is any dirty data in fifo.
         i2c_ll_txfifo_rst(hal->dev);
     }

components/esp_driver_i2c/include/driver/i2c_types.h

@@ -8,8 +8,8 @@
 
 #include <stdint.h>
 #include <stdbool.h>
-#include "hal/i2c_types.h"
 #include "soc/soc_caps.h"
+#include "hal/i2c_types.h"
 #include "sdkconfig.h"
 
 #ifdef __cplusplus

components/esp_driver_i2c/include/esp_private/i2c_platform.h

@@ -1,22 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-
-#pragma once
-
-#include <stdint.h>
-#include "esp_err.h"
-#include "driver/i2c_types.h"
-#include "hal/gpio_types.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// Empty file in order not cause breaking change. Should be removed in next version.
-
-#ifdef __cplusplus
-}
-#endif

components/esp_hal_i2c/esp32/include/hal/i2c_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,6 +22,11 @@
 extern "C" {
 #endif
 
+#define I2C_LL_GET(_attr)       I2C_LL_ ## _attr
+
+#define I2C_LL_FIFO_LEN         32 /*!< I2C hardware FIFO depth */
+#define I2C_LL_CMD_REG_NUM      16 /*!< Number of I2C command registers */
+
 /**
  * @brief I2C hardware cmd register fields.
  */
@@ -485,7 +490,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
 __attribute__((always_inline))
 static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
 {
-    *length = (hw->status_reg.tx_fifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->status_reg.tx_fifo_cnt);
+    *length = (hw->status_reg.tx_fifo_cnt >= I2C_LL_GET(FIFO_LEN)) ? 0 : (I2C_LL_GET(FIFO_LEN) - hw->status_reg.tx_fifo_cnt);
 }
 
 /**

components/esp_hal_i2c/esp32c2/include/hal/i2c_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -24,6 +24,14 @@
 extern "C" {
 #endif
 
+#define I2C_LL_GET(_attr)       I2C_LL_ ## _attr
+
+#define I2C_LL_FIFO_LEN           16 /*!< I2C hardware FIFO depth */
+#define I2C_LL_CMD_REG_NUM        8  /*!< Number of I2C command registers */
+
+// FSM_RST only resets the FSM, not using it. So I2C_LL_SUPPORT_HW_FSM_RST not defined.
+#define I2C_LL_SUPPORT_HW_CLR_BUS            (1)  /*!< Support hardware clear bus */
+
 /**
  * @brief I2C hardware cmd register fields.
  */
@@ -523,7 +531,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
 __attribute__((always_inline))
 static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
 {
-    *length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
+    *length = (hw->sr.txfifo_cnt >= I2C_LL_GET(FIFO_LEN)) ? 0 : (I2C_LL_GET(FIFO_LEN) - hw->sr.txfifo_cnt);
 }
 
 /**

components/esp_hal_i2c/esp32c3/include/hal/i2c_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -24,6 +24,14 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
+#define I2C_LL_GET(_attr)       I2C_LL_ ## _attr
+
+#define I2C_LL_FIFO_LEN         32 /*!< I2C hardware FIFO depth */
+#define I2C_LL_CMD_REG_NUM      8  /*!< Number of I2C command registers */
+
+// FSM_RST only resets the FSM, not using it. So I2C_LL_SUPPORT_HW_FSM_RST not defined.
+#define I2C_LL_SUPPORT_HW_CLR_BUS            (1)  /*!< Support hardware clear bus */
+// #define I2C_LL_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)  /*!< Slave support I2CRAM access */
 
 /**
  * @brief I2C hardware cmd register fields.
@@ -604,7 +612,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
 __attribute__((always_inline))
 static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
 {
-    *length = SOC_I2C_FIFO_LEN - hw->sr.tx_fifo_cnt;
+    *length = I2C_LL_GET(FIFO_LEN) - hw->sr.tx_fifo_cnt;
 }
 
 /**

components/esp_hal_i2c/esp32c5/include/hal/i2c_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -25,6 +25,15 @@
 #ifdef __cplusplus
 extern "C" {
 #endif
+#define I2C_LL_GET(_attr)       I2C_LL_ ## _attr
+
+#define I2C_LL_FIFO_LEN         32 /*!< I2C hardware FIFO depth */
+#define I2C_LL_LP_FIFO_LEN      16 /*!< LP_I2C hardware FIFO depth */
+#define I2C_LL_CMD_REG_NUM      8  /*!< Number of I2C command registers */
+
+#define I2C_LL_SUPPORT_HW_FSM_RST            (1)  /*!< Support hardware FSM reset */
+// #define I2C_LL_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)  /*!< Slave support I2CRAM access */
+// #define I2C_LL_SLAVE_SUPPORT_SLAVE_UNMATCH   (1)  /*!< Slave support slave unmatch */
 
 /**
  * @brief I2C hardware cmd register fields.
@@ -574,7 +583,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
 __attribute__((always_inline))
 static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
 {
-    *length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
+    *length = (hw->sr.txfifo_cnt >= I2C_LL_GET(FIFO_LEN)) ? 0 : (I2C_LL_GET(FIFO_LEN) - hw->sr.txfifo_cnt);
 }
 
 /**

components/esp_hal_i2c/esp32c6/include/hal/i2c_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -25,6 +25,18 @@
 extern "C" {
 #endif
 
+// ESP32-C6 has 1 I2C
+#define I2C_LL_GET(_attr)       I2C_LL_ ## _attr
+
+#define I2C_LL_FIFO_LEN         32 /*!< I2C hardware FIFO depth */
+#define I2C_LL_LP_FIFO_LEN      16 /*!< LP_I2C hardware FIFO depth */
+#define I2C_LL_CMD_REG_NUM      8  /*!< Number of I2C command registers */
+
+#define I2C_LL_SUPPORT_HW_FSM_RST            (1)  /*!< Support hardware FSM reset */
+#define I2C_LL_SUPPORT_HW_CLR_BUS            (1)  /*!< Support hardware clear bus */
+// #define I2C_LL_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)  /*!< Slave support I2CRAM access */
+// #define I2C_LL_SLAVE_SUPPORT_SLAVE_UNMATCH   (1)  /*!< Slave support slave unmatch */
+
 /**
  * @brief I2C hardware cmd register fields.
  */
@@ -578,7 +590,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
 __attribute__((always_inline))
 static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
 {
-    *length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
+    *length = (hw->sr.txfifo_cnt >= I2C_LL_GET(FIFO_LEN)) ? 0 : (I2C_LL_GET(FIFO_LEN) - hw->sr.txfifo_cnt);
 }
 
 /**

components/esp_hal_i2c/esp32c61/include/hal/i2c_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -26,6 +26,16 @@
 extern "C" {
 #endif
 
+// ESP32-C61 has 1 I2C
+#define I2C_LL_GET(_attr)       I2C_LL_ ## _attr
+
+#define I2C_LL_FIFO_LEN         32 /*!< I2C hardware FIFO depth */
+#define I2C_LL_CMD_REG_NUM      8  /*!< Number of I2C command registers */
+
+#define I2C_LL_SUPPORT_HW_FSM_RST            (1)  /*!< Support hardware FSM reset */
+// #define I2C_LL_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)  /*!< Slave support I2CRAM access */
+// #define I2C_LL_SLAVE_SUPPORT_SLAVE_UNMATCH   (1)  /*!< Slave support slave unmatch */
+
 /**
  * @brief I2C hardware cmd register fields.
  */
@@ -555,7 +565,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
 __attribute__((always_inline))
 static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
 {
-    *length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
+    *length = (hw->sr.txfifo_cnt >= I2C_LL_GET(FIFO_LEN)) ? 0 : (I2C_LL_GET(FIFO_LEN) - hw->sr.txfifo_cnt);
 }
 
 /**

components/esp_hal_i2c/esp32h2/include/hal/i2c_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -23,6 +23,16 @@
 extern "C" {
 #endif
 
+#define I2C_LL_GET(_attr)       I2C_LL_ ## _attr
+
+#define I2C_LL_FIFO_LEN         32 /*!< I2C hardware FIFO depth */
+#define I2C_LL_CMD_REG_NUM      8  /*!< Number of I2C command registers */
+
+#define I2C_LL_SUPPORT_HW_FSM_RST            (1)  /*!< Support hardware FSM reset */
+#define I2C_LL_SUPPORT_HW_CLR_BUS            (1)  /*!< Support hardware clear bus */
+// #define I2C_LL_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)  /*!< Slave support I2CRAM access */
+// #define I2C_LL_SLAVE_SUPPORT_SLAVE_UNMATCH   (1)  /*!< Slave support slave unmatch */
+
 /**
  * @brief I2C hardware cmd register fields.
  */
@@ -551,7 +561,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
 __attribute__((always_inline))
 static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
 {
-    *length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
+    *length = (hw->sr.txfifo_cnt >= I2C_LL_GET(FIFO_LEN)) ? 0 : (I2C_LL_GET(FIFO_LEN) - hw->sr.txfifo_cnt);
 }
 
 /**

components/esp_hal_i2c/esp32h21/include/hal/i2c_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,6 +22,16 @@
 extern "C" {
 #endif
 
+#define I2C_LL_GET(_attr)       I2C_LL_ ## _attr
+
+#define I2C_LL_FIFO_LEN         32 /*!< I2C hardware FIFO depth */
+#define I2C_LL_CMD_REG_NUM      8  /*!< Number of I2C command registers */
+
+#define I2C_LL_SUPPORT_HW_FSM_RST            (1)  /*!< Support hardware FSM reset */
+#define I2C_LL_SUPPORT_HW_CLR_BUS            (1)  /*!< Support hardware clear bus */
+// #define I2C_LL_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)  /*!< Slave support I2CRAM access */
+// #define I2C_LL_SLAVE_SUPPORT_SLAVE_UNMATCH   (1)  /*!< Slave support slave unmatch */
+
 /**
  * @brief I2C hardware cmd register fields.
  */
@@ -551,7 +561,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
 __attribute__((always_inline))
 static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
 {
-    *length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
+    *length = (hw->sr.txfifo_cnt >= I2C_LL_GET(FIFO_LEN)) ? 0 : (I2C_LL_GET(FIFO_LEN) - hw->sr.txfifo_cnt);
 }
 
 /**

components/esp_hal_i2c/esp32h4/include/hal/i2c_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -22,6 +22,16 @@
 extern "C" {
 #endif
 
+#define I2C_LL_GET(_attr)       I2C_LL_ ## _attr
+
+#define I2C_LL_FIFO_LEN         32 /*!< I2C hardware FIFO depth */
+#define I2C_LL_CMD_REG_NUM      8  /*!< Number of I2C command registers */
+
+#define I2C_LL_SUPPORT_HW_FSM_RST            (1)  /*!< Support hardware FSM reset */
+#define I2C_LL_SUPPORT_HW_CLR_BUS            (1)  /*!< Support hardware clear bus */
+// #define I2C_LL_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)  /*!< Slave support I2CRAM access */
+// #define I2C_LL_SLAVE_SUPPORT_SLAVE_UNMATCH   (1)  /*!< Slave support slave unmatch */
+
 /**
  * @brief I2C hardware cmd register fields.
  */
@@ -577,7 +587,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
 __attribute__((always_inline))
 static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
 {
-    *length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
+    *length = (hw->sr.txfifo_cnt >= I2C_LL_GET(FIFO_LEN)) ? 0 : (I2C_LL_GET(FIFO_LEN) - hw->sr.txfifo_cnt);
 }
 
 /**

components/esp_hal_i2c/esp32p4/include/hal/i2c_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -24,6 +24,17 @@
 extern "C" {
 #endif
 
+#define I2C_LL_GET(_attr)       I2C_LL_ ## _attr
+
+#define I2C_LL_FIFO_LEN         32 /*!< I2C hardware FIFO depth */
+#define I2C_LL_LP_FIFO_LEN      16 /*!< LP_I2C hardware FIFO depth */
+#define I2C_LL_CMD_REG_NUM      8  /*!< Number of I2C command registers */
+
+#define I2C_LL_SUPPORT_HW_FSM_RST            (1)  /*!< Support hardware FSM reset */
+#define I2C_LL_SUPPORT_HW_CLR_BUS            (1)  /*!< Support hardware clear bus */
+// #define I2C_LL_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)  /*!< Slave support I2CRAM access */
+// #define I2C_LL_SLAVE_SUPPORT_SLAVE_UNMATCH   (1)  /*!< Slave support slave unmatch */
+
 /**
  * @brief I2C hardware cmd register fields.
  */
@@ -593,7 +604,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
 __attribute__((always_inline))
 static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
 {
-    *length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
+    *length = (hw->sr.txfifo_cnt >= I2C_LL_GET(FIFO_LEN)) ? 0 : (I2C_LL_GET(FIFO_LEN) - hw->sr.txfifo_cnt);
 }
 
 /**

components/esp_hal_i2c/esp32s2/include/hal/i2c_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,6 +21,14 @@
 extern "C" {
 #endif
 
+#define I2C_LL_GET(_attr)       I2C_LL_ ## _attr
+
+#define I2C_LL_FIFO_LEN         32 /*!< I2C hardware FIFO depth */
+#define I2C_LL_CMD_REG_NUM      16 /*!< Number of I2C command registers */
+
+// FSM_RST only resets the FSM, not using it. So I2C_LL_SUPPORT_HW_FSM_RST not defined.
+#define I2C_LL_SUPPORT_HW_CLR_BUS            (1)  /*!< Support hardware clear bus */
+
 /**
  * @brief I2C hardware cmd register fields.
  */
@@ -529,7 +537,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
 __attribute__((always_inline))
 static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
 {
-    *length = (hw->status_reg.tx_fifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->status_reg.tx_fifo_cnt);
+    *length = (hw->status_reg.tx_fifo_cnt >= I2C_LL_GET(FIFO_LEN)) ? 0 : (I2C_LL_GET(FIFO_LEN) - hw->status_reg.tx_fifo_cnt);
 }
 
 /**

components/esp_hal_i2c/esp32s3/include/hal/i2c_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -25,6 +25,15 @@
 extern "C" {
 #endif
 
+#define I2C_LL_GET(_attr)       I2C_LL_ ## _attr
+
+#define I2C_LL_FIFO_LEN         32 /*!< I2C hardware FIFO depth */
+#define I2C_LL_CMD_REG_NUM      8  /*!< Number of I2C command registers */
+
+// FSM_RST only resets the FSM, not using it. So I2C_LL_SUPPORT_HW_FSM_RST not defined.
+#define I2C_LL_SUPPORT_HW_CLR_BUS            (1)  /*!< Support hardware clear bus */
+// #define I2C_LL_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)  /*!< Slave support I2CRAM access */
+
 /**
  * @brief I2C hardware cmd register fields.
  */
@@ -612,7 +621,7 @@ static inline void i2c_ll_get_rxfifo_cnt(i2c_dev_t *hw, uint32_t *length)
 __attribute__((always_inline))
 static inline void i2c_ll_get_txfifo_len(i2c_dev_t *hw, uint32_t *length)
 {
-    *length = (hw->sr.txfifo_cnt >= SOC_I2C_FIFO_LEN) ? 0 : (SOC_I2C_FIFO_LEN - hw->sr.txfifo_cnt);
+    *length = (hw->sr.txfifo_cnt >= I2C_LL_GET(FIFO_LEN)) ? 0 : (I2C_LL_GET(FIFO_LEN) - hw->sr.txfifo_cnt);
 }
 
 /**

components/esp_hal_i2c/i2c_hal.c

@@ -69,7 +69,7 @@ void i2c_hal_master_set_scl_timeout_val(i2c_hal_context_t *hal, uint32_t timeout
     i2c_ll_set_tout(hal->dev, reg_val);
 }
 
-#if !SOC_I2C_SUPPORT_HW_FSM_RST
+#if !I2C_LL_SUPPORT_HW_FSM_RST
 
 void i2c_hal_get_timing_config(i2c_hal_context_t *hal, i2c_hal_timing_config_t *timing_config)
 {
@@ -93,7 +93,7 @@ void i2c_hal_set_timing_config(i2c_hal_context_t *hal, i2c_hal_timing_config_t *
     i2c_ll_master_set_fractional_divider(hal->dev, timing_config->clk_cfg.clk_div.numerator, timing_config->clk_cfg.clk_div.denominator);
 }
 
-#endif // !SOC_I2C_SUPPORT_HW_FSM_RST
+#endif // !I2C_LL_SUPPORT_HW_FSM_RST
 
 void i2c_hal_master_trans_start(i2c_hal_context_t *hal)
 {

components/esp_hal_i2c/include/hal/i2c_hal.h

@@ -179,7 +179,7 @@ void _i2c_hal_deinit(i2c_hal_context_t *hal);
  */
 void i2c_hal_master_trans_start(i2c_hal_context_t *hal);
 
-#if !SOC_I2C_SUPPORT_HW_FSM_RST
+#if !I2C_LL_SUPPORT_HW_FSM_RST
 
 /**
  * @brief Get timing configuration
@@ -197,7 +197,7 @@ void i2c_hal_get_timing_config(i2c_hal_context_t *hal, i2c_hal_timing_config_t *
  */
 void i2c_hal_set_timing_config(i2c_hal_context_t *hal, i2c_hal_timing_config_t *timing_config);
 
-#endif // !SOC_I2C_SUPPORT_HW_FSM_RST
+#endif // !I2C_LL_SUPPORT_HW_FSM_RST
 
 #endif  // #if SOC_I2C_SUPPORTED
 

components/esp_hal_i2c/test_apps/hal_i2c/components/hal_i2c/hal_i2c.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Unlicense OR CC0-1.0
  */
@@ -220,7 +220,7 @@ esp_err_t hal_i2c_write(i2c_port_t port_num, uint16_t addr, const uint8_t *txdat
 
     uint32_t remaining_byte = txlength;
     while (remaining_byte) {
-        uint32_t tx_len_tmp = remaining_byte > SOC_I2C_FIFO_LEN - 1 ? SOC_I2C_FIFO_LEN - 1 : remaining_byte;
+        uint32_t tx_len_tmp = remaining_byte > I2C_LL_GET(FIFO_LEN) - 1 ? I2C_LL_GET(FIFO_LEN) - 1 : remaining_byte;
         i2c_ll_write_txfifo(dev, txdata, tx_len_tmp);
         /*The I2C controller support up to  I2C commands, as such, if we need to enqueue more commands than that,
         we can tell the hardware to start with the enqueued commands first and wait for the next commands to send afterwards.
@@ -262,7 +262,7 @@ esp_err_t hal_i2c_read(i2c_port_t port_num, uint16_t addr, uint8_t *rxdata, uint
     uint32_t remaining_byte = rxlength;
 
     while (remaining_byte) {
-        uint32_t tmp_rx_length = (remaining_byte > SOC_I2C_FIFO_LEN) ? SOC_I2C_FIFO_LEN : remaining_byte;
+        uint32_t tmp_rx_length = (remaining_byte > I2C_LL_GET(FIFO_LEN)) ? I2C_LL_GET(FIFO_LEN) : remaining_byte;
         remaining_byte -= tmp_rx_length;
         if (tmp_rx_length == 1) {
             i2c_format_cmd(port_num, cmd_idx++, I2C_LL_CMD_READ, NACK_VALUE, 0, NOT_CHECK_ACK_VALUE, 1);
@@ -307,7 +307,7 @@ esp_err_t hal_i2c_write_read(i2c_port_t port_num, uint16_t addr, const uint8_t *
     // Write first
     uint32_t remaining_byte = txlength;
     while (remaining_byte) {
-        uint32_t tx_len_tmp = remaining_byte > SOC_I2C_FIFO_LEN - 1 ? SOC_I2C_FIFO_LEN - 1 : remaining_byte;
+        uint32_t tx_len_tmp = remaining_byte > I2C_LL_GET(FIFO_LEN) - 1 ? I2C_LL_GET(FIFO_LEN) - 1 : remaining_byte;
         i2c_ll_write_txfifo(dev, txdata, tx_len_tmp);
         /*The I2C controller support up to  I2C commands, as such, if we need to enqueue more commands than that,
         we can tell the hardware to start with the enqueued commands first and wait for the next commands to send afterwards.
@@ -333,7 +333,7 @@ esp_err_t hal_i2c_write_read(i2c_port_t port_num, uint16_t addr, const uint8_t *
     remaining_byte = rxlength;
 
     while (remaining_byte) {
-        uint32_t tmp_rx_length = (remaining_byte > SOC_I2C_FIFO_LEN) ? SOC_I2C_FIFO_LEN : remaining_byte;
+        uint32_t tmp_rx_length = (remaining_byte > I2C_LL_GET(FIFO_LEN)) ? I2C_LL_GET(FIFO_LEN) : remaining_byte;
         remaining_byte -= tmp_rx_length;
         if (tmp_rx_length == 1) {
             i2c_format_cmd(port_num, cmd_idx++, I2C_LL_CMD_READ, NACK_VALUE, 0, NOT_CHECK_ACK_VALUE, 1);

components/soc/esp32/include/soc/Kconfig.soc_caps.in

@@ -363,18 +363,6 @@ config SOC_HP_I2C_NUM
     int
     default 2
 
-config SOC_I2C_FIFO_LEN
-    int
-    default 32
-
-config SOC_I2C_CMD_REG_NUM
-    int
-    default 16
-
-config SOC_I2C_SUPPORT_SLAVE
-    bool
-    default y
-
 config SOC_I2C_SUPPORT_APB
     bool
     default y
@@ -383,6 +371,10 @@ config SOC_I2C_SUPPORT_10BIT_ADDR
     bool
     default y
 
+config SOC_I2C_SUPPORT_SLAVE
+    bool
+    default y
+
 config SOC_I2C_STOP_INDEPENDENT
     bool
     default y

components/soc/esp32/include/soc/soc_caps.h

@@ -1,6 +1,6 @@
 
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -196,19 +196,16 @@
 #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM  (3)
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32 has 2 I2C
 #define SOC_I2C_NUM                (2U)
-#define SOC_HP_I2C_NUM             (2)
+#define SOC_HP_I2C_NUM             (2U)
 
-#define SOC_I2C_FIFO_LEN        (32) /*!< I2C hardware FIFO depth */
-#define SOC_I2C_CMD_REG_NUM     (16) /*!< Number of I2C command registers */
-#define SOC_I2C_SUPPORT_SLAVE   (1)
-
-#define SOC_I2C_SUPPORT_APB     (1)
+#define SOC_I2C_SUPPORT_APB        (1)
 #define SOC_I2C_SUPPORT_10BIT_ADDR (1)
 
+#define SOC_I2C_SUPPORT_SLAVE      (1)
+
 // On ESP32, the stop bit should be independent, we can't put trans data and stop command together
-#define SOC_I2C_STOP_INDEPENDENT (1)
+#define SOC_I2C_STOP_INDEPENDENT   (1)
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
 // ESP32 has 2 I2S

components/soc/esp32c2/include/soc/Kconfig.soc_caps.in

@@ -327,18 +327,6 @@ config SOC_HP_I2C_NUM
     int
     default 1
 
-config SOC_I2C_FIFO_LEN
-    int
-    default 16
-
-config SOC_I2C_CMD_REG_NUM
-    int
-    default 8
-
-config SOC_I2C_SUPPORT_HW_CLR_BUS
-    bool
-    default y
-
 config SOC_I2C_SUPPORT_XTAL
     bool
     default y

components/soc/esp32c2/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -149,16 +149,9 @@
 #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM       (3)
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32-C2 has 1 I2C
 #define SOC_I2C_NUM                 (1U)
 #define SOC_HP_I2C_NUM              (1U)
 
-#define SOC_I2C_FIFO_LEN            (16) /*!< I2C hardware FIFO depth */
-#define SOC_I2C_CMD_REG_NUM         (8)  /*!< Number of I2C command registers */
-
-// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
-#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
-
 #define SOC_I2C_SUPPORT_XTAL        (1)
 #define SOC_I2C_SUPPORT_RTC         (1)
 #define SOC_I2C_SUPPORT_10BIT_ADDR  (1)

components/soc/esp32c3/include/soc/Kconfig.soc_caps.in

@@ -423,22 +423,6 @@ config SOC_HP_I2C_NUM
     int
     default 1
 
-config SOC_I2C_FIFO_LEN
-    int
-    default 32
-
-config SOC_I2C_CMD_REG_NUM
-    int
-    default 8
-
-config SOC_I2C_SUPPORT_SLAVE
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_CLR_BUS
-    bool
-    default y
-
 config SOC_I2C_SUPPORT_XTAL
     bool
     default y
@@ -451,6 +435,10 @@ config SOC_I2C_SUPPORT_10BIT_ADDR
     bool
     default y
 
+config SOC_I2C_SUPPORT_SLAVE
+    bool
+    default y
+
 config SOC_I2C_SLAVE_SUPPORT_BROADCAST
     bool
     default y
@@ -459,10 +447,6 @@ config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
     bool
     default y
 
-config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
-    bool
-    default y
-
 config SOC_I2S_HW_VERSION_2
     bool
     default y

components/soc/esp32c3/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -188,23 +188,17 @@
 #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM       (3)
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32-C3 has 1 I2C
-#define SOC_I2C_NUM                 (1U)
-#define SOC_HP_I2C_NUM              (1U)
-
-#define SOC_I2C_FIFO_LEN            (32) /*!< I2C hardware FIFO depth */
-#define SOC_I2C_CMD_REG_NUM         (8)  /*!< Number of I2C command registers */
-#define SOC_I2C_SUPPORT_SLAVE       (1)
+#define SOC_I2C_NUM                             (1U)
+#define SOC_HP_I2C_NUM                          (1U)
 
 // FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
-#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
+#define SOC_I2C_SUPPORT_XTAL                    (1)
+#define SOC_I2C_SUPPORT_RTC                     (1)
+#define SOC_I2C_SUPPORT_10BIT_ADDR              (1)
 
-#define SOC_I2C_SUPPORT_XTAL        (1)
-#define SOC_I2C_SUPPORT_RTC         (1)
-#define SOC_I2C_SUPPORT_10BIT_ADDR   (1)
-#define SOC_I2C_SLAVE_SUPPORT_BROADCAST    (1)
-#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE    (1)
-#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)
+#define SOC_I2C_SUPPORT_SLAVE                   (1)
+#define SOC_I2C_SLAVE_SUPPORT_BROADCAST         (1)
+#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE     (1)
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
 #define SOC_I2S_HW_VERSION_2        (1)

components/soc/esp32c5/include/soc/Kconfig.soc_caps.in

@@ -651,21 +651,9 @@ config SOC_HP_I2C_NUM
     int
     default 1
 
-config SOC_I2C_FIFO_LEN
+config SOC_LP_I2C_NUM
     int
-    default 32
-
-config SOC_I2C_CMD_REG_NUM
-    int
-    default 8
-
-config SOC_I2C_SUPPORT_SLAVE
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_FSM_RST
-    bool
-    default y
+    default 1
 
 config SOC_I2C_SUPPORT_XTAL
     bool
@@ -679,6 +667,10 @@ config SOC_I2C_SUPPORT_10BIT_ADDR
     bool
     default y
 
+config SOC_I2C_SUPPORT_SLAVE
+    bool
+    default y
+
 config SOC_I2C_SLAVE_SUPPORT_BROADCAST
     bool
     default y
@@ -687,26 +679,10 @@ config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
     bool
     default y
 
-config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
-    bool
-    default y
-
-config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
-    bool
-    default y
-
 config SOC_I2C_SUPPORT_SLEEP_RETENTION
     bool
     default y
 
-config SOC_LP_I2C_NUM
-    int
-    default 1
-
-config SOC_LP_I2C_FIFO_LEN
-    int
-    default 16
-
 config SOC_I2S_HW_VERSION_2
     bool
     default y

components/soc/esp32c5/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -268,29 +268,19 @@
 #define SOC_ANA_CMPR_SUPPORT_ETM               (1)
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-#define SOC_I2C_NUM                 (2U)
-#define SOC_HP_I2C_NUM              (1U)
+#define SOC_I2C_NUM                             (2U)
+#define SOC_HP_I2C_NUM                          (1U)
+#define SOC_LP_I2C_NUM                          (1U)
 
-#define SOC_I2C_FIFO_LEN            (32) /*!< I2C hardware FIFO depth */
-#define SOC_I2C_CMD_REG_NUM         (8)  /*!< Number of I2C command registers */
-#define SOC_I2C_SUPPORT_SLAVE       (1)
+#define SOC_I2C_SUPPORT_XTAL                    (1)
+#define SOC_I2C_SUPPORT_RTC                     (1)
+#define SOC_I2C_SUPPORT_10BIT_ADDR              (1)
 
-#define SOC_I2C_SUPPORT_HW_FSM_RST  (1)
-#define SOC_I2C_SUPPORT_XTAL        (1)
-#define SOC_I2C_SUPPORT_RTC         (1)
-#define SOC_I2C_SUPPORT_10BIT_ADDR   (1)
-#define SOC_I2C_SLAVE_SUPPORT_BROADCAST    (1)
-#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE    (1)
-#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)
-#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH    (1)
+#define SOC_I2C_SUPPORT_SLAVE                   (1)
+#define SOC_I2C_SLAVE_SUPPORT_BROADCAST         (1)
+#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE     (1)
 
-#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
-
-/*-------------------------- LP_I2C CAPS -------------------------------------*/
-// ESP32-C5 has 1 LP_I2C
-#define SOC_LP_I2C_NUM              (1U)
-
-#define SOC_LP_I2C_FIFO_LEN         (16) /*!< LP_I2C hardware FIFO depth */
+#define SOC_I2C_SUPPORT_SLEEP_RETENTION         (1)
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
 #define SOC_I2S_HW_VERSION_2        (1)

components/soc/esp32c6/include/soc/Kconfig.soc_caps.in

@@ -559,25 +559,9 @@ config SOC_HP_I2C_NUM
     int
     default 1
 
-config SOC_I2C_FIFO_LEN
+config SOC_LP_I2C_NUM
     int
-    default 32
-
-config SOC_I2C_CMD_REG_NUM
-    int
-    default 8
-
-config SOC_I2C_SUPPORT_SLAVE
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_FSM_RST
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_CLR_BUS
-    bool
-    default y
+    default 1
 
 config SOC_I2C_SUPPORT_XTAL
     bool
@@ -591,6 +575,10 @@ config SOC_I2C_SUPPORT_10BIT_ADDR
     bool
     default y
 
+config SOC_I2C_SUPPORT_SLAVE
+    bool
+    default y
+
 config SOC_I2C_SLAVE_SUPPORT_BROADCAST
     bool
     default y
@@ -599,26 +587,10 @@ config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
     bool
     default y
 
-config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
-    bool
-    default y
-
-config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
-    bool
-    default y
-
 config SOC_I2C_SUPPORT_SLEEP_RETENTION
     bool
     default y
 
-config SOC_LP_I2C_NUM
-    int
-    default 1
-
-config SOC_LP_I2C_FIFO_LEN
-    int
-    default 16
-
 config SOC_I2S_HW_VERSION_2
     bool
     default y

components/soc/esp32c6/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -238,31 +238,19 @@
 #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32-C6 has 1 I2C
-#define SOC_I2C_NUM                 (2U) // I2C_NUM = HP_I2C + LP_I2C
-#define SOC_HP_I2C_NUM              (1U)
+#define SOC_I2C_NUM                             (2U)
+#define SOC_HP_I2C_NUM                          (1U)
+#define SOC_LP_I2C_NUM                          (1U)
 
-#define SOC_I2C_FIFO_LEN            (32) /*!< I2C hardware FIFO depth */
-#define SOC_I2C_CMD_REG_NUM         (8)  /*!< Number of I2C command registers */
-#define SOC_I2C_SUPPORT_SLAVE       (1)
+#define SOC_I2C_SUPPORT_XTAL                    (1)
+#define SOC_I2C_SUPPORT_RTC                     (1)
+#define SOC_I2C_SUPPORT_10BIT_ADDR              (1)
 
-#define SOC_I2C_SUPPORT_HW_FSM_RST  (1)
-#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
+#define SOC_I2C_SUPPORT_SLAVE                   (1)
+#define SOC_I2C_SLAVE_SUPPORT_BROADCAST         (1)
+#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE     (1)
 
-#define SOC_I2C_SUPPORT_XTAL        (1)
-#define SOC_I2C_SUPPORT_RTC         (1)
-#define SOC_I2C_SUPPORT_10BIT_ADDR   (1)
-#define SOC_I2C_SLAVE_SUPPORT_BROADCAST    (1)
-#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE    (1)
-#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)
-#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH    (1)
-#define SOC_I2C_SUPPORT_SLEEP_RETENTION           (1)
-
-/*-------------------------- LP_I2C CAPS -------------------------------------*/
-// ESP32-C6 has 1 LP_I2C
-#define SOC_LP_I2C_NUM              (1U)
-
-#define SOC_LP_I2C_FIFO_LEN         (16) /*!< LP_I2C hardware FIFO depth */
+#define SOC_I2C_SUPPORT_SLEEP_RETENTION         (1)
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
 #define SOC_I2S_HW_VERSION_2        (1)

components/soc/esp32c61/include/soc/Kconfig.soc_caps.in

@@ -515,22 +515,6 @@ config SOC_HP_I2C_NUM
     int
     default 1
 
-config SOC_I2C_FIFO_LEN
-    int
-    default 32
-
-config SOC_I2C_CMD_REG_NUM
-    int
-    default 8
-
-config SOC_I2C_SUPPORT_SLAVE
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_FSM_RST
-    bool
-    default y
-
 config SOC_I2C_SUPPORT_XTAL
     bool
     default y
@@ -543,6 +527,10 @@ config SOC_I2C_SUPPORT_10BIT_ADDR
     bool
     default y
 
+config SOC_I2C_SUPPORT_SLAVE
+    bool
+    default y
+
 config SOC_I2C_SLAVE_SUPPORT_BROADCAST
     bool
     default y
@@ -551,14 +539,6 @@ config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
     bool
     default y
 
-config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
-    bool
-    default y
-
-config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
-    bool
-    default y
-
 config SOC_I2C_SUPPORT_SLEEP_RETENTION
     bool
     default y

components/soc/esp32c61/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -220,23 +220,18 @@
 #define SOC_ANA_CMPR_SUPPORT_ETM               (1)
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32-C61 has 1 I2C
-#define SOC_I2C_NUM                 (1U)
-#define SOC_HP_I2C_NUM              (1U)
+#define SOC_I2C_NUM                             (1U)
+#define SOC_HP_I2C_NUM                          (1U)
 
-#define SOC_I2C_FIFO_LEN            (32) /*!< I2C hardware FIFO depth */
-#define SOC_I2C_CMD_REG_NUM         (8)  /*!< Number of I2C command registers */
-#define SOC_I2C_SUPPORT_SLAVE       (1)
+#define SOC_I2C_SUPPORT_XTAL                    (1)
+#define SOC_I2C_SUPPORT_RTC                     (1)
+#define SOC_I2C_SUPPORT_10BIT_ADDR              (1)
 
-#define SOC_I2C_SUPPORT_HW_FSM_RST  (1)
-#define SOC_I2C_SUPPORT_XTAL        (1)
-#define SOC_I2C_SUPPORT_RTC         (1)
-#define SOC_I2C_SUPPORT_10BIT_ADDR   (1)
-#define SOC_I2C_SLAVE_SUPPORT_BROADCAST    (1)
-#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE    (1)
-#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)
-#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH    (1)
-#define SOC_I2C_SUPPORT_SLEEP_RETENTION        (1)
+#define SOC_I2C_SUPPORT_SLAVE                   (1)
+#define SOC_I2C_SLAVE_SUPPORT_BROADCAST         (1)
+#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE     (1)
+
+#define SOC_I2C_SUPPORT_SLEEP_RETENTION         (1)
 
 // /*-------------------------- I2S CAPS ----------------------------------------*/
 #define SOC_I2S_HW_VERSION_2            (1)

components/soc/esp32h2/include/soc/Kconfig.soc_caps.in

@@ -575,26 +575,6 @@ config SOC_HP_I2C_NUM
     int
     default 2
 
-config SOC_I2C_FIFO_LEN
-    int
-    default 32
-
-config SOC_I2C_CMD_REG_NUM
-    int
-    default 8
-
-config SOC_I2C_SUPPORT_SLAVE
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_FSM_RST
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_CLR_BUS
-    bool
-    default y
-
 config SOC_I2C_SUPPORT_XTAL
     bool
     default y
@@ -607,6 +587,10 @@ config SOC_I2C_SUPPORT_10BIT_ADDR
     bool
     default y
 
+config SOC_I2C_SUPPORT_SLAVE
+    bool
+    default y
+
 config SOC_I2C_SLAVE_SUPPORT_BROADCAST
     bool
     default y
@@ -615,14 +599,6 @@ config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
     bool
     default y
 
-config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
-    bool
-    default y
-
-config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
-    bool
-    default y
-
 config SOC_I2C_SUPPORT_SLEEP_RETENTION
     bool
     default y

components/soc/esp32h2/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -262,25 +262,18 @@
 #define SOC_ANA_CMPR_INTR_SHARE_WITH_GPIO   (1)
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32-H2 has 2 I2C
-#define SOC_I2C_NUM                 (2U)
-#define SOC_HP_I2C_NUM              (2U)
+#define SOC_I2C_NUM                             (2U)
+#define SOC_HP_I2C_NUM                          (2U)
 
-#define SOC_I2C_FIFO_LEN            (32) /*!< I2C hardware FIFO depth */
-#define SOC_I2C_CMD_REG_NUM         (8)  /*!< Number of I2C command registers */
-#define SOC_I2C_SUPPORT_SLAVE       (1)
+#define SOC_I2C_SUPPORT_XTAL                    (1)
+#define SOC_I2C_SUPPORT_RTC                     (1)
+#define SOC_I2C_SUPPORT_10BIT_ADDR              (1)
 
-#define SOC_I2C_SUPPORT_HW_FSM_RST  (1)
-#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
+#define SOC_I2C_SUPPORT_SLAVE                   (1)
+#define SOC_I2C_SLAVE_SUPPORT_BROADCAST         (1)
+#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE     (1)
 
-#define SOC_I2C_SUPPORT_XTAL        (1)
-#define SOC_I2C_SUPPORT_RTC         (1)
-#define SOC_I2C_SUPPORT_10BIT_ADDR   (1)
-#define SOC_I2C_SLAVE_SUPPORT_BROADCAST    (1)
-#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE    (1)
-#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)
-#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH    (1)
-#define SOC_I2C_SUPPORT_SLEEP_RETENTION           (1)
+#define SOC_I2C_SUPPORT_SLEEP_RETENTION         (1)
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
 #define SOC_I2S_HW_VERSION_2        (1)

components/soc/esp32h21/include/soc/Kconfig.soc_caps.in

@@ -415,26 +415,6 @@ config SOC_HP_I2C_NUM
     int
     default 2
 
-config SOC_I2C_FIFO_LEN
-    int
-    default 32
-
-config SOC_I2C_CMD_REG_NUM
-    int
-    default 8
-
-config SOC_I2C_SUPPORT_SLAVE
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_FSM_RST
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_CLR_BUS
-    bool
-    default y
-
 config SOC_I2C_SUPPORT_XTAL
     bool
     default y
@@ -447,6 +427,10 @@ config SOC_I2C_SUPPORT_10BIT_ADDR
     bool
     default y
 
+config SOC_I2C_SUPPORT_SLAVE
+    bool
+    default y
+
 config SOC_I2C_SLAVE_SUPPORT_BROADCAST
     bool
     default y
@@ -455,14 +439,6 @@ config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
     bool
     default y
 
-config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
-    bool
-    default y
-
-config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
-    bool
-    default y
-
 config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
     bool
     default y

components/soc/esp32h21/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -242,25 +242,18 @@
 #define SOC_ANA_CMPR_INTR_SHARE_WITH_GPIO   (1)
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32-H21 has 2 I2C
 #define SOC_I2C_NUM                             (2U)
 #define SOC_HP_I2C_NUM                          (2U)
 
-#define SOC_I2C_FIFO_LEN                        (32) /*!< I2C hardware FIFO depth */
-#define SOC_I2C_CMD_REG_NUM                     (8)  /*!< Number of I2C command registers */
-#define SOC_I2C_SUPPORT_SLAVE                   (1)
-
-#define SOC_I2C_SUPPORT_HW_FSM_RST              (1)
-#define SOC_I2C_SUPPORT_HW_CLR_BUS              (1)
-
 #define SOC_I2C_SUPPORT_XTAL                    (1)
 #define SOC_I2C_SUPPORT_RTC                     (1)
 #define SOC_I2C_SUPPORT_10BIT_ADDR              (1)
+
+#define SOC_I2C_SUPPORT_SLAVE                   (1)
 #define SOC_I2C_SLAVE_SUPPORT_BROADCAST         (1)
 #define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE     (1)
-#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS     (1)
-#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH     (1)
-// #define SOC_I2C_SUPPORT_SLEEP_RETENTION           (1)
+
+// #define SOC_I2C_SUPPORT_SLEEP_RETENTION         (1) // TODO: [ESP32H21] IDF-11579
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
 // #define SOC_I2S_HW_VERSION_2        (1)

components/soc/esp32h4/include/soc/Kconfig.soc_caps.in

@@ -391,26 +391,6 @@ config SOC_HP_I2C_NUM
     int
     default 2
 
-config SOC_I2C_FIFO_LEN
-    int
-    default 32
-
-config SOC_I2C_CMD_REG_NUM
-    int
-    default 8
-
-config SOC_I2C_SUPPORT_SLAVE
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_FSM_RST
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_CLR_BUS
-    bool
-    default y
-
 config SOC_I2C_SUPPORT_XTAL
     bool
     default y
@@ -423,6 +403,10 @@ config SOC_I2C_SUPPORT_10BIT_ADDR
     bool
     default y
 
+config SOC_I2C_SUPPORT_SLAVE
+    bool
+    default y
+
 config SOC_I2C_SLAVE_SUPPORT_BROADCAST
     bool
     default y
@@ -431,14 +415,6 @@ config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
     bool
     default y
 
-config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
-    bool
-    default y
-
-config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
-    bool
-    default y
-
 config SOC_I2C_SUPPORT_SLEEP_RETENTION
     bool
     default y

components/soc/esp32h4/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -250,25 +250,18 @@
 #define SOC_ETM_SUPPORT_SLEEP_RETENTION 1
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32-H4 has 2 I2C
-#define SOC_I2C_NUM                 (2U)
-#define SOC_HP_I2C_NUM              (2U)
+#define SOC_I2C_NUM                             (2U)
+#define SOC_HP_I2C_NUM                          (2U)
 
-#define SOC_I2C_FIFO_LEN            (32) /*!< I2C hardware FIFO depth */
-#define SOC_I2C_CMD_REG_NUM         (8)  /*!< Number of I2C command registers */
-#define SOC_I2C_SUPPORT_SLAVE       (1)
+#define SOC_I2C_SUPPORT_XTAL                    (1)
+#define SOC_I2C_SUPPORT_RTC                     (1)
+#define SOC_I2C_SUPPORT_10BIT_ADDR              (1)
 
-#define SOC_I2C_SUPPORT_HW_FSM_RST  (1)
-#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
+#define SOC_I2C_SUPPORT_SLAVE                   (1)
+#define SOC_I2C_SLAVE_SUPPORT_BROADCAST         (1)
+#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE     (1)
 
-#define SOC_I2C_SUPPORT_XTAL        (1)
-#define SOC_I2C_SUPPORT_RTC         (1)
-#define SOC_I2C_SUPPORT_10BIT_ADDR   (1)
-#define SOC_I2C_SLAVE_SUPPORT_BROADCAST    (1)
-#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE    (1)
-#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)
-#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH    (1)
-#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
+#define SOC_I2C_SUPPORT_SLEEP_RETENTION         (1)
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
 #define SOC_I2S_HW_VERSION_2        (1)

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -787,25 +787,9 @@ config SOC_HP_I2C_NUM
     int
     default 2
 
-config SOC_I2C_FIFO_LEN
+config SOC_LP_I2C_NUM
     int
-    default 32
-
-config SOC_I2C_CMD_REG_NUM
-    int
-    default 8
-
-config SOC_I2C_SUPPORT_SLAVE
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_FSM_RST
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_CLR_BUS
-    bool
-    default y
+    default 1
 
 config SOC_I2C_SUPPORT_XTAL
     bool
@@ -819,6 +803,10 @@ config SOC_I2C_SUPPORT_10BIT_ADDR
     bool
     default y
 
+config SOC_I2C_SUPPORT_SLAVE
+    bool
+    default y
+
 config SOC_I2C_SLAVE_SUPPORT_BROADCAST
     bool
     default y
@@ -827,26 +815,10 @@ config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
     bool
     default y
 
-config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
-    bool
-    default y
-
-config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
-    bool
-    default y
-
 config SOC_I2C_SUPPORT_SLEEP_RETENTION
     bool
     default y
 
-config SOC_LP_I2C_NUM
-    int
-    default 1
-
-config SOC_LP_I2C_FIFO_LEN
-    int
-    default 16
-
 config SOC_I2S_HW_VERSION_2
     bool
     default y

components/soc/esp32p4/include/soc/soc_caps.h

@@ -306,32 +306,19 @@
 #define SOC_ANA_CMPR_SUPPORT_ETM               (1)
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32-P4 has 2 I2Cs
-#define SOC_I2C_NUM                 (3U) // I2C_NUM = HP_I2C + LP_I2C
-#define SOC_HP_I2C_NUM              (2U)
+#define SOC_I2C_NUM                             (3U)
+#define SOC_HP_I2C_NUM                          (2U)
+#define SOC_LP_I2C_NUM                          (1U)
 
-#define SOC_I2C_FIFO_LEN            (32) /*!< I2C hardware FIFO depth */
-#define SOC_I2C_CMD_REG_NUM         (8)  /*!< Number of I2C command registers */
-#define SOC_I2C_SUPPORT_SLAVE       (1)
+#define SOC_I2C_SUPPORT_XTAL                    (1)
+#define SOC_I2C_SUPPORT_RTC                     (1)
+#define SOC_I2C_SUPPORT_10BIT_ADDR              (1)
 
-#define SOC_I2C_SUPPORT_HW_FSM_RST  (1)
-#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
+#define SOC_I2C_SUPPORT_SLAVE                   (1)
+#define SOC_I2C_SLAVE_SUPPORT_BROADCAST         (1)
+#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE     (1)
 
-#define SOC_I2C_SUPPORT_XTAL        (1)
-#define SOC_I2C_SUPPORT_RTC         (1)
-#define SOC_I2C_SUPPORT_10BIT_ADDR  (1)
-#define SOC_I2C_SLAVE_SUPPORT_BROADCAST    (1)
-#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE    (1)
-#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)
-#define SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH    (1)
-
-#define SOC_I2C_SUPPORT_SLEEP_RETENTION (1)
-
-/*-------------------------- LP_I2C CAPS -------------------------------------*/
-// ESP32-P4 has 1 LP_I2C
-#define SOC_LP_I2C_NUM              (1U)
-
-#define SOC_LP_I2C_FIFO_LEN         (16) /*!< LP_I2C hardware FIFO depth */
+#define SOC_I2C_SUPPORT_SLEEP_RETENTION         (1)
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
 #define SOC_I2S_HW_VERSION_2        (1)

components/soc/esp32s2/include/soc/Kconfig.soc_caps.in

@@ -419,13 +419,13 @@ config SOC_HP_I2C_NUM
     int
     default 2
 
-config SOC_I2C_FIFO_LEN
-    int
-    default 32
+config SOC_I2C_SUPPORT_REF_TICK
+    bool
+    default y
 
-config SOC_I2C_CMD_REG_NUM
-    int
-    default 16
+config SOC_I2C_SUPPORT_APB
+    bool
+    default y
 
 config SOC_I2C_SUPPORT_SLAVE
     bool
@@ -435,18 +435,6 @@ config SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE
     bool
     default y
 
-config SOC_I2C_SUPPORT_HW_CLR_BUS
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_REF_TICK
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_APB
-    bool
-    default y
-
 config SOC_I2S_HW_VERSION_1
     bool
     default y

components/soc/esp32s2/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -190,21 +190,14 @@
 #define SOC_DEDIC_GPIO_HAS_INTERRUPT    (1) /*!< Dedicated GPIO has its own interrupt source */
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32-S2 has 2 I2C
-#define SOC_I2C_NUM                 (2U)
-#define SOC_HP_I2C_NUM              (2U)
+#define SOC_I2C_NUM                             (2U)
+#define SOC_HP_I2C_NUM                          (2U)
 
-#define SOC_I2C_FIFO_LEN       (32) /*!< I2C hardware FIFO depth */
-#define SOC_I2C_CMD_REG_NUM    (16) /*!< Number of I2C command registers */
-#define SOC_I2C_SUPPORT_SLAVE       (1)
-#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
+#define SOC_I2C_SUPPORT_REF_TICK                (1)
+#define SOC_I2C_SUPPORT_APB                     (1)
 
-// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
-//ESP32-S2 support hardware clear bus
-#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
-
-#define SOC_I2C_SUPPORT_REF_TICK   (1)
-#define SOC_I2C_SUPPORT_APB        (1)
+#define SOC_I2C_SUPPORT_SLAVE                   (1)
+#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE     (1)
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
 // ESP32-S2 has 1 I2S

components/soc/esp32s3/include/soc/Kconfig.soc_caps.in

@@ -479,22 +479,6 @@ config SOC_HP_I2C_NUM
     int
     default 2
 
-config SOC_I2C_FIFO_LEN
-    int
-    default 32
-
-config SOC_I2C_CMD_REG_NUM
-    int
-    default 8
-
-config SOC_I2C_SUPPORT_SLAVE
-    bool
-    default y
-
-config SOC_I2C_SUPPORT_HW_CLR_BUS
-    bool
-    default y
-
 config SOC_I2C_SUPPORT_XTAL
     bool
     default y
@@ -507,11 +491,11 @@ config SOC_I2C_SUPPORT_10BIT_ADDR
     bool
     default y
 
-config SOC_I2C_SLAVE_SUPPORT_BROADCAST
+config SOC_I2C_SUPPORT_SLAVE
     bool
     default y
 
-config SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS
+config SOC_I2C_SLAVE_SUPPORT_BROADCAST
     bool
     default y
 

components/soc/esp32s3/include/soc/soc_caps.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -199,25 +199,16 @@
 #define SOC_GPIO_CLOCKOUT_CHANNEL_NUM  (3)
 
 /*-------------------------- I2C CAPS ----------------------------------------*/
-// ESP32-S3 has 2 I2C
-#define SOC_I2C_NUM                 (2U)
-#define SOC_HP_I2C_NUM              (2U)
+#define SOC_I2C_NUM                             (2U)
+#define SOC_HP_I2C_NUM                          (2U)
 
-#define SOC_I2C_FIFO_LEN       (32) /*!< I2C hardware FIFO depth */
-#define SOC_I2C_CMD_REG_NUM         (8)  /*!< Number of I2C command registers */
-#define SOC_I2C_SUPPORT_SLAVE       (1)
+#define SOC_I2C_SUPPORT_XTAL                    (1)
+#define SOC_I2C_SUPPORT_RTC                     (1)
+#define SOC_I2C_SUPPORT_10BIT_ADDR              (1)
 
-// FSM_RST only resets the FSM, not using it. So SOC_I2C_SUPPORT_HW_FSM_RST not defined.
-//ESP32-S3 support hardware clear bus
-#define SOC_I2C_SUPPORT_HW_CLR_BUS  (1)
-
-#define SOC_I2C_SUPPORT_XTAL       (1)
-#define SOC_I2C_SUPPORT_RTC        (1)
-
-#define SOC_I2C_SUPPORT_10BIT_ADDR  (1)
-#define SOC_I2C_SLAVE_SUPPORT_BROADCAST    (1)
-#define SOC_I2C_SLAVE_SUPPORT_I2CRAM_ACCESS   (1)
-#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE (1)
+#define SOC_I2C_SUPPORT_SLAVE                   (1)
+#define SOC_I2C_SLAVE_SUPPORT_BROADCAST         (1)
+#define SOC_I2C_SLAVE_CAN_GET_STRETCH_CAUSE     (1)
 
 /*-------------------------- I2S CAPS ----------------------------------------*/
 #define SOC_I2S_HW_VERSION_2        (1)

components/ulp/lp_core/lp_core/lp_core_i2c.c

@@ -15,7 +15,7 @@
 
 #if SOC_LP_I2C_SUPPORTED
 
-#define LP_I2C_FIFO_LEN     SOC_LP_I2C_FIFO_LEN
+#define LP_I2C_FIFO_LEN     I2C_LL_GET(LP_FIFO_LEN)
 #define LP_I2C_READ_MODE    I2C_MASTER_READ
 #define LP_I2C_WRITE_MODE   I2C_MASTER_WRITE
 #define LP_I2C_ACK          I2C_MASTER_ACK