Merge branch 'change/added_mspi_str_odd_divider_check_v6.0' into 'release/v6.0'

mspi: added sdr divider check to be not odd divider (v6.0)

See merge request espressif/esp-idf!46869

components/esp_hw_support/mspi_timing_tuning/port/esp32c5/mspi_timing_tuning_configs.h

@@ -9,6 +9,10 @@
 #include "esp_assert.h"
 #include "esp_flash_partitions.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #define MSPI_TIMING_MSPI1_IS_INVOLVED                (CONFIG_ESPTOOLPY_FLASHFREQ_80M || CONFIG_ESPTOOLPY_FLASHFREQ_120M)   //This means esp flash driver needs to be notified
 #define MSPI_TIMING_CONFIG_NUM_MAX                   32  //This should be larger than the max available timing config num
 #define MSPI_TIMING_TEST_DATA_LEN                    128
@@ -100,6 +104,16 @@ ESP_STATIC_ASSERT(MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_FLASH_MO
 #define MSPI_TIMING_CORE_CLOCK_MHZ                   80
 #endif
 
+/**
+ * @note
+ * Limitation 2: SDR mode requires the core clock divider (core_clk / div = module_clk) to be even number or 1.
+ */
+#if MSPI_TIMING_FLASH_STR_MODE
+ESP_STATIC_ASSERT((MSPI_TIMING_CORE_CLOCK_MHZ == MSPI_TIMING_FLASH_MODULE_CLOCK) || (MSPI_TIMING_CORE_CLOCK_MHZ % (2 * MSPI_TIMING_FLASH_MODULE_CLOCK) == 0), "FLASH Mode configuration are not supported");
+#endif
+#if MSPI_TIMING_PSRAM_STR_MODE
+ESP_STATIC_ASSERT((MSPI_TIMING_CORE_CLOCK_MHZ == MSPI_TIMING_PSRAM_MODULE_CLOCK) || (MSPI_TIMING_CORE_CLOCK_MHZ % (2 * MSPI_TIMING_PSRAM_MODULE_CLOCK) == 0), "PSRAM Mode configuration are not supported");
+#endif
 
 //------------------------------------------Helper Macros to get FLASH/PSRAM tuning configs-----------------------------------------------//
 #define __GET_TUNING_CONFIG(type, core_clock, module_clock, mode) \
@@ -135,3 +149,7 @@ ESP_STATIC_ASSERT(MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_FLASH_MO
 #define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE          {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}}
 #define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE            14
 #define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE     4
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/mspi_timing_tuning/port/esp32c61/mspi_timing_tuning_configs.h

@@ -9,6 +9,10 @@
 #include "esp_assert.h"
 #include "esp_flash_partitions.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #define MSPI_TIMING_MSPI1_IS_INVOLVED                CONFIG_ESPTOOLPY_FLASHFREQ_120M   //This means esp flash driver needs to be notified
 #define MSPI_TIMING_CONFIG_NUM_MAX                   32  //This should be larger than the max available timing config num
 #define MSPI_TIMING_TEST_DATA_LEN                    128
@@ -98,6 +102,17 @@ ESP_STATIC_ASSERT(MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_FLASH_MO
 #define MSPI_TIMING_CORE_CLOCK_MHZ                   80
 #endif
 
+/**
+ * @note
+ * Limitation 2: SDR mode requires the core clock divider (core_clk / div = module_clk) to be even number or 1.
+ */
+#if MSPI_TIMING_FLASH_STR_MODE
+ESP_STATIC_ASSERT((MSPI_TIMING_CORE_CLOCK_MHZ == MSPI_TIMING_FLASH_MODULE_CLOCK) || (MSPI_TIMING_CORE_CLOCK_MHZ % (2 * MSPI_TIMING_FLASH_MODULE_CLOCK) == 0), "FLASH Mode configuration are not supported");
+#endif
+#if MSPI_TIMING_PSRAM_STR_MODE
+ESP_STATIC_ASSERT((MSPI_TIMING_CORE_CLOCK_MHZ == MSPI_TIMING_PSRAM_MODULE_CLOCK) || (MSPI_TIMING_CORE_CLOCK_MHZ % (2 * MSPI_TIMING_PSRAM_MODULE_CLOCK) == 0), "PSRAM Mode configuration are not supported");
+#endif
+
 
 //------------------------------------------Helper Macros to get FLASH/PSRAM tuning configs-----------------------------------------------//
 #define __GET_TUNING_CONFIG(type, core_clock, module_clock, mode) \
@@ -133,3 +148,7 @@ ESP_STATIC_ASSERT(MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_FLASH_MO
 #define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE          {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 1}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}}
 #define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE            14
 #define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE     4
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/mspi_timing_tuning/port/esp32p4/mspi_timing_tuning_configs.h

@@ -1,11 +1,16 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 #pragma once
 
 #include "sdkconfig.h"
+#include "esp_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
 
 #define MSPI_TIMING_MSPI1_IS_INVOLVED       CONFIG_ESPTOOLPY_FLASHFREQ_120M   //This means esp flash driver needs to be notified
 #define MSPI_TIMING_CONFIG_NUM_MAX          32  //This should be larger than the max available timing config num
@@ -49,6 +54,14 @@
 #define MSPI_TIMING_FLASH_CORE_CLOCK_MHZ    80
 #endif
 
+/**
+ * @note
+ * Limitation 1: SDR mode requires the core clock divider (core_clk / div = module_clk) to be even number or 1.
+ */
+#if MSPI_TIMING_FLASH_STR_MODE
+ESP_STATIC_ASSERT((MSPI_TIMING_FLASH_CORE_CLOCK_MHZ == MSPI_TIMING_FLASH_MODULE_CLOCK) || (MSPI_TIMING_FLASH_CORE_CLOCK_MHZ % (2 * MSPI_TIMING_FLASH_MODULE_CLOCK) == 0), "FLASH Mode configuration are not supported");
+#endif
+
 //------------------------------------------Helper Macros to get FLASH/PSRAM tuning configs-----------------------------------------------//
 #define __GET_TUNING_CONFIG(type, core_clock, module_clock, mode) \
         (mspi_timing_config_t) { .tuning_config_table = MSPI_TIMING_##type##_CONFIG_TABLE_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \
@@ -66,3 +79,7 @@
 #define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE        {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {2, 1, 3}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {2, 1, 4}}
 #define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE          12
 #define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_120M_MODULE_CLK_120M_STR_MODE   2
+
+#ifdef __cplusplus
+}
+#endif

components/esp_hw_support/mspi_timing_tuning/port/esp32s3/mspi_timing_tuning_configs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2019-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,6 +9,10 @@
 #include "esp_assert.h"
 #include "esp_flash_partitions.h"
 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
 #define MSPI_TIMING_MSPI1_IS_INVOLVED                1   //This means esp flash driver needs to be notified
 #define MSPI_TIMING_CONFIG_NUM_MAX                   20  //This should be larger than the max available timing config num
 #define MSPI_TIMING_TEST_DATA_LEN                    64
@@ -262,3 +266,7 @@ ESP_STATIC_ASSERT(CHECK_POWER_OF_2(MSPI_TIMING_CORE_CLOCK_MHZ / MSPI_TIMING_PSRA
 #define MSPI_TIMING_PLL_FREQ_SCAN_THRESH_MHZ_HIGH                                    520
 #define MSPI_TIMING_PLL_FREQ_SCAN_WIDTH_MHZ                                          160
 #define MSPI_TIMING_PLL_FREQ_SCAN_STEP_MHZ_MODULE_CLK_120M                           8
+
+#ifdef __cplusplus
+}
+#endif