espressif/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2026-04-27 19:13:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

refactor(gpio): remove some useless macros from io_mux_reg.h

Browse Source
This commit is contained in:
Song Ruo Jing
2025-09-26 15:40:33 +08:00
parent ae7962e697
commit c1209fc2ac
18 changed files with 18 additions and 37 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c2.c
+2 -2
View File
@@ -101,10 +101,10 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
if (hd_gpio_num < SOC_GPIO_PIN_COUNT) {
esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
}
if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
if (wp_gpio_num < SOC_GPIO_PIN_COUNT) {
esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
}
}
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c3.c
+2 -2
View File
@@ -112,10 +112,10 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
if (hd_gpio_num < SOC_GPIO_PIN_COUNT) {
esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
}
if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
if (wp_gpio_num < SOC_GPIO_PIN_COUNT) {
esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
}
}
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s2.c
+2 -2
View File
@@ -114,10 +114,10 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
if (hd_gpio_num < SOC_GPIO_PIN_COUNT) {
esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
}
if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
if (wp_gpio_num < SOC_GPIO_PIN_COUNT) {
esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
}
}
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32s3.c
+2 -2
View File
@@ -125,10 +125,10 @@ void IRAM_ATTR bootloader_configure_spi_pins(int drv)
esp_rom_gpio_pad_set_drv(q_gpio_num, drv);
esp_rom_gpio_pad_set_drv(d_gpio_num, drv);
esp_rom_gpio_pad_set_drv(cs0_gpio_num, drv);
if (hd_gpio_num <= MAX_PAD_GPIO_NUM) {
if (hd_gpio_num < SOC_GPIO_PIN_COUNT) {
esp_rom_gpio_pad_set_drv(hd_gpio_num, drv);
}
if (wp_gpio_num <= MAX_PAD_GPIO_NUM) {
if (wp_gpio_num < SOC_GPIO_PIN_COUNT) {
esp_rom_gpio_pad_set_drv(wp_gpio_num, drv);
}
}
components/soc/esp32c2/register/soc/io_mux_reg.h
-3
View File
@@ -123,9 +123,6 @@
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define MAX_RTC_GPIO_NUM 5
#define MAX_PAD_GPIO_NUM 20
#define MAX_GPIO_NUM 24
#define DIG_IO_HOLD_BIT_SHIFT 0
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32c3/register/soc/io_mux_reg.h
+1 -3
View File
@@ -133,9 +133,7 @@
#define USB_INT_PHY0_DM_GPIO_NUM 18
#define USB_INT_PHY0_DP_GPIO_NUM 19
#define MAX_RTC_GPIO_NUM 5
#define MAX_PAD_GPIO_NUM 21
#define MAX_GPIO_NUM 25
#define MAX_RTC_GPIO_NUM 5
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
components/soc/esp32c5/register/soc/io_mux_reg.h
-3
View File
@@ -134,9 +134,6 @@ extern "C" {
#define USB_INT_PHY0_DP_GPIO_NUM 14
#define MAX_RTC_GPIO_NUM 6
#define MAX_PAD_GPIO_NUM 28
#define MAX_GPIO_NUM 32
#define DIG_IO_HOLD_BIT_SHIFT 32
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
// definitions above are inherited from previous version of code, should double check
components/soc/esp32c6/register/soc/io_mux_reg.h
-3
View File
@@ -140,9 +140,6 @@
#define USB_INT_PHY0_DP_GPIO_NUM 13
#define MAX_RTC_GPIO_NUM 7
#define MAX_PAD_GPIO_NUM 30
#define MAX_GPIO_NUM 34
#define DIG_IO_HOLD_BIT_SHIFT 32
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32c61/register/soc/io_mux_reg.h
+1 -2
View File
@@ -110,8 +110,7 @@ extern "C" {
#define USB_INT_PHY0_DP_GPIO_NUM 13
#define MAX_RTC_GPIO_NUM 6
#define MAX_PAD_GPIO_NUM 29
#define MAX_GPIO_NUM 33
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
// definitions above are inherited from previous version of code, should double check
components/soc/esp32h2/register/soc/io_mux_reg.h
-2
View File
@@ -152,8 +152,6 @@
#define USB_INT_PHY0_DP_GPIO_NUM 27
#define MAX_RTC_GPIO_NUM 14 // GPIO7~14 are the pads with LP function
#define MAX_PAD_GPIO_NUM 27
#define MAX_GPIO_NUM 31
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32h21/register/soc/io_mux_reg.h
+1 -2
View File
@@ -145,8 +145,7 @@ extern "C" {
#define USB_INT_PHY0_DP_GPIO_NUM 18
#define MAX_RTC_GPIO_NUM 11 // GPIO5~11 are the pads with LP function
#define MAX_PAD_GPIO_NUM 25
#define MAX_GPIO_NUM 29
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32h4/register/soc/io_mux_reg.h
+1 -2
View File
@@ -138,8 +138,7 @@ extern "C" {
#define USB_OTG_INT_PHY_DP_GPIO_NUM USB_INT_PHY1_DP_GPIO_NUM
#define MAX_RTC_GPIO_NUM 5
#define MAX_PAD_GPIO_NUM 39
#define MAX_GPIO_NUM 39
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
// definitions above are inherited from previous version of code, should double check
components/soc/esp32p4/register/hw_ver1/soc/io_mux_reg.h
-2
View File
@@ -176,8 +176,6 @@
#define USB_OTG_INT_PHY_DP_GPIO_NUM USB_INT_PHY1_DP_GPIO_NUM
#define MAX_RTC_GPIO_NUM 15
#define MAX_PAD_GPIO_NUM 54
#define MAX_GPIO_NUM 56
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32p4/register/hw_ver3/soc/io_mux_reg.h
-2
View File
@@ -176,8 +176,6 @@
#define USB_OTG_INT_PHY_DP_GPIO_NUM USB_INT_PHY1_DP_GPIO_NUM
#define MAX_RTC_GPIO_NUM 15
#define MAX_PAD_GPIO_NUM 54
#define MAX_GPIO_NUM 56
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
components/soc/esp32s2/register/soc/io_mux_reg.h
-2
View File
@@ -144,8 +144,6 @@
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
#define MAX_RTC_GPIO_NUM 21
#define MAX_PAD_GPIO_NUM 46
#define MAX_GPIO_NUM 53
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
components/soc/esp32s3/register/soc/io_mux_reg.h
+2 -3
View File
@@ -154,9 +154,8 @@
#define XTAL32K_P_GPIO_NUM 15
#define XTAL32K_N_GPIO_NUM 16
#define MAX_RTC_GPIO_NUM 21
#define MAX_PAD_GPIO_NUM 48
#define MAX_GPIO_NUM 53
#define MAX_RTC_GPIO_NUM 21
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
docs/en/migration-guides/release-6.x/6.0/peripherals.rst
+2
View File
@@ -115,6 +115,8 @@ GPIO
- ``rom_`` prefix has been added to all GPIO ROM APIs in ``components/esp_rom/esp32xx/include/esp32xx/rom/gpio.h``. For example, :func:`gpio_iomux_in` is now :func:`rom_gpio_iomux_in`.
- ``MAX_PAD_GPIO_NUM``, ``MAX_GPIO_NUM``, and ``DIG_IO_HOLD_BIT_SHIFT`` macros have been removed.
LEDC
----
docs/zh_CN/migration-guides/release-6.x/6.0/peripherals.rst
+2
View File
@@ -115,6 +115,8 @@ GPIO
- ``rom_`` 前缀已添加进 ``components/esp_rom/esp32xx/include/esp32xx/rom/gpio.h`` 中的所有 GPIO ROM API。例如，:func:`gpio_iomux_in` 现在为 :func:`rom_gpio_iomux_in`。
- ``MAX_PAD_GPIO_NUM``、 ``MAX_GPIO_NUM`` 和 ``DIG_IO_HOLD_BIT_SHIFT`` 宏已被移除。
LEDC
----