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Merge branch 'feat/add_esp32c5_eco3_wifi_support_v6.0' into 'release/v6.0'

Browse Source 
Feat(wifi): add full support for esp32c5 v1.2 and esp32c61 v1.1

See merge request espressif/esp-idf!44991
This commit is contained in:
Jiang Jiang Jian
2026-01-12 20:46:24 +08:00
parent 12d0df2537 7089093fde
commit c7d81c24e6
11 changed files with 813 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_coex/lib
+1 -1
Submodule components/esp_coex/lib updated: 63e292b57b...ee5cd79583
components/esp_rom/CMakeLists.txt
+6 -1
View File
@@ -322,6 +322,9 @@ else() # Regular app build
rom_linker_script("coexist")
rom_linker_script("net80211")
rom_linker_script("pp")
if(CONFIG_ESP32C5_REV_MIN_FULL GREATER_EQUAL 102)
rom_linker_script("eco3")
endif()
elseif(target STREQUAL "esp32c61")
# esp32c61.rom.api.ld has been split to several lds by components.
# esp32c61.rom.api.ld is still reserved to map the APIs
@@ -329,9 +332,11 @@ else() # Regular app build
rom_linker_script("coexist")
rom_linker_script("net80211")
rom_linker_script("pp")
if(CONFIG_ESP32C61_REV_MIN_FULL GREATER_EQUAL 101)
rom_linker_script("eco4")
endif()
endif()
if(CONFIG_ESP_ROM_HAS_NEWLIB AND NOT target STREQUAL "esp32" AND NOT target STREQUAL "esp32s2")
# ESP32 and S2 are a bit different, keep them as special cases in the target specific include section
if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410
components/esp_rom/esp32c5/ld/esp32c5.rom.eco3.ld
+405
View File
@@ -0,0 +1,405 @@
/*
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/***************************************
eco3 fixed
***************************************/
coex_core_timer_idx_get = 0x40000aec;
coex_status_get = 0x40000b0c;
ets_delay_us = 0x4000003c;
Cache_Set_IDROM_MMU_Size = 0x400006c4;
//ieee80211_encap_esfbuf = 0x40000b60;
//ieee80211_set_tx_desc = 0x40000b70;
//sta_input = 0x40000bd4;
//sta_rx_eapol = 0x40000bd8;
//sta_reset_beacon_timeout = 0x40000bdc;
hal_mac_tx_set_ppdu = 0x40000c0c;
ic_mac_deinit = 0x40000c78;
ic_mac_init = 0x40000c7c;
lmacTxFrame = 0x40000cd0;
lmacDisableTransmit = 0x40000cd4;
pm_check_state = 0x40000d48;
//pm_set_beacon_filter = 0x40000d6c;
//pm_is_in_wifi_slice_threshold = 0x40000d70;
pm_keep_alive = 0x40000d78;
pm_process_tim = 0x40000da8;
//pm_tbtt_process = 0x40000dbc;
//pm_tx_data_process = 0x40000dd8;
pm_twt_process = 0x40000de8;
//pm_mac_try_enable_modem_state = 0x40000dfc;
//pm_update_next_tbtt = 0x40000e04;
pm_clear_wakeup_signal = 0x40000e0c;
pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000e10;
//pm_mac_disable_tsf_tbtt_modem_wakeup = 0x40000e14;
pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000e18;
//pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000e1c;
//pm_mac_modem_params_rt_update = 0x40000e20;
ppMapTxQueue = 0x40000e64;
//ppProcTxSecFrame = 0x40000e68;
//ppProcessTxQ = 0x40000e70;
ppRxPkt = 0x40000e8c;
ppRxProtoProc = 0x40000e90;
//ppProcessLifeTime = 0x40000ee4;
//rcGetSched = 0x40000f40;
//wDev_ProcessRxSucData = 0x40000fe0;
esp_test_tx_process_complete = 0x40001030;
pm_get_tbtt_count = 0x4000151c;
pm_enable_max_idle_timer = 0x400015b8;
//pm_beacon_offset_check = 0x400015cc;
pm_beacon_offset_get_average = 0x400015d0;
pm_beacon_offset_get_expect = 0x400015d4;
pm_beacon_offset_get_params = 0x400015d8;
phy_rate_to_index = 0x400010e8;
phy_get_target_pwr = 0x400010ec;
phy_get_max_pwr = 0x400010f0;
phy_get_pwr_index = 0x400010f4;
phy_get_rc_dout = 0x400010f8;
phy_rc_cal = 0x400010fc;
phy_abs_temp = 0x40001100;
phy_set_chan_interp = 0x40001104;
phy_loop_clk_en = 0x40001108;
phy_get_data_sat = 0x4000110c;
phy_byte_to_word = 0x40001110;
phy_bb_bss_cbw40 = 0x40001118;
phy_set_chan_reg = 0x4000111c;
phy_i2c_master_reset = 0x40001120;
phy_chan14_mic_enable = 0x40001124;
phy_chan14_mic_cfg = 0x40001128;
phy_set_most_tpw = 0x4000112c;
phy_get_most_tpw = 0x40001130;
phy_tx_state_out = 0x40001134;
phy_ant_dft_cfg = 0x40001138;
phy_ant_wifitx_cfg = 0x4000113c;
phy_ant_wifirx_cfg = 0x40001140;
phy_ant_bttx_cfg = 0x40001144;
phy_ant_btrx_cfg = 0x40001148;
//phy_chan_dump_cfg = 0x4000114c;
phy_chan_dump_cfg_752 = 0x40001150;
phy_enable_low_rate = 0x40001154;
phy_disable_low_rate = 0x40001158;
phy_is_low_rate_enabled = 0x4000115c;
phy_dig_reg_backup = 0x40001160;
phy_chan_filt_set = 0x40001164;
phy_rx11blr_cfg = 0x40001168;
phy_set_cca = 0x4000116c;
phy_set_rx_sense = 0x40001170;
phy_freq_module_resetn = 0x40001174;
phy_freq_chan_en_sw = 0x40001178;
phy_write_chan_freq = 0x4000117c;
phy_get_freq_mem_param = 0x40001180;
phy_get_freq_mem_addr = 0x40001184;
phy_wr_freq_mem = 0x40001188;
phy_read_rf_freq_mem = 0x4000118c;
phy_freq_i2c_mem_write = 0x40001190;
phy_freq_num_get_data = 0x40001194;
phy_freq_i2c_num_addr = 0x40001198;
phy_freq_i2c_write_set = 0x4000119c;
phy_en_hw_set_freq = 0x400011a4;
phy_dis_hw_set_freq = 0x400011a8;
phy_wait_freq_set_busy = 0x400011ac;
phy_i2c_enter_critical_ = 0x400011b0;
phy_i2c_exit_critical_ = 0x400011b4;
phy_i2c_clk_sel = 0x400011b8;
phy_get_i2c_read_mask_ = 0x400011bc;
phy_get_i2c_mst0_mask = 0x400011c0;
phy_get_i2c_hostid_ = 0x400011c4;
phy_chip_i2c_readReg_org = 0x400011c8;
phy_chip_i2c_readReg = 0x400011cc;
phy_i2c_paral_set_mst0 = 0x400011d0;
phy_i2c_paral_set_read = 0x400011d4;
phy_i2c_paral_read = 0x400011d8;
phy_i2c_paral_write = 0x400011dc;
phy_i2c_paral_write_num = 0x400011e0;
phy_i2c_paral_write_mask = 0x400011e4;
phy_i2c_readReg = 0x400011e8;
phy_chip_i2c_writeReg = 0x400011ec;
phy_i2c_writeReg = 0x400011f0;
phy_i2c_readReg_Mask = 0x400011f4;
phy_set_txcap_reg = 0x400011f8;
phy_i2c_sar2_init_code = 0x400011fc;
phy_i2c_pkdet_set = 0x40001200;
phy_filter_dcap_set = 0x40001204;
phy_i2c_rc_cal_set = 0x40001208;
phy_ckgen_5g_cal = 0x4000120c;
phy_ckgen_2g_cal = 0x40001210;
phy_adc_rate_set = 0x40001214;
phy_dac_rate_set = 0x40001218;
phy_encode_i2c_master = 0x4000121c;
phy_i2c_master_fill = 0x40001220;
phy_band_reg = 0x40001224;
phy_open_fe_bb_clk = 0x40001228;
phy_get_mac_addr = 0x4000122c;
phy_set_mac_data = 0x40001230;
phy_rfcal_data_sub = 0x40001234;
phy_rf_cal_data_recovery = 0x40001238;
phy_rf_cal_data_backup = 0x4000123c;
phy_rfcal_data_check = 0x40001240;
phy_pbus_force_mode = 0x40001244;
phy_pbus_force_test = 0x4000124c;
phy_pbus_rd = 0x40001250;
phy_pbus_debugmode = 0x40001254;
phy_pbus_workmode = 0x40001258;
phy_pbus_clear_reg = 0x4000125c;
phy_pbus_set_rxgain = 0x40001260;
phy_pbus_set_dco = 0x40001264;
phy_set_loopback_gain = 0x40001268;
phy_txcal_debuge_mode_ = 0x4000126c;
phy_txcal_work_mode = 0x40001270;
phy_write_pbus_mem = 0x40001274;
phy_set_pbus_mem_2g = 0x40001278;
phy_set_pbus_mem_5g = 0x4000127c;
phy_pbus_reg_store = 0x40001280;
phy_set_pbus_mem = 0x40001284;
phy_get_rx_pbus_freq = 0x40001288;
phy_set_rx_pbus_freq = 0x4000128c;
phy_pbus_xpd_iq_path = 0x40001290;
phy_pbus_set_rftx1_5g = 0x40001294;
phy_pwdet_reg_init = 0x40001298;
phy_pwdet_sar2_init = 0x4000129c;
phy_en_pwdet = 0x400012a0;
phy_get_sar_sig_ref = 0x400012a4;
phy_pwdet_tone_start = 0x400012a8;
phy_get_tone_sar_dout = 0x400012ac;
phy_get_fm_sar_dout = 0x400012b0;
phy_txtone_linear_pwr = 0x400012b4;
phy_linear_to_db = 0x400012b8;
phy_get_power_db = 0x400012bc;
phy_meas_tone_pwr_db = 0x400012c0;
phy_pwdet_wait_idle = 0x400012c4;
phy_pkdet_vol_start = 0x400012c8;
phy_read_sar_dout = 0x400012cc;
phy_read_sar2_code = 0x400012d0;
phy_get_sar2_vol = 0x400012d4;
phy_get_pkdet_data = 0x400012d8;
phy_rx_pkdet_dc_cal = 0x400012dc;
phy_disable_agc = 0x400012e0;
phy_enable_agc = 0x400012e4;
phy_disable_cca = 0x400012e8;
phy_enable_cca = 0x400012ec;
phy_write_gain_mem = 0x400012f0;
phy_bb_bss_cbw40_dig = 0x400012f4;
phy_tx_paon_set = 0x400012f8;
phy_i2cmst_reg_init = 0x400012fc;
phy_bt_gain_offset = 0x40001300;
phy_fe_reg_init = 0x40001304;
phy_mac_enable_bb = 0x40001308;
phy_bb_wdg_cfg = 0x4000130c;
phy_fe_txrx_reset = 0x40001310;
phy_set_rx_comp_ = 0x40001314;
phy_agc_max_gain_set = 0x40001318;
phy_agc_reg_init = 0x4000131c;
phy_bb_reg_init = 0x40001320;
phy_open_i2c_xpd = 0x40001324;
phy_force_txrx_off = 0x40001328;
phy_txiq_set_reg = 0x4000132c;
phy_rxiq_set_reg = 0x40001330;
phy_rx_gain_force = 0x40001334;
phy_set_txclk_en = 0x40001338;
phy_set_rxclk_en = 0x4000133c;
phy_start_tx_tone_step = 0x40001340;
phy_stop_tx_tone = 0x40001344;
phy_bb_wdg_test_en = 0x40001348;
phy_noise_floor_auto_set = 0x4000134c;
phy_read_hw_noisefloor = 0x40001350;
phy_iq_corr_enable = 0x40001354;
phy_wifi_agc_sat_gain = 0x40001358;
phy_bbpll_cal = 0x4000135c;
phy_ant_init = 0x40001360;
phy_wifi_fbw_sel = 0x40001364;
phy_bt_filter_reg = 0x40001368;
phy_rx_sense_set = 0x4000136c;
phy_tx_state_set = 0x40001370;
phy_close_pa = 0x40001374;
phy_freq_correct = 0x40001378;
phy_set_pbus_reg = 0x4000137c;
phy_wifi_rifs_mode_en = 0x40001380;
phy_rfagc_disable = 0x40001384;
phy_pkdadc_set = 0x40001388;
phy_nrx_freq_set = 0x4000138c;
phy_fe_adc_on = 0x40001390;
phy_force_pwr_index = 0x40001394;
phy_fft_scale_force = 0x40001398;
phy_force_rx_gain = 0x4000139c;
phy_wifi_enable_set = 0x400013a0;
phy_bb_cbw_chan_cfg = 0x400013a4;
phy_vht_support = 0x400013a8;
phy_csidump_force_lltf_cfg = 0x400013ac;
phy_hemu_ru26_good_res = 0x400013b0;
phy_bb_cfo_cfg = 0x400013b4;
phy_freq_band_reg_set = 0x400013b8;
phy_set_bb_wdg = 0x400013bc;
phy_sifs_reg_init = 0x400013c0;
phy_bbtx_outfilter = 0x400013c4;
phy_bb_wdt_rst_enable = 0x400013c8;
phy_bb_wdt_int_enable = 0x400013cc;
phy_bb_wdt_timeout_clear = 0x400013d0;
phy_bb_wdt_get_status = 0x400013d4;
phy_freq_to_chan = 0x400013d8;
phy_chan_to_freq = 0x400013dc;
phy_freq_to_index = 0x400013e0;
phy_iq_est_enable = 0x400013e4;
phy_iq_est_disable = 0x400013e8;
phy_dc_iq_est = 0x400013ec;
phy_set_cal_rxdc = 0x400013f0;
phy_rxiq_get_mis = 0x400013f4;
phy_rxiq_cover_mg_mp = 0x400013f8;
phy_rfcal_rxiq = 0x400013fc;
phy_get_rfcal_rxiq_data = 0x40001400;
phy_get_dco_comp = 0x40001404;
phy_pbus_rx_dco_cal = 0x40001408;
phy_rxdc_est_min = 0x4000140c;
phy_rx_dco_cal_1step = 0x40001410;
phy_set_lb_txiq = 0x40001414;
phy_rxiq_opt = 0x40001418;
phy_bb_gain_index = 0x40001430;
phy_rfrx_gain_index = 0x40001434;
phy_gen_rx_gain_table = 0x40001438;
phy_get_rxbb_dc = 0x4000143c;
phy_wr_rx_gain_mem = 0x40001440;
phy_set_tsens_power_ = 0x40001444;
phy_get_tsens_value_ = 0x40001448;
phy_tsens_read_init = 0x4000144c;
phy_code_to_temp = 0x40001450;
phy_tsens_dac_to_index = 0x40001454;
phy_tsens_dac_cal = 0x40001458;
phy_tsens_code_read = 0x4000145c;
phy_tsens_temp_read = 0x40001460;
phy_tsens_temp_read_local = 0x40001464;
phy_temp_to_power_ = 0x40001468;
phy_bt_txdc_cal = 0x4000146c;
phy_bt_txiq_cal = 0x40001470;
phy_txdc_cal = 0x40001474;
phy_txdc_cal_pwdet = 0x40001478;
phy_txiq_get_mis_pwr = 0x4000147c;
phy_txiq_cover = 0x40001480;
phy_rfcal_txiq = 0x40001484;
phy_get_power_atten = 0x40001488;
phy_pwdet_ref_code = 0x4000148c;
phy_pwdet_code_cal = 0x40001490;
phy_rfcal_txcap = 0x40001494;
phy_txcap_setting = 0x40001498;
phy_get_cal_chan = 0x4000149c;
phy_get_chan_cal_index = 0x400014a0;
phy_get_chan_cap = 0x400014a4;
phy_freq_to_mbgain = 0x400014a8;
phy_rfcal_pwrctrl = 0x400014ac;
phy_get_pwdet_offset_ = 0x400014b0;
phy_tx_pwctrl_init_cal = 0x400014b4;
phy_tx_pwctrl_init = 0x400014b8;
phy_bt_tx_pwctrl_init = 0x400014bc;
phy_txbbgain_to_index = 0x400014c0;
phy_index_to_txbbgain = 0x400014c4;
phy_bt_get_tx_gain = 0x400014c8;
phy_dig_gain_check = 0x400014cc;
phy_wifi_get_tx_gain = 0x400014d0;
phy_wifi_11g_rate_chg = 0x400014d4;
phy_set_tx_gain_mem = 0x400014dc;
phy_get_rate_fcc_index = 0x400014e0;
phy_get_chan_target_power = 0x400014e4;
phy_get_tx_gain_value = 0x400014e8;
phy_wifi_get_target_power = 0x400014ec;
phy_wifi_get_tx_tab_ = 0x400014f0;
phy_wifi_set_tx_gain = 0x400014f4;
phy_bt_get_tx_tab_ = 0x400014f8;
phy_bt_set_tx_gain = 0x400014fc;
phy_bt_tx_gain_init = 0x40001500;
/***************************************
eco3 newly added
***************************************/
/* Data (.data, .bss, .rodata) */
s_offchan_tx_progress_in_ptr = 0x4085fc5c;
s_phy_get_max_pwr_new_ptr = 0x4085fc58;
/* Functions */
phy_get_index_pwr = 0x400015dc;
phy_get_pwr_by_rate = 0x400015e0;
phy_set_adc_rand = 0x400015e4;
phy_get_interp_data = 0x400015e8;
phy_pbus_print = 0x400015ec;
phy_internal_delay = 0x400015f0;
phy_ftm_comp = 0x400015f4;
phy_11p_set = 0x400015f8;
phy_freq_mem_backup = 0x400015fc;
phy_get_cca = 0x40001600;
phy_set_cca_cnt = 0x40001604;
phy_get_cca_cnt = 0x40001608;
phy_get_noise_floor = 0x4000160c;
phy_get_rssi = 0x40001610;
phy_rxevm_reset_mem = 0x40001614;
phy_rxevm_init_cfg = 0x40001618;
phy_freq_reg_init = 0x4000161c;
phy_freq_mem_data = 0x40001620;
phy_set_freq_sw_start = 0x40001624;
phy_freq_mem_change_5g_ = 0x40001628;
phy_i2c_bbpll_set = 0x4000162c;
phy_i2c_master_mem_txcap = 0x40001630;
phy_get_xtal_code = 0x40001634;
phy_get_dcap_degen = 0x40001638;
phy_get_vco_init = 0x4000163c;
phy_get_tcode = 0x40001640;
phy_get_tm7 = 0x40001644;
phy_get_dreg_1p1 = 0x40001648;
phy_set_freq_i2c_ = 0x4000164c;
phy_tatget_pwr_band = 0x40001650;
phy_band_i2c_set = 0x40001654;
phy_band_change = 0x40001658;
phy_close_fe_bb_clk = 0x4000165c;
phy_reg_init = 0x40001660;
phy_xpd_rf = 0x40001664;
phy_pbus_rd_addr = 0x40001668;
phy_rx_loop_cap_set = 0x4000166c;
phy_pbus_xpd_dpd_path = 0x40001670;
phy_rx_filter_mode = 0x40001674;
phy_dac_scale_set = 0x40001678;
phy_bbpll_recal = 0x4000167c;
bb_agc_reg_update = 0x40001680;
phy_bb_dcmem_clr = 0x40001684;
phy_txgain_comp_pacfg = 0x40001688;
phy_i2c_txrate_init = 0x4000168c;
phy_iq_swap_set = 0x40001690;
phy_bb_fsm_rst = 0x40001694;
phy_lltf_mask_en = 0x40001698;
phy_magtrk_scale_set = 0x4000169c;
phy_cfg_tx_magtrk = 0x400016a0;
phy_tx_magtrk_init = 0x400016a4;
phy_restart_cal = 0x400016a8;
phy_reset_ckgen = 0x400016ac;
phy_write_rfpll_sdm = 0x400016b0;
phy_rfpll_set_freq = 0x400016b4;
phy_set_rf_freq_offset = 0x400016b8;
phy_i2c_sdm_en = 0x400016bc;
phy_freq_cal_test = 0x400016c0;
phy_set_rfpll_freq = 0x400016c4;
phy_set_channel_rfpll_freq_ = 0x400016c8;
phy_read_pll_cap = 0x400016cc;
//phy_set_chan_misc = 0x400016d0;
phy_chip_set_chan_offset = 0x400016d4;
phy_chip_set_chan_ana = 0x400016d8;
phy_freq_set_reg = 0x400016dc;
phy_rfrx_rxdc_cal = 0x400016e0;
phy_linear_to_db_64bits = 0x400016e4;
phy_get_iq_est_snr = 0x400016e8;
phy_get_loop_snr = 0x400016ec;
phy_get_rx_sig_pwr = 0x400016f0;
phy_adc_rate_cal_rxdc = 0x400016f4;
phy_set_iqcal_ckgen_code = 0x400016f8;
phy_dpd_rxdc_cal = 0x400016fc;
phy_txpwr_correct = 0x40001700;
phy_txpwr_cal_track = 0x40001704;
phy_bt_track_tx_power = 0x40001708;
phy_wifi_track_tx_power = 0x4000170c;
phy_txpwr_track_slow = 0x40001710;
phy_set_tsens_pwr = 0x40001714;
phy_bt_tx_gain_set = 0x40001718;
phy_get_chan_power_offset = 0x4000171c;
phy_chan_vs_index = 0x40001720;
phy_get_txiq_dcode_offset_ = 0x40001724;
phy_get_txiq_set = 0x40001728;
components/esp_rom/esp32c5/ld/esp32c5.rom.net80211.ld
+2 -2
View File
@@ -32,7 +32,7 @@ ic_ebuf_recycle_rx = 0x40000b40;
ic_ebuf_recycle_tx = 0x40000b44;
ic_reset_rx_ba = 0x40000b48;
ic_ebuf_alloc = 0x40000b4c;
ic_reset_extra_softap_rx_ba = 0x40000b50;
//ic_reset_extra_softap_rx_ba = 0x40000b50;
ieee80211_align_eb = 0x40000b54;
ieee80211_ampdu_reorder = 0x40000b58;
ieee80211_ampdu_start_age_timer = 0x40000b5c;
@@ -68,7 +68,7 @@ wifi_is_started = 0x40000bd0;
/*sta_input = 0x40000bd4;*/
//sta_rx_eapol = 0x40000bd8;
//sta_reset_beacon_timeout = 0x40000bdc;
sta_get_beacon_timeout = 0x40000be0;
//sta_get_beacon_timeout = 0x40000be0;
ampdu_process_multicast_address_qos_frame = 0x40000be4;
/* Data (.data, .bss, .rodata) */
net80211_funcs = 0x4085ffac;
components/esp_rom/esp32c5/ld/esp32c5.rom.pp.ld
+4 -4
View File
@@ -117,7 +117,7 @@ pm_local_tsf_process = 0x40000d68;
/*pm_is_in_wifi_slice_threshold = 0x40000d70;*/
pm_is_waked = 0x40000d74;
/*pm_keep_alive = 0x40000d78;*/
pm_on_beacon_rx = 0x40000d7c;
//pm_on_beacon_rx = 0x40000d7c;
pm_on_data_rx = 0x40000d80;
pm_on_data_tx = 0x40000d84;
pm_on_tbtt = 0x40000d88;
@@ -127,9 +127,9 @@ pm_on_isr_set_twt_target = 0x40000d94;
pm_on_isr_twt_wake = 0x40000d98;
pm_on_tsf_timer = 0x40000d9c;
pm_on_twt_force_tx = 0x40000da0;
pm_parse_beacon = 0x40000da4;
//pm_parse_beacon = 0x40000da4;
/*pm_process_tim = 0x40000da8;*/
pm_rx_beacon_process = 0x40000dac;
//pm_rx_beacon_process = 0x40000dac;
pm_rx_data_process = 0x40000db0;
pm_sleep = 0x40000db4;
pm_sleep_for = 0x40000db8;
@@ -204,7 +204,7 @@ ppProcTxDone = 0x40000ec8;
ppMapWaitTxq = 0x40000ecc;
ppProcessWaitingQueue = 0x40000ed0;
ppDisableQueue = 0x40000ed4;
ppCalVHTDeliNum = 0x40000ed8;
//ppCalVHTDeliNum = 0x40000ed8;
ppCalTxVHTSMPDULength = 0x40000edc;
ppCheckTxRTS = 0x40000ee0;
/*ppProcessLifeTime = 0x40000ee4;*/
components/esp_rom/esp32c61/ld/esp32c61.rom.eco4.ld
+370
View File
@@ -0,0 +1,370 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/***************************************
eco4 fixed
***************************************/
coex_core_timer_idx_get = 0x40000a54;
coex_status_get = 0x40000a74;
ets_delay_us = 0x4000003c;
ieee80211_encap_esfbuf = 0x40000ac8;
ieee80211_set_tx_desc = 0x40000ad8;
sta_input = 0x40000b3c;
//sta_rx_eapol = 0x40000b40;
//sta_reset_beacon_timeout = 0x40000b44;
hal_mac_tx_set_ppdu = 0x40000b74;
ic_mac_deinit = 0x40000be8;
ic_mac_init = 0x40000bec;
lmacTxFrame = 0x40000c40;
lmacDisableTransmit = 0x40000c44;
pm_check_state = 0x40000cb4;
pm_set_beacon_filter = 0x40000cd8;
//pm_is_in_wifi_slice_threshold = 0x40000cdc;
pm_keep_alive = 0x40000ce4;
pm_process_tim = 0x40000d14;
pm_tbtt_process = 0x40000d28;
pm_tx_data_process = 0x40000d44;
pm_twt_process = 0x40000d54;
pm_mac_try_enable_modem_state = 0x40000d68;
//pm_update_next_tbtt = 0x40000d70;
pm_clear_wakeup_signal = 0x40000d78;
pm_mac_disable_tsf_tbtt_soc_wakeup = 0x40000d7c;
pm_mac_disable_tsf_tbtt_modem_wakeup = 0x40000d80;
pm_mac_enable_tsf_tbtt_soc_wakeup = 0x40000d84;
pm_mac_enable_tsf_tbtt_modem_wakeup = 0x40000d88;
//pm_mac_modem_params_rt_update = 0x40000d8c;
pm_coex_pwr_update = 0x40000d9c;
ppMapTxQueue = 0x40000ddc;
ppProcTxSecFrame = 0x40000de0;
ppProcessTxQ = 0x40000de8;
ppRxPkt = 0x40000e04;
ppRxProtoProc = 0x40000e08;
//ppProcessLifeTime = 0x40000e54;
rcGetSched = 0x40000eb4;
//wDev_ProcessRxSucData = 0x40000f54;
pm_get_tbtt_count = 0x400014c8;
pm_beacon_offset_check = 0x40001564;
pm_beacon_offset_get_average = 0x40001568;
pm_beacon_offset_get_expect = 0x4000156c;
pm_beacon_offset_get_params = 0x40001570;
pm_enable_max_idle_timer = 0x40001578;
phy_get_rc_dout = 0x40001058;
phy_rc_cal = 0x4000105c;
phy_abs_temp = 0x40001060;
phy_set_chan_cal_interp = 0x40001064;
phy_loopback_mode_en = 0x40001068;
phy_get_data_sat = 0x4000106c;
phy_byte_to_word = 0x40001070;
phy_bb_bss_cbw40 = 0x40001074;
phy_set_chan_reg = 0x40001078;
phy_i2c_master_reset = 0x4000107c;
phy_chan14_mic_enable = 0x40001080;
phy_chan14_mic_cfg = 0x40001084;
phy_freq_module_resetn = 0x40001088;
phy_freq_chan_en_sw = 0x4000108c;
phy_write_chan_freq = 0x40001090;
phy_get_freq_mem_param = 0x40001094;
phy_get_freq_mem_addr = 0x40001098;
phy_wr_rf_freq_mem = 0x4000109c;
phy_read_rf_freq_mem = 0x400010a0;
phy_freq_i2c_mem_write = 0x400010a4;
phy_freq_reg_init = 0x400010a8;
phy_freq_num_get_data = 0x400010ac;
phy_freq_i2c_num_addr = 0x400010b0;
phy_freq_i2c_write_set = 0x400010b4;
phy_pll_dac_mem_update = 0x400010b8;
phy_pll_cap_mem_update = 0x400010bc;
phy_en_hw_set_freq = 0x400010d4;
phy_dis_hw_set_freq = 0x400010d8;
phy_wait_freq_set_busy = 0x400010dc;
phy_set_chan_freq_sw_start = 0x400010e0;
phy_wait_i2c_sdm_stable = 0x400010e4;
phy_reg_init = 0x400010e8;
phy_xpd_rf = 0x400010ec;
phy_get_mac_addr = 0x400010f4;
phy_set_mac_data = 0x400010f8;
phy_rfcal_data_sub = 0x400010fc;
phy_rf_cal_data_recovery = 0x40001100;
phy_rf_cal_data_backup = 0x40001104;
phy_rfcal_data_check = 0x40001108;
phy_pwdet_reg_init = 0x4000110c;
phy_pwdet_sar2_init = 0x40001110;
phy_en_pwdet = 0x40001114;
phy_get_sar_sig_ref = 0x40001118;
phy_pwdet_tone_start = 0x4000111c;
phy_get_tone_sar_dout = 0x40001120;
phy_get_fm_sar_dout = 0x40001124;
phy_txtone_linear_pwr = 0x40001128;
phy_linear_to_db = 0x4000112c;
phy_get_power_db = 0x40001130;
phy_meas_tone_pwr_db = 0x40001134;
phy_pwdet_wait_idle = 0x40001138;
phy_pkdet_vol_start = 0x4000113c;
phy_read_sar_dout = 0x40001140;
phy_read_sar2_code = 0x40001144;
phy_get_sar2_vol = 0x40001148;
phy_get_pll_vol = 0x4000114c;
phy_tx_pwctrl_bg_init = 0x40001150;
phy_set_most_tpw = 0x40001154;
phy_get_most_tpw = 0x40001158;
phy_tx_state_out = 0x4000115c;
phy_ant_dft_cfg = 0x40001160;
phy_ant_wifitx_cfg = 0x40001164;
phy_ant_wifirx_cfg = 0x40001168;
phy_ant_bttx_cfg = 0x4000116c;
phy_ant_btrx_cfg = 0x40001170;
//phy_chan_dump_cfg = 0x40001174;
phy_enable_low_rate = 0x40001178;
phy_disable_low_rate = 0x4000117c;
phy_is_low_rate_enabled = 0x40001180;
phy_dig_reg_backup = 0x40001184;
phy_chan_filt_set = 0x40001188;
phy_rx11blr_cfg = 0x4000118c;
phy_set_cca = 0x40001190;
phy_set_rx_sense = 0x40001194;
phy_rx_gain_force = 0x40001198;
phy_mhz2ieee = 0x4000119c;
phy_chan_to_freq = 0x400011a0;
phy_restart_cal = 0x400011a4;
phy_write_rfpll_sdm = 0x400011a8;
phy_wait_rfpll_cal_end = 0x400011ac;
phy_rfpll_set_freq = 0x400011b0;
phy_set_rf_freq_offset = 0x400011b4;
phy_set_rfpll_freq = 0x400011b8;
phy_set_channel_rfpll_freq = 0x400011bc;
phy_rfpll_cap_correct = 0x400011c0;
phy_rfpll_cap_init_cal = 0x400011c4;
phy_set_freq = 0x400011c8;
phy_write_pll_cap = 0x400011cc;
phy_read_pll_cap = 0x400011d0;
phy_chip_set_chan_misc = 0x400011d4;
phy_freq_set_reg = 0x400011d8;
phy_rfpll_chgp_cal = 0x400011dc;
phy_gen_rx_gain_table = 0x400011e0;
phy_get_rxbb_dc = 0x400011e4;
phy_wr_rx_gain_mem = 0x400011e8;
phy_rfpll_cap_track = 0x400011ec;
phy_txpwr_correct = 0x400011f4;
phy_txpwr_cal_track = 0x400011f8;
phy_bt_track_tx_power = 0x400011fc;
phy_wifi_track_tx_power = 0x40001200;
phy_bt_txdc_cal = 0x40001204;
phy_bt_txiq_cal = 0x40001208;
phy_txdc_cal_pwdet = 0x4000120c;
phy_txdc_cal = 0x40001210;
phy_txiq_get_mis_pwr = 0x40001214;
phy_txiq_cover = 0x40001218;
phy_rfcal_txiq = 0x4000121c;
phy_get_power_atten = 0x40001220;
phy_pwdet_ref_code = 0x40001224;
phy_pwdet_code_cal = 0x40001228;
phy_rfcal_txcap = 0x4000122c;
phy_rfcal_pwrctrl = 0x40001234;
phy_tx_pwctrl_init_cal = 0x40001238;
phy_i2c_enter_critical_ = 0x40001244;
phy_i2c_exit_critical_ = 0x40001248;
phy_i2c_clk_sel = 0x4000124c;
phy_get_i2c_read_mask_ = 0x40001250;
phy_get_i2c_mst0_mask = 0x40001254;
phy_get_i2c_hostid_ = 0x40001258;
phy_chip_i2c_readReg_org = 0x4000125c;
phy_chip_i2c_readReg = 0x40001260;
phy_i2c_paral_set_mst0 = 0x40001264;
phy_i2c_paral_set_read = 0x40001268;
phy_i2c_paral_read = 0x4000126c;
phy_i2c_paral_write = 0x40001270;
phy_i2c_paral_write_num = 0x40001274;
phy_i2c_paral_write_mask = 0x40001278;
phy_i2c_readReg = 0x4000127c;
phy_chip_i2c_writeReg = 0x40001280;
phy_i2c_writeReg = 0x40001284;
phy_i2c_readReg_Mask = 0x40001288;
phy_i2c_writeReg_Mask = 0x4000128c;
phy_set_txcap_reg = 0x40001290;
phy_i2c_sar2_init_code = 0x40001294;
phy_filter_dcap_set = 0x4000129c;
phy_i2c_rc_cal_set = 0x400012ac;
phy_i2c_bbpll_set = 0x400012b0;
phy_adc_rate_set = 0x400012b4;
phy_dac_rate_set = 0x400012b8;
phy_encode_i2c_master = 0x400012bc;
phy_i2c_master_fill = 0x400012c0;
phy_i2c_master_mem_txcap = 0x400012c4;
phy_pbus_force_mode = 0x400012d0;
phy_pbus_rd_addr = 0x400012d4;
phy_pbus_rd_shift = 0x400012d8;
phy_pbus_force_test = 0x400012dc;
phy_pbus_rd = 0x400012e0;
phy_pbus_debugmode = 0x400012e4;
phy_pbus_workmode = 0x400012e8;
phy_pbus_set_rxgain = 0x400012ec;
phy_pbus_xpd_rx_off = 0x400012f0;
phy_pbus_xpd_rx_on = 0x400012f4;
phy_pbus_xpd_tx_off = 0x400012f8;
phy_pbus_xpd_tx_on = 0x400012fc;
phy_pbus_set_dco = 0x40001300;
phy_set_loopback_gain = 0x40001304;
phy_txcal_debuge_mode_ = 0x40001308;
phy_txcal_work_mode = 0x4000130c;
phy_pbus_clear_reg = 0x40001310;
phy_save_pbus_reg = 0x40001314;
phy_write_pbus_mem = 0x40001318;
phy_set_pbus_mem = 0x4000131c;
phy_disable_agc = 0x40001320;
phy_enable_agc = 0x40001324;
phy_disable_cca = 0x40001328;
phy_enable_cca = 0x4000132c;
phy_write_gain_mem = 0x40001330;
phy_bb_bss_cbw40_dig = 0x40001334;
phy_mac_tx_chan_offset = 0x40001338;
phy_rx_11b_opt = 0x4000133c;
phy_tx_paon_set = 0x40001340;
phy_i2cmst_reg_init = 0x40001344;
phy_bt_gain_offset = 0x40001348;
phy_fe_reg_init = 0x4000134c;
phy_mac_enable_bb = 0x40001350;
phy_bb_wdg_cfg = 0x40001354;
phy_fe_txrx_reset = 0x40001358;
phy_set_rx_comp_ = 0x4000135c;
phy_agc_reg_init = 0x40001360;
phy_btbb_wifi_bb_cfg2 = 0x40001364;
phy_bb_reg_init = 0x40001368;
phy_open_i2c_xpd = 0x4000136c;
phy_force_txrx_off = 0x40001370;
phy_txiq_set_reg = 0x40001374;
phy_rxiq_set_reg = 0x40001378;
phy_set_txclk_en = 0x4000137c;
phy_set_rxclk_en = 0x40001380;
phy_start_tx_tone_step = 0x40001384;
phy_stop_tx_tone = 0x40001388;
phy_bb_wdg_test_en = 0x4000138c;
phy_noise_floor_auto_set = 0x40001390;
phy_read_hw_noisefloor = 0x40001394;
phy_iq_corr_enable = 0x40001398;
phy_wifi_agc_sat_gain = 0x4000139c;
phy_bbpll_cal = 0x400013a0;
phy_ant_init = 0x400013a4;
phy_wifi_fbw_sel = 0x400013a8;
phy_bt_filter_reg = 0x400013ac;
phy_rx_sense_set = 0x400013b0;
phy_tx_state_set = 0x400013b4;
phy_close_pa = 0x400013b8;
phy_freq_correct = 0x400013bc;
phy_set_pbus_reg = 0x400013c0;
phy_wifi_rifs_mode_en = 0x400013c4;
phy_nrx_freq_set = 0x400013c8;
phy_fe_adc_on = 0x400013cc;
phy_force_pwr_index = 0x400013d0;
phy_fft_scale_force = 0x400013d4;
phy_force_rx_gain = 0x400013d8;
phy_wifi_enable_set = 0x400013dc;
phy_bb_wdt_rst_enable = 0x400013e0;
phy_bb_wdt_int_enable = 0x400013e4;
phy_bb_wdt_timeout_clear = 0x400013e8;
phy_bb_wdt_get_status = 0x400013ec;
phy_iq_est_enable = 0x400013f0;
phy_iq_est_disable = 0x400013f4;
phy_dc_iq_est = 0x400013f8;
phy_set_cal_rxdc = 0x400013fc;
phy_rxiq_get_mis = 0x40001400;
phy_rxiq_cover_mg_mp = 0x40001404;
phy_rfcal_rxiq = 0x40001408;
phy_get_rfcal_rxiq_data = 0x4000140c;
phy_get_dco_comp = 0x40001410;
phy_pbus_rx_dco_cal = 0x40001414;
phy_rxdc_est_min = 0x40001418;
phy_pbus_rx_dco_cal_1step = 0x4000141c;
phy_get_iq_value = 0x40001420;
phy_set_lb_txiq = 0x40001424;
phy_set_rx_gain_cal_iq = 0x40001428;
phy_set_rx_gain_cal_dc = 0x4000142c;
phy_spur_reg_write_one_tone = 0x40001430;
phy_spur_cal = 0x40001434;
phy_spur_coef_cfg = 0x40001438;
phy_bb_gain_index = 0x4000143c;
phy_rfrx_gain_index = 0x40001440;
phy_set_tsens_power_ = 0x40001444;
phy_set_tsens_range_ = 0x40001448;
phy_get_tsens_value_ = 0x4000144c;
phy_tsens_read_init = 0x40001450;
phy_code_to_temp = 0x40001454;
phy_tsens_dac_to_index = 0x40001458;
phy_tsens_dac_cal = 0x4000145c;
phy_tsens_code_read = 0x40001460;
phy_tsens_temp_read = 0x40001464;
phy_tsens_temp_read_local = 0x40001468;
phy_temp_to_power = 0x4000146c;
phy_txbbgain_to_index = 0x40001470;
phy_index_to_txbbgain = 0x40001474;
phy_bt_index_to_bb = 0x40001478;
phy_bt_bb_to_index = 0x4000147c;
phy_bt_get_tx_gain = 0x40001480;
phy_dig_gain_check = 0x40001484;
phy_wifi_get_tx_gain = 0x40001488;
phy_wifi_11g_rate_chg = 0x4000148c;
phy_set_tx_gain_mem = 0x40001490;
phy_get_rate_fcc_index = 0x40001494;
phy_get_chan_target_power = 0x40001498;
phy_get_tx_gain_value = 0x4000149c;
phy_wifi_get_target_power = 0x400014a0;
phy_wifi_get_tx_tab_ = 0x400014a4;
phy_wifi_set_tx_gain = 0x400014a8;
phy_bt_get_tx_tab_ = 0x400014ac;
phy_bt_set_tx_gain = 0x400014b0;
phy_rate_to_index = 0x400014b8;
phy_get_target_pwr = 0x400014bc;
phy_get_max_pwr = 0x400014c0;
phy_get_pwr_index = 0x400014c4;
phy_chip_set_chan_ana = 0x400014d4;
phy_get_romfuncs = 0x400014d8;
/***************************************
eco4 newly added
***************************************/
/* Data (.data, .bss, .rodata) */
s_offchan_tx_progress_in_ptr = 0x4084fc5c;
/* Functions */
phy_bb_agc_reg_update = 0x4000157c;
phy_bb_cbw_chan_cfg = 0x40001580;
phy_bb_cfo_cfg = 0x40001584;
phy_bb_dcmem_clr = 0x40001588;
phy_bbpll_recal = 0x4000158c;
phy_bbtx_outfilter = 0x40001590;
phy_csidump_force_lltf_cfg = 0x40001594;
phy_dac_scale_set = 0x40001598;
phy_dcode_cal_init = 0x4000159c;
phy_fe_reg_update = 0x400015a0;
phy_freq_band_reg_set = 0x400015a4;
phy_get_cca = 0x400015a8;
phy_get_cca_cnt = 0x400015ac;
phy_get_dreg1p6 = 0x400015b0;
phy_get_noise_floor = 0x400015b4;
phy_get_oc_dr1 = 0x400015b8;
phy_get_rssi = 0x400015bc;
phy_get_rx_sig_pwr = 0x400015c0;
phy_get_txiq_set = 0x400015c4;
phy_get_xtal_duty = 0x400015c8;
phy_hemu_ru26_good_res = 0x400015cc;
phy_i2c_txrate_init = 0x400015d0;
phy_lltf_mask_en = 0x400015d4;
phy_open_fe_bb_clk = 0x400015d8;
phy_reset_ckgen = 0x400015dc;
phy_rx_filter_mode = 0x400015e0;
phy_set_bb_wdg = 0x400015e4;
phy_set_cca_cnt = 0x400015e8;
phy_set_channel_dcode = 0x400015ec;
phy_set_ext_dcode = 0x400015f0;
phy_set_freq_i2c_ = 0x400015f4;
phy_sifs_reg_init = 0x400015f8;
phy_txgain_comp_pacfg = 0x400015fc;
phy_txpwr_track_slow = 0x40001600;
phy_vht_support = 0x40001604;
components/esp_rom/esp32c61/ld/esp32c61.rom.net80211.ld
+2 -2
View File
@@ -28,7 +28,7 @@ ic_ebuf_recycle_rx = 0x40000aa8;
ic_ebuf_recycle_tx = 0x40000aac;
ic_reset_rx_ba = 0x40000ab0;
ic_ebuf_alloc = 0x40000ab4;
ic_reset_extra_softap_rx_ba = 0x40000ab8;
//ic_reset_extra_softap_rx_ba = 0x40000ab8;
ieee80211_align_eb = 0x40000abc;
ieee80211_ampdu_reorder = 0x40000ac0;
ieee80211_ampdu_start_age_timer = 0x40000ac4;
@@ -64,7 +64,7 @@ wifi_is_started = 0x40000b38;
/*sta_input = 0x40000b3c;*/
//sta_rx_eapol = 0x40000b40;
//sta_reset_beacon_timeout = 0x40000b44;
sta_get_beacon_timeout = 0x40000b48;
//sta_get_beacon_timeout = 0x40000b48;
ampdu_process_multicast_address_qos_frame = 0x40000b4c;
/* Data (.data, .bss, .rodata) */
net80211_funcs = 0x4084ffac;
components/esp_wifi/lib
+1 -1
Submodule components/esp_wifi/lib updated: a1f781901a...1955b2abcd
components/esp_wifi/src/wifi_init.c
+18
View File
@@ -722,6 +722,24 @@ void nan_ndp_resp_timeout_process(void *p)
}
#endif /* CONFIG_ESP_WIFI_NAN_SYNC_ENABLE */
#if CONFIG_IDF_TARGET_ESP32C5
#if CONFIG_ESP32C5_REV_MIN_FULL <= 100
void esp32c5_eco3_rom_ptr_init(void)
{
/* Do not remove, stub to overwrite weak link in Wi-Fi Lib */
}
#endif
#endif
#if CONFIG_IDF_TARGET_ESP32C61
#if CONFIG_ESP32C61_REV_MIN_FULL <= 100
void esp32c61_eco4_rom_ptr_init(void)
{
/* Do not remove, stub to overwrite weak link in Wi-Fi Lib */
}
#endif
#endif
#if CONFIG_IDF_TARGET_ESP32C2
#if CONFIG_ESP32C2_REV_MIN_FULL < 200
void esp32c2_eco4_rom_ptr_init(void)
tools/test_apps/system/build_test/sdkconfig.ci.esp32c5_rev102
+2
View File
@@ -0,0 +1,2 @@
CONFIG_IDF_TARGET="esp32c5"
CONFIG_ESP32C5_REV_MIN_102=y
tools/test_apps/system/build_test/sdkconfig.ci.esp32c61_rev101
+2
View File
@@ -0,0 +1,2 @@
CONFIG_IDF_TARGET="esp32c61"
CONFIG_ESP32C61_REV_MIN_101=y