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change(mem): deprecated tcm and added scp memory utils

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This commit is contained in:
armando
2026-03-11 10:40:57 +08:00
parent 261683e6b0
commit c96f69faef
35 changed files with 144 additions and 114 deletions
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components/app_trace/port/riscv/port_jtag.c
+1 -1
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@@ -44,7 +44,7 @@ typedef struct {
const static char *TAG = "esp_apptrace";
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
#define APPTRACE_DRAM_ATTR TCM_DRAM_ATTR
#define APPTRACE_DRAM_ATTR SPM_DRAM_ATTR
#else
#define APPTRACE_DRAM_ATTR
#endif
components/bootloader_support/include/bootloader_memory_utils.h
+18 -6
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@@ -197,19 +197,31 @@ inline static void * esp_ptr_diram_iram_to_dram(const void *p) {
#endif
}
#if SOC_MEM_TCM_SUPPORTED
#if SOC_MEM_SCP_SUPPORTED
/**
* @brief Check if the pointer is in TCM
* @brief Check if the pointer is in TCM (SCP)
*
* @param p pointer
*
* @return true: is in TCM; false: not in TCM
* @return true: is in TCM (SCP); false: not in TCM (SCP)
*/
__attribute__((always_inline))
__attribute__((always_inline, deprecated("esp_ptr_in_tcm is deprecated, please use esp_ptr_in_scp instead")))
inline static bool esp_ptr_in_tcm(const void *p) {
return ((intptr_t)p >= SOC_TCM_LOW && (intptr_t)p < SOC_TCM_HIGH);
return ((intptr_t)p >= SOC_SCP_LOW && (intptr_t)p < SOC_SCP_HIGH);
}
#endif //#if SOC_MEM_TCM_SUPPORTED
/**
* @brief Check if the pointer is in SCP
*
* @param p pointer
*
* @return true: is in SCP; false: not in SCP
*/
__attribute__((always_inline))
inline static bool esp_ptr_in_scp(const void *p) {
return ((intptr_t)p >= SOC_SCP_LOW && (intptr_t)p < SOC_SCP_HIGH);
}
#endif //#if SOC_MEM_SCP_SUPPORTED
/** End of the common section that has to be in sync with esp_memory_utils.h **/
components/bootloader_support/src/esp_image_format.c
+2 -2
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@@ -524,8 +524,8 @@ static bool verify_load_addresses(int segment_index, intptr_t load_addr, intptr_
}
#endif
#if SOC_MEM_TCM_SUPPORTED
else if (esp_ptr_in_tcm(load_addr_p) && esp_ptr_in_tcm(load_inclusive_end_p)) {
#if SOC_MEM_SCP_SUPPORTED
else if (esp_ptr_in_scp(load_addr_p) && esp_ptr_in_scp(load_inclusive_end_p)) {
return true;
}
#endif
components/esp_common/include/esp_attr.h
+11 -6
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@@ -29,14 +29,19 @@ extern "C" {
// Forces data into DRAM instead of flash
#define DRAM_ATTR _SECTION_ATTR_IMPL(".dram1", __COUNTER__)
// Places code into TCM instead of flash
#define TCM_IRAM_ATTR _SECTION_ATTR_IMPL(".tcm.text", __COUNTER__)
// Places code into SCP instead of flash
#define SPM_IRAM_ATTR _SECTION_ATTR_IMPL(".scp.text", __COUNTER__)
// Forces code into TCM instead of flash
#define FORCE_TCM_IRAM_ATTR _SECTION_FORCE_ATTR_IMPL(".tcm.text", __COUNTER__)
// Forces code into SCP instead of flash
#define FORCE_SPM_IRAM_ATTR _SECTION_FORCE_ATTR_IMPL(".scp.text", __COUNTER__)
// Forces data into TCM instead of L2MEM
#define TCM_DRAM_ATTR _SECTION_ATTR_IMPL(".tcm.data", __COUNTER__)
// Forces data into SCP instead of L2MEM
#define SPM_DRAM_ATTR _SECTION_ATTR_IMPL(".scp.data", __COUNTER__)
// Deprecated macros for TCM (SCP)
#define TCM_IRAM_ATTR _SECTION_ATTR_IMPL(".scp.text", __COUNTER__) _Pragma ("GCC warning \"'TCM_IRAM_ATTR' macro is deprecated, please use `SPM_IRAM_ATTR`\"")
#define FORCE_TCM_IRAM_ATTR _SECTION_FORCE_ATTR_IMPL(".scp.text", __COUNTER__) _Pragma ("GCC warning \"'FORCE_TCM_IRAM_ATTR' macro is deprecated, please use `FORCE_SPM_IRAM_ATTR`\"")
#define TCM_DRAM_ATTR _SECTION_ATTR_IMPL(".scp.data", __COUNTER__) _Pragma ("GCC warning \"'TCM_DRAM_ATTR' macro is deprecated, please use `SPM_DRAM_ATTR`\"")
// Forces data to be removed from the final binary but keeps it in the ELF file
#define NOLOAD_ATTR _SECTION_ATTR_IMPL(".noload_keep_in_elf", __COUNTER__)
components/esp_common/soc.lf
+6 -6
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@@ -42,14 +42,14 @@ entries:
entries:
.ext_ram.bss+
[sections:tcm_text]
[sections:scp_text]
entries:
.tcm.text+
.scp.text+
[sections:tcm_data]
[sections:scp_data]
entries:
.tcm.data+
.scp.data+
[sections:tcm_bss]
[sections:scp_bss]
entries:
.tcm.bss+
.scp.bss+
components/esp_driver_dma/src/dma2d.c
+2 -2
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@@ -712,8 +712,8 @@ esp_err_t dma2d_set_desc_addr(dma2d_channel_handle_t dma2d_chan, intptr_t desc_b
{
esp_err_t ret = ESP_OK;
ESP_GOTO_ON_FALSE_ISR(dma2d_chan && desc_base_addr, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
// 2D-DMA descriptor addr needs 8-byte alignment and not in TCM (addr not in TCM is IDF restriction)
ESP_GOTO_ON_FALSE_ISR((desc_base_addr & 0x7) == 0 && !esp_ptr_in_tcm((void *)desc_base_addr), ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
// 2D-DMA descriptor addr needs 8-byte alignment and not in SCP (addr not in SCP is IDF restriction)
ESP_GOTO_ON_FALSE_ISR((desc_base_addr & 0x7) == 0 && !esp_ptr_in_scp((void *)desc_base_addr), ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
// When flash encryption is enabled, the descriptor must be in internal RAM because descriptor size is not 16-byte aligned, which breaks flash encryption alignment restriction
ESP_GOTO_ON_FALSE_ISR(!esp_efuse_is_flash_encryption_enabled() || esp_ptr_internal((void *)desc_base_addr), ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
components/esp_driver_gpio/test_apps/gpio/sdkconfig.defaults.esp32p4
+1 -1
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@@ -1,5 +1,5 @@
CONFIG_SPIRAM=y
CONFIG_SPIRAM_MODE_HEX=y
CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0
# Disable PSRAM halfsleep feature, otherwise P4 tcm section overflows with COMPILER_OPTIMIZATION_NONE=y
# Disable PSRAM halfsleep feature, otherwise P4 scp section overflows with COMPILER_OPTIMIZATION_NONE=y
CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED=n
components/esp_driver_i2s/test_apps/i2s/sdkconfig.defaults.esp32p4
+1 -1
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@@ -1,5 +1,5 @@
CONFIG_SPIRAM=y
CONFIG_SPIRAM_MODE_HEX=y
CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0
# Disable PSRAM halfsleep feature, otherwise P4 tcm section overflows with COMPILER_OPTIMIZATION_NONE=y
# Disable PSRAM halfsleep feature, otherwise P4 scp section overflows with COMPILER_OPTIMIZATION_NONE=y
CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED=n
components/esp_hw_support/esp_memory_utils.c
+2 -2
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@@ -53,8 +53,8 @@ bool esp_ptr_byte_accessible(const void *p)
intptr_t ip = (intptr_t) p;
bool r;
r = (ip >= SOC_BYTE_ACCESSIBLE_LOW && ip < SOC_BYTE_ACCESSIBLE_HIGH);
#if SOC_MEM_TCM_SUPPORTED
r |= esp_ptr_in_tcm(p);
#if SOC_MEM_SCP_SUPPORTED
r |= esp_ptr_in_scp(p);
#endif
#if CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
/* For ESP32 case, RTC fast memory is accessible to PRO cpu only and hence
components/esp_hw_support/include/esp_memory_utils.h
+20 -8
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@@ -196,19 +196,31 @@ inline static void * esp_ptr_diram_iram_to_dram(const void *p) {
#endif
}
#if SOC_MEM_TCM_SUPPORTED
#if SOC_MEM_SCP_SUPPORTED
/**
* @brief Check if the pointer is in TCM
* @brief Check if the pointer is in TCM (SCP)
*
* @param p pointer
*
* @return true: is in TCM; false: not in TCM
* @return true: is in TCM (SCP); false: not in TCM (SCP)
*/
__attribute__((always_inline))
__attribute__((always_inline, deprecated("esp_ptr_in_tcm is deprecated, please use esp_ptr_in_scp instead")))
inline static bool esp_ptr_in_tcm(const void *p) {
return ((intptr_t)p >= SOC_TCM_LOW && (intptr_t)p < SOC_TCM_HIGH);
return ((intptr_t)p >= SOC_SCP_LOW && (intptr_t)p < SOC_SCP_HIGH);
}
#endif //#if SOC_MEM_TCM_SUPPORTED
/**
* @brief Check if the pointer is in SCP
*
* @param p pointer
*
* @return true: is in SCP; false: not in SCP
*/
__attribute__((always_inline))
inline static bool esp_ptr_in_scp(const void *p) {
return ((intptr_t)p >= SOC_SCP_LOW && (intptr_t)p < SOC_SCP_HIGH);
}
#endif //#if SOC_MEM_SCP_SUPPORTED
/** End of common functions to be kept in sync with bootloader_memory_utils.h **/
/** Add app-specific functions below **/
@@ -278,8 +290,8 @@ inline static bool esp_ptr_internal(const void *p) {
bool r;
r = ((intptr_t)p >= SOC_MEM_INTERNAL_LOW && (intptr_t)p < SOC_MEM_INTERNAL_HIGH);
#if SOC_MEM_TCM_SUPPORTED
r |= esp_ptr_in_tcm(p);
#if SOC_MEM_SCP_SUPPORTED
r |= esp_ptr_in_scp(p);
#endif
#if SOC_RTC_SLOW_MEM_SUPPORTED
components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu.c
+12 -12
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@@ -41,14 +41,14 @@
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU && !CONFIG_FREERTOS_UNICORE
static TCM_DRAM_ATTR smp_retention_state_t s_smp_retention_state[portNUM_PROCESSORS];
static SPM_DRAM_ATTR smp_retention_state_t s_smp_retention_state[portNUM_PROCESSORS];
#endif
static bool s_fpu_saved[portNUM_PROCESSORS];
ESP_LOG_ATTR_TAG(TAG, "sleep");
static TCM_DRAM_ATTR __attribute__((unused)) sleep_cpu_retention_t s_cpu_retention;
static SPM_DRAM_ATTR __attribute__((unused)) sleep_cpu_retention_t s_cpu_retention;
extern RvCoreCriticalSleepFrame *rv_core_critical_regs_frame[portNUM_PROCESSORS];
@@ -62,7 +62,7 @@ FORCE_INLINE_ATTR void restore_mstatus(uint32_t mstatus_val)
RV_WRITE_CSR(mstatus, mstatus_val);
}
static TCM_IRAM_ATTR RvCoreNonCriticalSleepFrame * rv_core_noncritical_regs_save(void)
static SPM_IRAM_ATTR RvCoreNonCriticalSleepFrame * rv_core_noncritical_regs_save(void)
{
RvCoreNonCriticalSleepFrame *frame = s_cpu_retention.retent.non_critical_frame[esp_cpu_get_core_id()];
@@ -131,7 +131,7 @@ static TCM_IRAM_ATTR RvCoreNonCriticalSleepFrame * rv_core_noncritical_regs_save
return frame;
}
static TCM_IRAM_ATTR void rv_core_noncritical_regs_restore(void)
static SPM_IRAM_ATTR void rv_core_noncritical_regs_restore(void)
{
RvCoreNonCriticalSleepFrame *frame = s_cpu_retention.retent.non_critical_frame[esp_cpu_get_core_id()];
@@ -198,7 +198,7 @@ static TCM_IRAM_ATTR void rv_core_noncritical_regs_restore(void)
RV_WRITE_CSR(mcycle, frame->mcycle);
}
static TCM_IRAM_ATTR void cpu_domain_dev_regs_save(cpu_domain_dev_sleep_frame_t *frame)
static SPM_IRAM_ATTR void cpu_domain_dev_regs_save(cpu_domain_dev_sleep_frame_t *frame)
{
assert(frame);
cpu_domain_dev_regs_region_t *region = frame->region;
@@ -212,7 +212,7 @@ static TCM_IRAM_ATTR void cpu_domain_dev_regs_save(cpu_domain_dev_sleep_frame_t
}
}
static TCM_IRAM_ATTR void cpu_domain_dev_regs_restore(cpu_domain_dev_sleep_frame_t *frame)
static SPM_IRAM_ATTR void cpu_domain_dev_regs_restore(cpu_domain_dev_sleep_frame_t *frame)
{
assert(frame);
cpu_domain_dev_regs_region_t *region = frame->region;
@@ -227,12 +227,12 @@ static TCM_IRAM_ATTR void cpu_domain_dev_regs_restore(cpu_domain_dev_sleep_frame
}
#if CONFIG_PM_CHECK_SLEEP_RETENTION_FRAME
static TCM_IRAM_ATTR void update_retention_frame_crc(uint32_t *frame_ptr, uint32_t frame_check_size, uint32_t *frame_crc_ptr)
static SPM_IRAM_ATTR void update_retention_frame_crc(uint32_t *frame_ptr, uint32_t frame_check_size, uint32_t *frame_crc_ptr)
{
*(frame_crc_ptr) = esp_rom_crc32_le(0, (void *)frame_ptr, frame_check_size);
}
static TCM_IRAM_ATTR void validate_retention_frame_crc(uint32_t *frame_ptr, uint32_t frame_check_size, uint32_t *frame_crc_ptr)
static SPM_IRAM_ATTR void validate_retention_frame_crc(uint32_t *frame_ptr, uint32_t frame_check_size, uint32_t *frame_crc_ptr)
{
if(*(frame_crc_ptr) != esp_rom_crc32_le(0, (void *)(frame_ptr), frame_check_size)){
// resume uarts
@@ -256,7 +256,7 @@ extern void rv_core_fpu_save(RvCoreCriticalSleepFrame *frame);
extern void rv_core_fpu_restore(RvCoreCriticalSleepFrame *frame);
typedef uint32_t (* sleep_cpu_entry_cb_t)(uint32_t, uint32_t, uint32_t, bool);
static TCM_IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep,
static SPM_IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep,
uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
{
uint8_t core_id = esp_cpu_get_core_id();
@@ -298,7 +298,7 @@ static TCM_IRAM_ATTR esp_err_t do_cpu_retention(sleep_cpu_entry_cb_t goto_sleep,
return reject ? reject : pmu_sleep_finish(dslp);
}
esp_err_t TCM_IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uint32_t, uint32_t, bool),
esp_err_t SPM_IRAM_ATTR esp_sleep_cpu_retention(uint32_t (*goto_sleep)(uint32_t, uint32_t, uint32_t, bool),
uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
{
esp_sleep_execute_event_callbacks(SLEEP_EVENT_SW_CPU_TO_MEM_START, (void *)0);
@@ -383,7 +383,7 @@ esp_err_t sleep_cpu_configure(bool light_sleep_enable)
#if !CONFIG_FREERTOS_UNICORE
#if CONFIG_PM_ESP_SLEEP_POWER_DOWN_CPU
static TCM_IRAM_ATTR void smp_core_do_retention(void)
static SPM_IRAM_ATTR void smp_core_do_retention(void)
{
uint8_t core_id = esp_cpu_get_core_id();
@@ -454,7 +454,7 @@ static TCM_IRAM_ATTR void smp_core_do_retention(void)
}
TCM_IRAM_ATTR void esp_sleep_cpu_skip_retention(void) {
SPM_IRAM_ATTR void esp_sleep_cpu_skip_retention(void) {
atomic_store(&s_smp_retention_state[esp_cpu_get_core_id()], SMP_SKIP_RETENTION);
}
#endif
components/esp_hw_support/lowpower/port/esp32p4/sleep_cpu_asm.S
+2 -2
View File
@@ -14,7 +14,7 @@
#define MTVT (0x307)
#define MINTTHRESH (0x347)
.section .tcm.data,"aw"
.section .scp.data,"aw"
.global rv_core_critical_regs_frame
.type rv_core_critical_regs_frame,@object
.align 4
@@ -33,7 +33,7 @@ rv_core_critical_regs_frame:
--------------------------------------------------------------------------------
*/
.section .tcm.text,"ax"
.section .scp.text,"ax"
.global rv_core_critical_regs_save
.type rv_core_critical_regs_save,@function
.align 4
components/esp_hw_support/lowpower/port/esp32p4/sleep_fpu_asm.S
+1 -1
View File
@@ -8,7 +8,7 @@
#include "freertos/FreeRTOSConfig.h"
#include "sdkconfig.h"
.section .tcm.text,"ax"
.section .scp.text,"ax"
.global rv_core_fpu_save
.type rv_core_fpu_save,@function
.align 4
components/esp_hw_support/port/esp32p4/cpu_region_protect.c
+6 -6
View File
@@ -50,12 +50,12 @@ static void esp_cpu_configure_invalid_regions(void)
// 0. Gap at bottom of address space
PMA_RESET_AND_ENTRY_SET_NAPOT(0, 0, SOC_CPU_SUBSYSTEM_LOW, PMA_NAPOT | PMA_NONE);
// 1. Gap between CPU subsystem region & HP TCM
// 1. Gap between CPU subsystem region & HP SCP
PMA_RESET_AND_ENTRY_SET_TOR(1, SOC_CPU_SUBSYSTEM_HIGH, PMA_NONE);
PMA_RESET_AND_ENTRY_SET_TOR(2, SOC_TCM_LOW, PMA_TOR | PMA_NONE);
PMA_RESET_AND_ENTRY_SET_TOR(2, SOC_SCP_LOW, PMA_TOR | PMA_NONE);
// 2. Gap between HP TCM and CPU Peripherals
PMA_RESET_AND_ENTRY_SET_TOR(3, SOC_TCM_HIGH, PMA_NONE);
// 2. Gap between HP SCP and CPU Peripherals
PMA_RESET_AND_ENTRY_SET_TOR(3, SOC_SCP_HIGH, PMA_NONE);
PMA_RESET_AND_ENTRY_SET_TOR(4, CPU_PERIPH_LOW, PMA_TOR | PMA_NONE);
// 3. Gap between CPU Peripherals and I_Cache
@@ -106,8 +106,8 @@ static void esp_cpu_configure_region_protection_rev_v3(void)
PMP_RESET_AND_ENTRY_SET(0, pmpaddr0, PMP_NAPOT | RW);
_Static_assert(SOC_CPU_SUBSYSTEM_LOW < SOC_CPU_SUBSYSTEM_HIGH, "Invalid CPU subsystem region");
// 2. HP-CPU TCM
// The default memory permissions are RWX and TCM should be RWX, so we can skip configuring it
// 2. HP-CPU SCP
// The default memory permissions are RWX and SCP should be RWX, so we can skip configuring it
// 3. CPU Peripherals
const uint32_t pmpaddr1 = PMPADDR_NAPOT(CPU_PERIPH_LOW, CPU_PERIPH_HIGH);
components/esp_hw_support/port/esp32p4/pmu_init.c
+4 -4
View File
@@ -39,13 +39,13 @@ typedef struct {
const pmu_lp_system_analog_param_t *analog;
} pmu_lp_system_param_t;
pmu_context_t * __attribute__((weak)) TCM_IRAM_ATTR PMU_instance(void)
pmu_context_t * __attribute__((weak)) SPM_IRAM_ATTR PMU_instance(void)
{
/* It should be explicitly defined in the internal RAM, because this
* instance will be used in pmu_sleep.c */
static TCM_DRAM_ATTR pmu_hal_context_t pmu_hal = { .dev = &PMU };
static TCM_DRAM_ATTR pmu_sleep_machine_constant_t pmu_mc = PMU_SLEEP_MC_DEFAULT();
static TCM_DRAM_ATTR pmu_context_t pmu_context = { .hal = &pmu_hal, .mc = (void *)&pmu_mc };
static SPM_DRAM_ATTR pmu_hal_context_t pmu_hal = { .dev = &PMU };
static SPM_DRAM_ATTR pmu_sleep_machine_constant_t pmu_mc = PMU_SLEEP_MC_DEFAULT();
static SPM_DRAM_ATTR pmu_context_t pmu_context = { .hal = &pmu_hal, .mc = (void *)&pmu_mc };
return &pmu_context;
}
components/esp_hw_support/port/esp32p4/pmu_sleep.c
+3 -3
View File
@@ -395,10 +395,10 @@ FORCE_INLINE_ATTR void pmu_sleep_cache_sync_items(uint32_t gid, uint32_t type, u
;
}
static TCM_DRAM_ATTR uint32_t s_mpll_freq_mhz_before_sleep = 0;
static SPM_DRAM_ATTR uint32_t s_mpll_freq_mhz_before_sleep = 0;
__attribute__((optimize("-O2")))
TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
SPM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu, bool dslp)
{
lp_aon_hal_inform_wakeup_type(dslp);
@@ -485,7 +485,7 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
return pmu_sleep_finish(dslp);
}
TCM_IRAM_ATTR bool pmu_sleep_finish(bool dslp)
SPM_IRAM_ATTR bool pmu_sleep_finish(bool dslp)
{
if (dslp) {
pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, HP_CALI_ACTIVE_DCM_VSET_DEFAULT);
components/esp_hw_support/port/esp32p4/rtc_clk.c
+4 -4
View File
@@ -30,7 +30,7 @@ ESP_HW_LOG_ATTR_TAG(TAG, "rtc_clk");
static int s_cur_cpll_freq = 0;
// MPLL frequency option, 400MHz. Zero if MPLL is not enabled.
static TCM_DRAM_ATTR uint32_t s_cur_mpll_freq = 0;
static SPM_DRAM_ATTR uint32_t s_cur_mpll_freq = 0;
void rtc_clk_32k_enable(bool enable)
{
@@ -642,13 +642,13 @@ bool rtc_dig_8m_enabled(void)
}
//------------------------------------MPLL-------------------------------------//
TCM_IRAM_ATTR void rtc_clk_mpll_disable(void)
SPM_IRAM_ATTR void rtc_clk_mpll_disable(void)
{
clk_ll_mpll_disable();
s_cur_mpll_freq = 0;
}
TCM_IRAM_ATTR void rtc_clk_mpll_enable(void)
SPM_IRAM_ATTR void rtc_clk_mpll_enable(void)
{
clk_ll_mpll_enable();
}
@@ -677,7 +677,7 @@ void rtc_clk_mpll_configure(uint32_t xtal_freq, uint32_t mpll_freq, bool thread_
s_cur_mpll_freq = mpll_freq;
}
TCM_IRAM_ATTR uint32_t rtc_clk_mpll_get_freq(void)
SPM_IRAM_ATTR uint32_t rtc_clk_mpll_get_freq(void)
{
return s_cur_mpll_freq;
}
components/esp_hw_support/port/esp32p4/rtc_time.c
+1 -1
View File
@@ -212,7 +212,7 @@ uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
}
TCM_IRAM_ATTR uint64_t rtc_time_get(void)
SPM_IRAM_ATTR uint64_t rtc_time_get(void)
{
return rtc_timer_hal_get_cycle_count(0);
}
components/esp_hw_support/port/esp32s31/rtc_clk.c
+1 -1
View File
@@ -32,7 +32,7 @@ static const char *TAG = "rtc_clk";
static int s_cur_cpll_freq = 0;
// MPLL frequency option, 400MHz. Zero if MPLL is not enabled.
static TCM_DRAM_ATTR uint32_t s_cur_mpll_freq = 0;
static SPM_DRAM_ATTR uint32_t s_cur_mpll_freq = 0;
void rtc_clk_32k_enable(bool enable)
{
components/esp_psram/device/include/esp_private/esp_psram_impl.h
+2 -2
View File
@@ -23,8 +23,8 @@ extern "C" {
#if CONFIG_PM_SLP_SPIRAM_HALFSLEEP_ENABLED
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
#define PSRAM_HALFSLEEP_DATA_ATTR TCM_DRAM_ATTR
#define PSRAM_HALFSLEEP_SLEEP_CODE_ATTR TCM_IRAM_ATTR
#define PSRAM_HALFSLEEP_DATA_ATTR SPM_DRAM_ATTR
#define PSRAM_HALFSLEEP_SLEEP_CODE_ATTR SPM_IRAM_ATTR
#else
#define PSRAM_HALFSLEEP_DATA_ATTR DRAM_ATTR
#define PSRAM_HALFSLEEP_SLEEP_CODE_ATTR IRAM_ATTR
components/esp_system/app.lf
+8 -8
View File
@@ -22,8 +22,8 @@ entries:
rtc_data -> rtc_data
rtc_rodata -> rtc_data
rtc_bss -> rtc_bss
tcm_text -> tcm_text
tcm_data -> tcm_data
scp_text -> scp_text
scp_data -> scp_data
[scheme:rtc]
entries:
@@ -46,13 +46,13 @@ entries:
entries:
text -> iram0_text
[scheme:tcm]
[scheme:scp]
entries:
text -> tcm_text
data -> tcm_data
rodata -> tcm_data
bss -> tcm_bss
common -> tcm_bss
text -> scp_text
data -> scp_data
rodata -> scp_data
bss -> scp_bss
common -> scp_bss
[mapping:default]
archive: *
components/esp_system/ld/esp32p4/memory.ld.in
+2 -2
View File
@@ -46,8 +46,8 @@ MEMORY
* of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
* are connected to the data port of the CPU and eg allow byte-wise access.
*/
/* TCM */
tcm_idram_seg (RX) : org = 0x30100000, len = 0x2000
/* SCP */
scp_idram_seg (RX) : org = 0x30100000, len = 0x2000
#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS
components/esp_system/ld/esp32p4/sections.ld.in
+1 -1
View File
@@ -11,7 +11,7 @@ SECTIONS
{
#include "ld.rtc.sections"
#include "ld.tcm.sections"
#include "ld.scp.sections"
#include "ld.iram.sections"
components/esp_system/ld/ld.scp.sections
+15
View File
@@ -0,0 +1,15 @@
#include "ld.common"
.scp.text :
{
/* Code marked as running out of scp */
_scp_text_start = ABSOLUTE(.);
SECTION_MAPPINGS(scp_text)
_scp_text_end = ABSOLUTE(.);
} > scp_idram_seg
.scp.data :
{
_scp_data_start = ABSOLUTE(.);
SECTION_MAPPINGS(scp_data)
_scp_data_end = ABSOLUTE(.);
} > scp_idram_seg
components/esp_system/ld/ld.tcm.sections
-15
View File
@@ -1,15 +0,0 @@
#include "ld.common"
.tcm.text :
{
/* Code marked as running out of TCM */
_tcm_text_start = ABSOLUTE(.);
SECTION_MAPPINGS(tcm_text)
_tcm_text_end = ABSOLUTE(.);
} > tcm_idram_seg
.tcm.data :
{
_tcm_data_start = ABSOLUTE(.);
SECTION_MAPPINGS(tcm_data)
_tcm_data_end = ABSOLUTE(.);
} > tcm_idram_seg
components/hal/esp32p4/include/hal/lp_clkrst_ll.h
+2 -2
View File
@@ -21,8 +21,8 @@ extern "C" {
/**
* Select CPU reset vector
* @param boot_from_lp_ram
* true: boot from LP TCM RAM: 0x50108000
* false: boot from HP TCM ROM: 0x4FC00000
* true: boot from LP SCP RAM: 0x50108000
* false: boot from HP SCP ROM: 0x4FC00000
*/
__attribute__((always_inline))
static inline void lp_clkrst_ll_boot_from_lp_ram(bool boot_from_lp_ram)
components/heap/include/esp_heap_caps.h
+2 -1
View File
@@ -44,7 +44,8 @@ extern "C" {
#define MALLOC_CAP_IRAM_8BIT (1<<13) ///< Memory must be in IRAM and allow unaligned access
#define MALLOC_CAP_RETENTION (1<<14) ///< Memory must be able to accessed by retention DMA
#define MALLOC_CAP_RTCRAM (1<<15) ///< Memory must be in RTC fast memory
#define MALLOC_CAP_TCM (1<<16) ///< Memory must be in TCM memory
#define MALLOC_CAP_SCP (1<<16) ///< Memory must be in SCP memory
#define MALLOC_CAP_TCM MALLOC_CAP_SCP _Pragma ("GCC warning \"'MALLOC_CAP_TCM' macro is deprecated, please use `MALLOC_CAP_SCP`\"")
#define MALLOC_CAP_DMA_DESC_AHB (1<<17) ///< Memory must be capable of containing AHB DMA descriptors
#define MALLOC_CAP_DMA_DESC_AXI (1<<18) ///< Memory must be capable of containing AXI DMA descriptors
#define MALLOC_CAP_CACHE_ALIGNED (1<<19) ///< Memory must be aligned to the cache line size of any intermediate caches
components/heap/port/esp32p4/memory_layout.c
+6 -6
View File
@@ -36,7 +36,7 @@ enum {
*/
SOC_MEMORY_TYPE_RETENT_MEM = 1,
SOC_MEMORY_TYPE_SPIRAM = 2,
SOC_MEMORY_TYPE_TCM = 3,
SOC_MEMORY_TYPE_SCP = 3,
SOC_MEMORY_TYPE_RTCRAM = 4,
SOC_MEMORY_TYPE_NUM,
};
@@ -53,7 +53,7 @@ enum {
#endif
// The memory used for SIMD instructions requires the bus of its memory regions be able to transfer the data in 128-bit
// TCM and RTCRAM memory regions cannot satisfy 128-bit data access
// SCP and RTCRAM memory regions cannot satisfy 128-bit data access
/**
* Defined the attributes and allocation priority of each memory on the chip,
@@ -66,7 +66,7 @@ const soc_memory_type_desc_t soc_memory_types[SOC_MEMORY_TYPE_NUM] = {
[SOC_MEMORY_TYPE_RETENT_MEM] = { "RETENT_RAM", { MALLOC_L2MEM_BASE_CAPS | MALLOC_CAP_RETENTION | MALLOC_CAP_SIMD, 0, 0 }},
[SOC_MEMORY_TYPE_L2MEM] = { "RAM", { MALLOC_L2MEM_BASE_CAPS | MALLOC_CAP_SIMD, 0, 0 }},
[SOC_MEMORY_TYPE_SPIRAM] = { "SPIRAM", { MALLOC_CAP_SPIRAM, 0, ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_SIMD }},
[SOC_MEMORY_TYPE_TCM] = { "TCM", { MALLOC_CAP_TCM, ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL, 0 }},
[SOC_MEMORY_TYPE_SCP] = { "SCP", { MALLOC_CAP_SCP, ESP32P4_MEM_COMMON_CAPS | MALLOC_CAP_INTERNAL, 0 }},
[SOC_MEMORY_TYPE_RTCRAM] = { "RTCRAM", { MALLOC_CAP_RTCRAM, 0, MALLOC_RTCRAM_BASE_CAPS}},
};
@@ -112,7 +112,7 @@ const soc_memory_region_t soc_memory_regions[] = {
#ifdef CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP
{ 0x50108000, APP_USABLE_LP_RAM_SIZE, SOC_MEMORY_TYPE_RTCRAM, 0, false}, //LPRAM
#endif
{ 0x30100000, 0x2000, SOC_MEMORY_TYPE_TCM, 0, false},
{ 0x30100000, 0x2000, SOC_MEMORY_TYPE_SCP, 0, false},
};
const size_t soc_memory_region_count = sizeof(soc_memory_regions) / sizeof(soc_memory_region_t);
@@ -125,7 +125,7 @@ extern int _data_start, _heap_start, _iram_start, _iram_end, _rtc_force_slow_end
extern int _rtc_p4_rev3_mspi_workaround_start, _rtc_p4_rev3_mspi_workaround_end;
#endif
#endif
extern int _tcm_text_start, _tcm_data_end;
extern int _scp_text_start, _scp_data_end;
extern int _rtc_reserved_start, _rtc_reserved_end;
extern int _rtc_ulp_memory_start;
@@ -146,7 +146,7 @@ SOC_RESERVE_MEMORY_REGION((intptr_t)&_data_start, (intptr_t)&_heap_start, dram_d
// Target has a shared D/IRAM virtual address, no need to calculate I_D_OFFSET like previous chips
SOC_RESERVE_MEMORY_REGION((intptr_t)&_iram_start, (intptr_t)&_iram_end, iram_code);
SOC_RESERVE_MEMORY_REGION((intptr_t)&_tcm_text_start, (intptr_t)&_tcm_data_end, tcm_code_data);
SOC_RESERVE_MEMORY_REGION((intptr_t)&_scp_text_start, (intptr_t)&_scp_data_end, scp_code_data);
#ifdef CONFIG_SPIRAM
SOC_RESERVE_MEMORY_REGION( SOC_EXTRAM_LOW, SOC_EXTRAM_HIGH, extram_region);
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
+1 -1
View File
@@ -1847,7 +1847,7 @@ config SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_MEM_TCM_SUPPORTED
config SOC_MEM_SCP_SUPPORTED
bool
default y
components/soc/esp32p4/include/soc/soc.h
+2 -2
View File
@@ -155,8 +155,8 @@
#define SOC_IROM_MASK_HIGH 0x4fc20000
#define SOC_DROM_MASK_LOW 0x4fc00000
#define SOC_DROM_MASK_HIGH 0x4fc20000
#define SOC_TCM_LOW 0x30100000
#define SOC_TCM_HIGH 0x30102000
#define SOC_SCP_LOW 0x30100000
#define SOC_SCP_HIGH 0x30102000
#define SOC_IRAM_LOW 0x4ff00000
#define SOC_IRAM_HIGH 0x4ffc0000
#define SOC_DRAM_LOW 0x4ff00000
components/soc/esp32p4/include/soc/soc_caps.h
+1 -1
View File
@@ -708,7 +708,7 @@
#define SOC_TEMPERATURE_SENSOR_SUPPORT_SLEEP_RETENTION (1)
/*-------------------------- Memory CAPS --------------------------*/
#define SOC_MEM_TCM_SUPPORTED (1)
#define SOC_MEM_SCP_SUPPORTED (1)
#define SOC_ASYNCHRONOUS_BUS_ERROR_MODE (1)
/*--------------------------- EMAC --------------------------------*/
#define SOC_EMAC_IEEE1588V2_SUPPORTED (1) /*!< EMAC Supports IEEE1588v2 time stamping */
docs/en/api-guides/memory-types.rst
+1 -1
View File
@@ -187,7 +187,7 @@ The ``DRAM_ATTR`` attribute can be used to force constants from DROM into the :r
Remaining RTC FAST memory is added to the heap unless the option :ref:`CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP` is disabled. This memory can be used interchangeably with :ref:`DRAM`, but is slightly slower to access.
.. only:: SOC_MEM_TCM_SUPPORTED
.. only:: SOC_MEM_SCP_SUPPORTED
SPM (Scratchpad Memory)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
docs/en/security/esp32p4_log.inc
+1 -1
View File
@@ -127,7 +127,7 @@
I (310) heap_init: At 4FF3AFC0 len 00004BE4 (18 KiB): RAM
I (316) heap_init: At 4FF40000 len 00060000 (384 KiB): RAM
I (323) heap_init: At 50108000 len 00007FE8 (31 KiB): RTCRAM
I (329) heap_init: At 30100044 len 00001FBC (7 KiB): TCM
I (329) heap_init: At 30100044 len 00001FBC (7 KiB): SCP
I (336) spi_flash: detected chip: generic
I (340) spi_flash: flash io: dio
W (344) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.
docs/zh_CN/api-guides/memory-types.rst
+1 -1
View File
@@ -187,7 +187,7 @@ DROM（数据存储在 flash 中）
除非禁用 :ref:`CONFIG_ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP` 选项，否则剩余的 RTC FAST memory 会被添加到堆中。该部分内存可以和 :ref:`DRAM` 互换使用，但是访问速度稍慢一点。
.. only:: SOC_MEM_TCM_SUPPORTED
.. only:: SOC_MEM_SCP_SUPPORTED
SPM（暂存内存）
^^^^^^^^^^^^^^^^^^^^^^^^^^^^
docs/zh_CN/security/esp32p4_log.inc
+1 -1
View File
@@ -127,7 +127,7 @@
I (310) heap_init: At 4FF3AFC0 len 00004BE4 (18 KiB): RAM
I (316) heap_init: At 4FF40000 len 00060000 (384 KiB): RAM
I (323) heap_init: At 50108000 len 00007FE8 (31 KiB): RTCRAM
I (329) heap_init: At 30100044 len 00001FBC (7 KiB): TCM
I (329) heap_init: At 30100044 len 00001FBC (7 KiB): SCP
I (336) spi_flash: detected chip: generic
I (340) spi_flash: flash io: dio
W (344) spi_flash: Detected size(4096k) larger than the size in the binary image header(2048k). Using the size in the binary image header.