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fix(mmu): fixed drom/irom reservation bus cap search logic

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This commit is contained in:
armando
2026-04-08 15:02:27 +08:00
parent 5c55b812be
commit ca135856c1
2 changed files with 6 additions and 19 deletions
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components/esp_mm/esp_mmu_map.c
+2 -2
View File
@@ -150,7 +150,7 @@ static void s_reserve_irom_region(mem_region_t *hw_mem_regions, int region_nums)
cache_bus_mask_t bus_mask = s_get_bus_mask((uint32_t)&_instruction_reserved_start, irom_len_to_reserve); cache_bus_mask_t bus_mask = s_get_bus_mask((uint32_t)&_instruction_reserved_start, irom_len_to_reserve);
for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) { for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) {
if (bus_mask & hw_mem_regions[i].bus_id) { if ((bus_mask & hw_mem_regions[i].bus_id) == bus_mask) {
if (hw_mem_regions[i].region_size <= irom_len_to_reserve) { if (hw_mem_regions[i].region_size <= irom_len_to_reserve) {
hw_mem_regions[i].free_head = hw_mem_regions[i].end; hw_mem_regions[i].free_head = hw_mem_regions[i].end;
hw_mem_regions[i].max_slot_size = 0; hw_mem_regions[i].max_slot_size = 0;
@@ -178,7 +178,7 @@ static void s_reserve_drom_region(mem_region_t *hw_mem_regions, int region_nums)
cache_bus_mask_t bus_mask = s_get_bus_mask((uint32_t)&_rodata_reserved_start, drom_len_to_reserve); cache_bus_mask_t bus_mask = s_get_bus_mask((uint32_t)&_rodata_reserved_start, drom_len_to_reserve);
for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) { for (int i = 0; i < SOC_MMU_LINEAR_ADDRESS_REGION_NUM; i++) {
if (bus_mask & hw_mem_regions[i].bus_id) { if ((bus_mask & hw_mem_regions[i].bus_id) == bus_mask) {
if (hw_mem_regions[i].region_size <= drom_len_to_reserve) { if (hw_mem_regions[i].region_size <= drom_len_to_reserve) {
hw_mem_regions[i].free_head = hw_mem_regions[i].end; hw_mem_regions[i].free_head = hw_mem_regions[i].end;
hw_mem_regions[i].max_slot_size = 0; hw_mem_regions[i].max_slot_size = 0;
components/hal/esp32s31/include/hal/cache_ll.h
+4 -17
View File
@@ -935,11 +935,7 @@ static inline void cache_ll_l1_enable_bus(uint32_t bus_id, cache_bus_mask_t mask
REG_CLR_BIT(CACHE_L1_ICACHE_CTRL_REG, ibus_mask); REG_CLR_BIT(CACHE_L1_ICACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0; uint32_t dbus_mask = 0;
if (bus_id == 1) { dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS0 : 0);
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS0 : 0);
} else {
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS1 : 0);
}
REG_CLR_BIT(CACHE_L1_DCACHE_CTRL_REG, dbus_mask); REG_CLR_BIT(CACHE_L1_DCACHE_CTRL_REG, dbus_mask);
} }
@@ -963,11 +959,7 @@ static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
} }
uint32_t dbus_mask = REG_READ(CACHE_L1_DCACHE_CTRL_REG); uint32_t dbus_mask = REG_READ(CACHE_L1_DCACHE_CTRL_REG);
if (cache_id == 0) { mask = (cache_bus_mask_t)(mask | ((!(dbus_mask & CACHE_L1_DCACHE_SHUT_DBUS0)) ? CACHE_BUS_DBUS0 : 0));
mask = (cache_bus_mask_t)(mask | ((!(dbus_mask & CACHE_L1_DCACHE_SHUT_DBUS0)) ? CACHE_BUS_DBUS0 : 0));
} else if (cache_id == 1) {
mask = (cache_bus_mask_t)(mask | ((!(dbus_mask & CACHE_L1_DCACHE_SHUT_DBUS1)) ? CACHE_BUS_DBUS0 : 0));
}
return mask; return mask;
} }
@@ -981,8 +973,7 @@ static inline cache_bus_mask_t cache_ll_l1_get_enabled_bus(uint32_t cache_id)
__attribute__((always_inline)) __attribute__((always_inline))
static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask) static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mask)
{ {
//On esp32h4, only `CACHE_BUS_IBUS0` and `CACHE_BUS_DBUS0` are supported. Use `cache_ll_l1_get_bus()` to get your bus first HAL_ASSERT((mask & (CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
HAL_ASSERT((mask & (CACHE_BUS_IBUS1 | CACHE_BUS_IBUS2| CACHE_BUS_DBUS1 | CACHE_BUS_DBUS2)) == 0);
uint32_t ibus_mask = 0; uint32_t ibus_mask = 0;
if (bus_id == 0) { if (bus_id == 0) {
@@ -993,11 +984,7 @@ static inline void cache_ll_l1_disable_bus(uint32_t bus_id, cache_bus_mask_t mas
REG_SET_BIT(CACHE_L1_ICACHE_CTRL_REG, ibus_mask); REG_SET_BIT(CACHE_L1_ICACHE_CTRL_REG, ibus_mask);
uint32_t dbus_mask = 0; uint32_t dbus_mask = 0;
if (bus_id == 1) { dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS0 : 0);
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS0 : 0);
} else {
dbus_mask = dbus_mask | ((mask & CACHE_BUS_DBUS0) ? CACHE_L1_DCACHE_SHUT_DBUS1 : 0);
}
REG_SET_BIT(CACHE_L1_DCACHE_CTRL_REG, dbus_mask); REG_SET_BIT(CACHE_L1_DCACHE_CTRL_REG, dbus_mask);
} }