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feat(mcpwm): support mcpwm on esp32h4

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This commit is contained in:
Chen Chen
2025-10-28 18:15:00 +08:00
parent c4f9d7177c
commit cb48f80f52
20 changed files with 2138 additions and 352 deletions
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components/esp_driver_mcpwm/test_apps/mcpwm/README.md
+2 -2
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@@ -1,2 +1,2 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
components/esp_hal_mcpwm/esp32c5/mcpwm_periph.c
+3 -4
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@@ -84,7 +84,6 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
/**
* MCPWM Registers to be saved during sleep retention
* - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
@@ -96,9 +95,9 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
* - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_EVT_EN2_REG, MCPWM_TASK_EN_REG, MCPWM_OP0_TSTMP_E1_REG, MCPWM_OP0_TSTMP_E2_REG, MCPWM_OP1_TSTMP_E1_REG, MCPWM_OP1_TSTMP_E2_REG, MCPWM_OP2_TSTMP_E1_REG, MCPWM_OP2_TSTMP_E2_REG
* - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
*/
#define MCPWM_RETENTION_REGS_CNT 68
#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x0)
static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x1ff18, 0x0};
#define MCPWM_RETENTION_REGS_CNT 67
#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4)
static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0xff8c, 0x0};
static const regdma_entries_config_t mcpwm_regs_retention[] = {
// backup stage: save configuration registers
// restore stage: restore the configuration registers
components/esp_hal_mcpwm/esp32c6/mcpwm_periph.c
+3 -4
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@@ -83,7 +83,6 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
/**
* MCPWM Registers to be saved during sleep retention
* - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
@@ -95,9 +94,9 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
* - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
* - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
*/
#define MCPWM_RETENTION_REGS_CNT 61
#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x0)
static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x318, 0x0};
#define MCPWM_RETENTION_REGS_CNT 60
#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4)
static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0x18c, 0x0};
static const regdma_entries_config_t mcpwm_regs_retention[] = {
// backup stage: save configuration registers
// restore stage: restore the configuration registers
components/esp_hal_mcpwm/esp32h2/mcpwm_periph.c
+3 -4
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@@ -83,7 +83,6 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
/**
* MCPWM Registers to be saved during sleep retention
* - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
@@ -95,9 +94,9 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[1] = {
* - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
* - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
*/
#define MCPWM_RETENTION_REGS_CNT 61
#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x0)
static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x318, 0x0};
#define MCPWM_RETENTION_REGS_CNT 60
#define MCPWM_RETENTION_REGS_BASE (DR_REG_MCPWM_BASE + 0x4)
static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0x18c, 0x0};
static const regdma_entries_config_t mcpwm_regs_retention[] = {
// backup stage: save configuration registers
// restore stage: restore the configuration registers
components/esp_hal_mcpwm/esp32h4/include/hal/mcpwm_ll.h
+1722
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File diff suppressed because it is too large Load Diff
components/esp_hal_mcpwm/esp32h4/mcpwm_periph.c
+202
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@@ -0,0 +1,202 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/interrupts.h"
#include "hal/mcpwm_periph.h"
#include "soc/mcpwm_reg.h"
#include "soc/gpio_sig_map.h"
const soc_mcpwm_signal_desc_t soc_mcpwm_signals[2] = {
{
.module_name = "MCPWM0",
.irq_id = ETS_PWM0_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM0_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM0_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
[1] = {
.fault_sig = PWM0_F1_IN_IDX
},
[2] = {
.fault_sig = PWM0_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM0_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM0_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM0_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM0_SYNC2_IN_IDX
}
}
},
{
.module_name = "MCPWM1",
.irq_id = ETS_PWM1_INTR_SOURCE,
.operators = {
[0] = {
.generators = {
[0] = {
.pwm_sig = PWM1_OUT0A_IDX
},
[1] = {
.pwm_sig = PWM1_OUT0B_IDX
}
}
},
[1] = {
.generators = {
[0] = {
.pwm_sig = PWM1_OUT1A_IDX
},
[1] = {
.pwm_sig = PWM1_OUT1B_IDX
}
}
},
[2] = {
.generators = {
[0] = {
.pwm_sig = PWM1_OUT2A_IDX
},
[1] = {
.pwm_sig = PWM1_OUT2B_IDX
}
}
}
},
.gpio_faults = {
[0] = {
.fault_sig = PWM1_F0_IN_IDX
},
[1] = {
.fault_sig = PWM1_F1_IN_IDX
},
[2] = {
.fault_sig = PWM1_F2_IN_IDX
}
},
.captures = {
[0] = {
.cap_sig = PWM1_CAP0_IN_IDX
},
[1] = {
.cap_sig = PWM1_CAP1_IN_IDX
},
[2] = {
.cap_sig = PWM1_CAP2_IN_IDX
}
},
.gpio_synchros = {
[0] = {
.sync_sig = PWM1_SYNC0_IN_IDX
},
[1] = {
.sync_sig = PWM1_SYNC1_IN_IDX
},
[2] = {
.sync_sig = PWM1_SYNC2_IN_IDX
}
}
}
};
/**
* MCPWM Registers to be saved during sleep retention
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG，MCPWM_TIMER0_SYNC_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
* |- Dead Time Configuration registers, e.g.: MCPWM_DT0_CFG_REG, MCPWM_DT0_FED_CFG_REG, MCPWM_DT0_RED_CFG_REG
* |- Carrier Configuration registers, e.g.: MCPWM_CARRIER0_CFG_REG
* └- Fault Handle Configuration registers, e.g.: MCPWM_FAULT_DETECT_REG, MCPWM_FH0_CFG0_REG, MCPWM_FH0_CFG1_REG
* - Capture Timer Configuration registers, e.g.: MCPWM_CAP_TIMER_CFG_REG, MCPWM_CAP_TIMER_PHASE_REG, MCPWM_CAP_CH0_CFG_REG, MCPWM_CAP_CH1_CFG_REG, MCPWM_CAP_CH2_CFG_REG
* - Interrupt enable registers, e.g.: MCPWM_INT_ENA_REG
* - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_EVT_EN2_REG, MCPWM_TASK_EN_REG, MCPWM_OP0_TSTMP_E1_REG, MCPWM_OP0_TSTMP_E2_REG, MCPWM_OP1_TSTMP_E1_REG, MCPWM_OP1_TSTMP_E2_REG, MCPWM_OP2_TSTMP_E1_REG, MCPWM_OP2_TSTMP_E2_REG
* - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
*/
#define MCPWM_RETENTION_REGS_CNT 67
#define MCPWM_RETENTION_REGS_BASE(i) DR_REG_MCPWM_BASE(i)
static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0xff8c, 0x0};
static const regdma_entries_config_t mcpwm0_regdma_entries[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00),
MCPWM_RETENTION_REGS_BASE(0), MCPWM_RETENTION_REGS_BASE(0),
MCPWM_RETENTION_REGS_CNT, 0, 0,
mcpwm_regs_map[0], mcpwm_regs_map[1],
mcpwm_regs_map[2], mcpwm_regs_map[3]),
.owner = ENTRY(0) | ENTRY(2),
},
};
static const regdma_entries_config_t mcpwm1_regdma_entries[] = {
[0] = {
.config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_MCPWM_LINK(0x00),
MCPWM_RETENTION_REGS_BASE(1), MCPWM_RETENTION_REGS_BASE(1),
MCPWM_RETENTION_REGS_CNT, 0, 0,
mcpwm_regs_map[0], mcpwm_regs_map[1],
mcpwm_regs_map[2], mcpwm_regs_map[3]),
.owner = ENTRY(0) | ENTRY(2),
},
};
const mcpwm_reg_retention_info_t mcpwm_reg_retention_info[2] = {
[0] = {
.regdma_entry_array = mcpwm0_regdma_entries,
.array_size = ARRAY_SIZE(mcpwm0_regdma_entries),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM0
},
[1] = {
.regdma_entry_array = mcpwm0_regdma_entries,
.array_size = ARRAY_SIZE(mcpwm1_regdma_entries),
.retention_module = SLEEP_RETENTION_MODULE_MCPWM1
},
};
components/esp_hal_mcpwm/esp32p4/mcpwm_periph.c
+3 -4
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@@ -153,7 +153,6 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[2] = {
#if SOC_MCPWM_SUPPORT_SLEEP_RETENTION
/**
* MCPWM Registers to be saved during sleep retention
* - Clk Configuration registers, e.g.: MCPWM_CLK_CFG_REG
* - Timer Configuration registers, e.g.: MCPWM_TIMER_SYNCI_CFG_REG, MCPWM_TIMER0_CFG0_REG, MCPWM_TIMER0_CFG1_REG, MCPWM_TIMER0_CFG1_REG
* - Operator Configuration registers, e.g.: MCPWM_OPERATOR_TIMERSEL_REG
* |- Generator Configuration registers, e.g.: MCPWM_GEN0_STMP_CFG_REG, MCPWM_GEN0_TSTMP_A_REG, MCPWM_GEN0_TSTMP_B_REG, MCPWM_GEN0_CFG0_REG, MCPWM_GEN0_FORCE_REG, MCPWM_GEN0_A_REG, MCPWM_GEN0_B_REG
@@ -165,9 +164,9 @@ const soc_mcpwm_signal_desc_t soc_mcpwm_signals[2] = {
* - ETM Configurations, e.g.: MCPWM_EVT_EN_REG, MCPWM_TASK_EN_REG
* - Misc Configurations, e.g.: MCPWM_UPDATE_CFG_REG
*/
#define MCPWM_RETENTION_REGS_CNT 68
#define MCPWM_RETENTION_REGS_BASE(i) REG_MCPWM_BASE(i)
static const uint32_t mcpwm_regs_map[4] = {0xefffeeef, 0x7efffbff, 0x1ff18, 0x0};
#define MCPWM_RETENTION_REGS_CNT 67
#define MCPWM_RETENTION_REGS_BASE(i) (REG_MCPWM_BASE(i) + 0x4)
static const uint32_t mcpwm_regs_map[4] = {0xf7fff777, 0x3f7ffdff, 0xff8c, 0x0};
#define MCPWM_SLEEP_RETENTION_ENTRIES(mcpwm_port) { \
/* backup stage: save configuration registers \
restore stage: restore the configuration registers */ \
components/soc/esp32h4/include/soc/Kconfig.soc_caps.in
+25 -1
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@@ -23,6 +23,10 @@ config SOC_PCNT_SUPPORTED
bool
default y
config SOC_MCPWM_SUPPORTED
bool
default y
config SOC_TWAI_SUPPORTED
bool
default y
@@ -587,6 +591,26 @@ config SOC_RMT_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_MCPWM_SWSYNC_CAN_PROPAGATE
bool
default y
config SOC_MCPWM_SUPPORT_ETM
bool
default y
config SOC_MCPWM_SUPPORT_EVENT_COMPARATOR
bool
default y
config SOC_MCPWM_CAPTURE_CLK_FROM_GROUP
bool
default y
config SOC_MCPWM_SUPPORT_SLEEP_RETENTION
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 3
@@ -961,7 +985,7 @@ config SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE
config SOC_PM_RETENTION_MODULE_NUM
int
default 32
default 64
config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
bool
components/soc/esp32h4/include/soc/clk_tree_defs.h
+47
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@@ -347,6 +347,53 @@ typedef enum {
LEDC_USE_XTAL_CLK = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
} soc_periph_ledc_clk_src_legacy_t;
//////////////////////////////////////////////////MCPWM/////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of MCPWM Timer
*/
#define SOC_MCPWM_TIMER_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM timer clock source
*/
typedef enum {
MCPWM_TIMER_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
MCPWM_TIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
MCPWM_TIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_TIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
} soc_periph_mcpwm_timer_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Capture Timer
*/
#define SOC_MCPWM_CAPTURE_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM capture clock source
*/
typedef enum {
MCPWM_CAPTURE_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
MCPWM_CAPTURE_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
MCPWM_CAPTURE_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CAPTURE_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
} soc_periph_mcpwm_capture_clk_src_t;
/**
* @brief Array initializer for all supported clock sources of MCPWM Carrier
*/
#define SOC_MCPWM_CARRIER_CLKS {SOC_MOD_CLK_PLL_F96M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
/**
* @brief Type of MCPWM carrier clock source
*/
typedef enum {
MCPWM_CARRIER_CLK_SRC_PLL96M = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the source clock */
MCPWM_CARRIER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
MCPWM_CARRIER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
MCPWM_CARRIER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F96M, /*!< Select PLL_F96M as the default clock choice */
} soc_periph_mcpwm_carrier_clk_src_t;
///////////////////////////////////////////////////// I2S //////////////////////////////////////////////////////////////
/**
components/soc/esp32h4/include/soc/retention_periph_defs.h
+6 -4
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@@ -49,12 +49,13 @@ typedef enum periph_retention_module {
SLEEP_RETENTION_MODULE_GPSPI3 = 25,
SLEEP_RETENTION_MODULE_LEDC = 26,
SLEEP_RETENTION_MODULE_MCPWM0 = 27,
SLEEP_RETENTION_MODULE_SDM0 = 28,
SLEEP_RETENTION_MODULE_MCPWM1 = 28,
SLEEP_RETENTION_MODULE_SDM0 = 29,
/* Modem module, which includes BLE and 802.15.4 */
SLEEP_RETENTION_MODULE_BLE_MAC = 29,
SLEEP_RETENTION_MODULE_BT_BB = 30,
SLEEP_RETENTION_MODULE_802154_MAC = 31,
SLEEP_RETENTION_MODULE_BLE_MAC = 30,
SLEEP_RETENTION_MODULE_BT_BB = 31,
SLEEP_RETENTION_MODULE_802154_MAC = 32,
SLEEP_RETENTION_MODULE_MAX = SOC_PM_RETENTION_MODULE_NUM - 1
} periph_retention_module_t;
@@ -87,6 +88,7 @@ typedef enum periph_retention_module {
: ((m) == SLEEP_RETENTION_MODULE_GPSPI3) ? true \
: ((m) == SLEEP_RETENTION_MODULE_LEDC) ? true \
: ((m) == SLEEP_RETENTION_MODULE_MCPWM0) ? true \
: ((m) == SLEEP_RETENTION_MODULE_MCPWM1) ? true \
: ((m) == SLEEP_RETENTION_MODULE_SDM0) ? true \
: false)
components/soc/esp32h4/include/soc/soc_caps.h
+7 -15
View File
@@ -39,7 +39,7 @@
#define SOC_AHB_GDMA_SUPPORTED 1
#define SOC_GPTIMER_SUPPORTED 1
#define SOC_PCNT_SUPPORTED 1
// #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32H4] IDF-12380
#define SOC_MCPWM_SUPPORTED 1
#define SOC_TWAI_SUPPORTED 1
#define SOC_ETM_SUPPORTED 1
// #define SOC_PARLIO_SUPPORTED 1 // TODO: [ESP32H4] IDF-12345 IDF-12347
@@ -328,19 +328,11 @@
#define SOC_RMT_SUPPORT_SLEEP_RETENTION 1 /*!< The sleep retention feature can help back up RMT registers before sleep */
/*-------------------------- MCPWM CAPS --------------------------------------*/
// #define SOC_MCPWM_GROUPS (1U) ///< 1 MCPWM groups on the chip (i.e., the number of independent MCPWM peripherals)
// #define SOC_MCPWM_TIMERS_PER_GROUP (3) ///< The number of timers that each group has
// #define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
// #define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
// #define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
// #define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
// #define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
// #define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
// #define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
// #define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
// #define SOC_MCPWM_SWSYNC_CAN_PROPAGATE (1) ///< Software sync event can be routed to its output
// #define SOC_MCPWM_SUPPORT_ETM (1) ///< Support ETM (Event Task Matrix)
// #define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP (1) ///< Capture timer shares clock with other PWM timers
#define SOC_MCPWM_SWSYNC_CAN_PROPAGATE 1 ///< Software sync event can be routed to its output
#define SOC_MCPWM_SUPPORT_ETM 1 ///< Support ETM (Event Task Matrix)
#define SOC_MCPWM_SUPPORT_EVENT_COMPARATOR 1 ///< Support event comparator (based on ETM)
#define SOC_MCPWM_CAPTURE_CLK_FROM_GROUP 1 ///< Capture timer shares clock with other PWM timers
#define SOC_MCPWM_SUPPORT_SLEEP_RETENTION 1 ///< Support back up registers before sleep
/*------------------------ USB SERIAL JTAG CAPS ------------------------------*/
// #define SOC_USB_SERIAL_JTAG_SUPPORT_LIGHT_SLEEP (1) /*!< Support to maintain minimum usb communication during light sleep */ // TODO: IDF-6395
@@ -527,7 +519,7 @@
#define SOC_PM_PAU_LINK_NUM (4)
#define SOC_PM_PAU_REGDMA_LINK_CONFIGURABLE (1)
#define SOC_PM_RETENTION_MODULE_NUM (32)
#define SOC_PM_RETENTION_MODULE_NUM (64)
/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
components/soc/esp32h4/register/soc/mcpwm_reg.h
+3
View File
@@ -11,6 +11,9 @@
extern "C" {
#endif
// MCPWM base address macro for multi-group support
#define DR_REG_MCPWM_BASE(i) (DR_REG_MCPWM0_BASE + (i) * 0x1000)
/** MCPWM_TIMER0_CFG0_REG register
* PWM timer0 period and update method configuration register.
*/
components/soc/esp32h4/register/soc/mcpwm_struct.h
+100 -300
View File
@@ -242,33 +242,19 @@ typedef union {
uint32_t val;
} mcpwm_genn_stmp_cfg_reg_t;
/** Type of genn_tstmp_a register
* Generatorn time stamp A's shadow register
/** Type of genn_tstmp register
* Generatorn time stamp shadow register (unified type for array access)
*/
typedef union {
struct {
/** cmprn_a : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator n time stamp A's shadow register.
/** cmprn : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator n time stamp shadow register.
*/
uint32_t cmprn_a:16;
uint32_t cmprn:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_genn_tstmp_a_reg_t;
/** Type of genn_tstmp_b register
* Generatorn time stamp B's shadow register
*/
typedef union {
struct {
/** cmprn_b : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM generator n time stamp B's shadow register.
*/
uint32_t cmprn_b:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_genn_tstmp_b_reg_t;
} mcpwm_genn_tstmp_reg_t;
/** Type of genn_cfg0 register
* Generatorn fault event T0 and T1 configuration register
@@ -371,217 +357,90 @@ typedef union {
uint32_t val;
} mcpwm_genn_force_reg_t;
/** Type of genn_a register
* PWMn output signal A actions configuration register
*/
typedef union {
struct {
/** genn_a_utez : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWMn A triggered by event TEZ when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_utez:2;
/** genn_a_utep : R/W; bitpos: [3:2]; default: 0;
* Configures action on PWMn A triggered by event TEP when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_utep:2;
/** genn_a_utea : R/W; bitpos: [5:4]; default: 0;
* Configures action on PWMn A triggered by event TEA when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_utea:2;
/** genn_a_uteb : R/W; bitpos: [7:6]; default: 0;
* Configures action on PWMn A triggered by event TEB when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_uteb:2;
/** genn_a_ut0 : R/W; bitpos: [9:8]; default: 0;
* Configures action on PWMn A triggered by event_t0 when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_ut0:2;
/** genn_a_ut1 : R/W; bitpos: [11:10]; default: 0;
* Configures action on PWMn A triggered by event_t1 when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_ut1:2;
/** genn_a_dtez : R/W; bitpos: [13:12]; default: 0;
* Configures action on PWMn A triggered by event TEZ when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_dtez:2;
/** genn_a_dtep : R/W; bitpos: [15:14]; default: 0;
* Configures action on PWMn A triggered by event TEP when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_dtep:2;
/** genn_a_dtea : R/W; bitpos: [17:16]; default: 0;
* Configures action on PWMn A triggered by event TEA when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_dtea:2;
/** genn_a_dteb : R/W; bitpos: [19:18]; default: 0;
* Configures action on PWMn A triggered by event TEB when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_dteb:2;
/** genn_a_dt0 : R/W; bitpos: [21:20]; default: 0;
* Configures action on PWMn A triggered by event_t0 when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_dt0:2;
/** genn_a_dt1 : R/W; bitpos: [23:22]; default: 0;
* Configures action on PWMn A triggered by event_t1 when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
*/
uint32_t genn_a_dt1:2;
uint32_t reserved_24:8;
};
uint32_t val;
} mcpwm_genn_a_reg_t;
/** Type of genn_b register
* PWMn output signal B actions configuration register
/** Type of genn register
* PWMn output signal actions configuration register (unified type for array access)
*/
typedef union {
struct {
/** genn_b_utez : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWMn B triggered by event TEZ when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
/** genn_utez : R/W; bitpos: [1:0]; default: 0;
* Configures action on PWMn triggered by event TEZ when timer increasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_utez:2;
/** genn_b_utep : R/W; bitpos: [3:2]; default: 0;
* Configures action on PWMn B triggered by event TEP when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_utez:2;
/** genn_utep : R/W; bitpos: [3:2]; default: 0;
* Configures action on PWMn triggered by event TEP when timer increasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_utep:2;
/** genn_b_utea : R/W; bitpos: [5:4]; default: 0;
* Configures action on PWMn B triggered by event TEA when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_utep:2;
/** genn_utea : R/W; bitpos: [5:4]; default: 0;
* Configures action on PWMn triggered by event TEA when timer increasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_utea:2;
/** genn_b_uteb : R/W; bitpos: [7:6]; default: 0;
* Configures action on PWMn B triggered by event TEB when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_utea:2;
/** genn_uteb : R/W; bitpos: [7:6]; default: 0;
* Configures action on PWMn triggered by event TEB when timer increasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_uteb:2;
/** genn_b_ut0 : R/W; bitpos: [9:8]; default: 0;
* Configures action on PWMn B triggered by event_t0 when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_uteb:2;
/** genn_ut0 : R/W; bitpos: [9:8]; default: 0;
* Configures action on PWMn triggered by event_t0 when timer increasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_ut0:2;
/** genn_b_ut1 : R/W; bitpos: [11:10]; default: 0;
* Configures action on PWMn B triggered by event_t1 when timer increasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_ut0:2;
/** genn_ut1 : R/W; bitpos: [11:10]; default: 0;
* Configures action on PWMn triggered by event_t1 when timer increasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_ut1:2;
/** genn_b_dtez : R/W; bitpos: [13:12]; default: 0;
* Configures action on PWMn B triggered by event TEZ when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_ut1:2;
/** genn_dtez : R/W; bitpos: [13:12]; default: 0;
* Configures action on PWMn triggered by event TEZ when timer decreasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_dtez:2;
/** genn_b_dtep : R/W; bitpos: [15:14]; default: 0;
* Configures action on PWMn B triggered by event TEP when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_dtez:2;
/** genn_dtep : R/W; bitpos: [15:14]; default: 0;
* Configures action on PWMn triggered by event TEP when timer decreasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_dtep:2;
/** genn_b_dtea : R/W; bitpos: [17:16]; default: 0;
* Configures action on PWMn B triggered by event TEA when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_dtep:2;
/** genn_dtea : R/W; bitpos: [17:16]; default: 0;
* Configures action on PWMn triggered by event TEA when timer decreasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_dtea:2;
/** genn_b_dteb : R/W; bitpos: [19:18]; default: 0;
* Configures action on PWMn B triggered by event TEB when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_dtea:2;
/** genn_dteb : R/W; bitpos: [19:18]; default: 0;
* Configures action on PWMn triggered by event TEB when timer decreasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_dteb:2;
/** genn_b_dt0 : R/W; bitpos: [21:20]; default: 0;
* Configures action on PWMn B triggered by event_t0 when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_dteb:2;
/** genn_dt0 : R/W; bitpos: [21:20]; default: 0;
* Configures action on PWMn triggered by event_t0 when timer decreasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_dt0:2;
/** genn_b_dt1 : R/W; bitpos: [23:22]; default: 0;
* Configures action on PWMn B triggered by event_t1 when timer decreasing.
* 0: No change
* 1: Low
* 2: High
* 3: Toggle
uint32_t genn_dt0:2;
/** genn_dt1 : R/W; bitpos: [23:22]; default: 0;
* Configures action on PWMn triggered by event_t1 when timer decreasing.
* 0: No change, 1: Low, 2: High, 3: Toggle
*/
uint32_t genn_b_dt1:2;
uint32_t genn_dt1:2;
uint32_t reserved_24:8;
};
uint32_t val;
} mcpwm_genn_b_reg_t;
} mcpwm_genn_reg_t;
/** Type of opn_tstmp register
* Operator timestamp register (unified type for array access)
*/
typedef union {
struct {
/** opn_tstmp_e : R/W; bitpos: [15:0]; default: 0;
* Configures the value of PWM operator timestamp.
*/
uint32_t opn_tstmp_e:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_opn_tstmp_reg_t;
/** Type of dtn_cfg register
* Dead time configuration register
@@ -1498,34 +1357,6 @@ typedef union {
uint32_t val;
} mcpwm_evt_en2_reg_t;
/** Type of opn_tstmp_e1 register
* Generatorn timer stamp E1 value register
*/
typedef union {
struct {
/** opn_tstmp_e1 : R/W; bitpos: [15:0]; default: 0;
* Configures generatorn timer stamp E1 value register
*/
uint32_t opn_tstmp_e1:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_opn_tstmp_e1_reg_t;
/** Type of opn_tstmp_e2 register
* Generatorn timer stamp E2 value register
*/
typedef union {
struct {
/** opn_tstmp_e2 : R/W; bitpos: [15:0]; default: 0;
* Configures generatorn timer stamp E2 value register
*/
uint32_t opn_tstmp_e2:16;
uint32_t reserved_16:16;
};
uint32_t val;
} mcpwm_opn_tstmp_e2_reg_t;
/** Type of clk register
* Global configuration register
*/
@@ -2239,62 +2070,36 @@ typedef union {
typedef struct {
volatile mcpwm_timern_cfg0_reg_t timer0_cfg0;
volatile mcpwm_timern_cfg1_reg_t timer0_cfg1;
volatile mcpwm_timern_sync_reg_t timer0_sync;
volatile mcpwm_timern_status_reg_t timer0_status;
volatile mcpwm_timern_cfg0_reg_t timer1_cfg0;
volatile mcpwm_timern_cfg1_reg_t timer1_cfg1;
volatile mcpwm_timern_sync_reg_t timer1_sync;
volatile mcpwm_timern_status_reg_t timer1_status;
volatile mcpwm_timern_cfg0_reg_t timer2_cfg0;
volatile mcpwm_timern_cfg1_reg_t timer2_cfg1;
volatile mcpwm_timern_sync_reg_t timer2_sync;
volatile mcpwm_timern_status_reg_t timer2_status;
volatile mcpwm_timern_cfg0_reg_t timern_cfg0;
volatile mcpwm_timern_cfg1_reg_t timern_cfg1;
volatile mcpwm_timern_sync_reg_t timern_sync;
volatile mcpwm_timern_status_reg_t timern_status;
} mcpwm_timer_regs_t;
typedef struct {
volatile mcpwm_genn_stmp_cfg_reg_t gen_stmp_cfg;
volatile mcpwm_genn_tstmp_reg_t timestamp[2];
volatile mcpwm_genn_cfg0_reg_t gen_cfg0;
volatile mcpwm_genn_force_reg_t gen_force;
volatile mcpwm_genn_reg_t generator[2];
volatile mcpwm_dtn_cfg_reg_t dt_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh_cfg1;
volatile mcpwm_fhn_status_reg_t fh_status;
} mcpwm_operator_reg_t;
typedef struct {
volatile mcpwm_opn_tstmp_reg_t timestamp[2];
} mcpwm_operator_tstmp_reg_t;
typedef struct mcpwm_dev_t {
volatile mcpwm_timer_regs_t timer[3];
volatile mcpwm_timer_synci_cfg_reg_t timer_synci_cfg;
volatile mcpwm_operator_timersel_reg_t operator_timersel;
volatile mcpwm_genn_stmp_cfg_reg_t gen0_stmp_cfg;
volatile mcpwm_genn_tstmp_a_reg_t gen0_tstmp_a;
volatile mcpwm_genn_tstmp_b_reg_t gen0_tstmp_b;
volatile mcpwm_genn_cfg0_reg_t gen0_cfg0;
volatile mcpwm_genn_force_reg_t gen0_force;
volatile mcpwm_genn_a_reg_t gen0_a;
volatile mcpwm_genn_b_reg_t gen0_b;
volatile mcpwm_dtn_cfg_reg_t dt0_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt0_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt0_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier0_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh0_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh0_cfg1;
volatile mcpwm_fhn_status_reg_t fh0_status;
volatile mcpwm_genn_stmp_cfg_reg_t gen1_stmp_cfg;
volatile mcpwm_genn_tstmp_a_reg_t gen1_tstmp_a;
volatile mcpwm_genn_tstmp_b_reg_t gen1_tstmp_b;
volatile mcpwm_genn_cfg0_reg_t gen1_cfg0;
volatile mcpwm_genn_force_reg_t gen1_force;
volatile mcpwm_genn_a_reg_t gen1_a;
volatile mcpwm_genn_b_reg_t gen1_b;
volatile mcpwm_dtn_cfg_reg_t dt1_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt1_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt1_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier1_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh1_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh1_cfg1;
volatile mcpwm_fhn_status_reg_t fh1_status;
volatile mcpwm_genn_stmp_cfg_reg_t gen2_stmp_cfg;
volatile mcpwm_genn_tstmp_a_reg_t gen2_tstmp_a;
volatile mcpwm_genn_tstmp_b_reg_t gen2_tstmp_b;
volatile mcpwm_genn_cfg0_reg_t gen2_cfg0;
volatile mcpwm_genn_force_reg_t gen2_force;
volatile mcpwm_genn_a_reg_t gen2_a;
volatile mcpwm_genn_b_reg_t gen2_b;
volatile mcpwm_dtn_cfg_reg_t dt2_cfg;
volatile mcpwm_dtn_fed_cfg_reg_t dt2_fed_cfg;
volatile mcpwm_dtn_red_cfg_reg_t dt2_red_cfg;
volatile mcpwm_carriern_cfg_reg_t carrier2_cfg;
volatile mcpwm_fhn_cfg0_reg_t fh2_cfg0;
volatile mcpwm_fhn_cfg1_reg_t fh2_cfg1;
volatile mcpwm_fhn_status_reg_t fh2_status;
volatile mcpwm_operator_reg_t operators[3];
volatile mcpwm_fault_detect_reg_t fault_detect;
volatile mcpwm_cap_timer_cfg_reg_t cap_timer_cfg;
volatile mcpwm_cap_timer_phase_reg_t cap_timer_phase;
@@ -2309,12 +2114,7 @@ typedef struct {
volatile mcpwm_evt_en_reg_t evt_en;
volatile mcpwm_task_en_reg_t task_en;
volatile mcpwm_evt_en2_reg_t evt_en2;
volatile mcpwm_opn_tstmp_e1_reg_t op0_tstmp_e1;
volatile mcpwm_opn_tstmp_e2_reg_t op0_tstmp_e2;
volatile mcpwm_opn_tstmp_e1_reg_t op1_tstmp_e1;
volatile mcpwm_opn_tstmp_e2_reg_t op1_tstmp_e2;
volatile mcpwm_opn_tstmp_e1_reg_t op2_tstmp_e1;
volatile mcpwm_opn_tstmp_e2_reg_t op2_tstmp_e2;
volatile mcpwm_operator_tstmp_reg_t operators_timestamp[3];
volatile mcpwm_clk_reg_t clk;
volatile mcpwm_version_reg_t version;
} mcpwm_dev_t;
docs/docs_not_updated/esp32h4.txt
-2
View File
@@ -127,8 +127,6 @@ api-reference/peripherals/bitscrambler.rst
api-reference/peripherals/temp_sensor.rst
api-reference/peripherals/usb_device.rst
api-reference/peripherals/jpeg.rst
api-reference/peripherals/mcpwm.rst
api-reference/peripherals/usb_host.rst
api-reference/peripherals/camera_driver.rst
api-reference/peripherals/adc_oneshot.rst
api-reference/peripherals/sdspi_share.rst
examples/peripherals/mcpwm/mcpwm_bdc_speed_control/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# MCPWM Brushed DC Motor Example
(See the README.md file in the upper level 'examples' directory for more information about examples.)
examples/peripherals/mcpwm/mcpwm_bldc_hall_control/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# MCPWM BLDC Motor Control with HALL Sensor Example
examples/peripherals/mcpwm/mcpwm_capture_hc_sr04/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# HC-SR04 Example based on MCPWM Capture
examples/peripherals/mcpwm/mcpwm_foc_svpwm_open_loop/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# MCPWM FOC SVPWM Generation Open Loop Example
examples/peripherals/mcpwm/mcpwm_servo_control/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# MCPWM RC Servo Control Example
(See the README.md file in the upper level 'examples' directory for more information about examples.)
examples/peripherals/mcpwm/mcpwm_sync/README.md
+2 -2
View File
@@ -1,5 +1,5 @@
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- |
| Supported Targets | ESP32 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S3 |
| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- |
# MCPWM Sync Example