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Merge branch 'fix/disable_pvt_for_esp32c5_v6.0' into 'release/v6.0'

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feat(esp32c5): disable PVT feature for esp32c5 (v6.0)

See merge request espressif/esp-idf!45702
This commit is contained in:
Jiang Jiang Jian
2026-02-12 15:47:21 +08:00
parent 63be46ed3d 3d263e7304
commit cd2a4df5fa
4 changed files with 17 additions and 6 deletions
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components/esp_security/src/init.c
+10
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@@ -55,6 +55,16 @@ static void esp_key_mgr_init(void)
ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103)
{
#if CONFIG_IDF_TARGET_ESP32C5
// Check for unsupported configuration: flash encryption with CPU frequency > 160MHz
// Manual encrypted flash writes are not stable at higher CPU clock.
// Please refer to the ESP32-C5 SoC Errata document for more details.
if (efuse_hal_flash_encryption_enabled() && CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ > 160) {
ESP_EARLY_LOGE(TAG, "Flash encryption with CPU frequency > 160MHz is not supported. Please reconfigure the CPU frequency.");
return ESP_ERR_NOT_SUPPORTED;
}
#endif
esp_crypto_clk_init();
#if SOC_KEY_MANAGER_SUPPORT_KEY_DEPLOYMENT
components/esp_system/port/soc/esp32c5/Kconfig.cpu
+7 -1
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@@ -1,9 +1,12 @@
choice ESP_DEFAULT_CPU_FREQ_MHZ
prompt "CPU frequency"
default ESP_DEFAULT_CPU_FREQ_MHZ_40 if IDF_ENV_FPGA
default ESP_DEFAULT_CPU_FREQ_MHZ_160 if SECURE_FLASH_ENC_ENABLED
default ESP_DEFAULT_CPU_FREQ_MHZ_240
help
CPU frequency to be set on application startup.
CPU frequency to be set on application startup. For flash encryption enabled case,
the default CPU frequency is 160MHz as the encrypted flash writes are not stable at
higher CPU clock. Please see SoC Errata document for details.
config ESP_DEFAULT_CPU_FREQ_MHZ_40
bool "40 MHz"
@@ -13,6 +16,9 @@ choice ESP_DEFAULT_CPU_FREQ_MHZ
config ESP_DEFAULT_CPU_FREQ_MHZ_160
bool "160 MHz"
config ESP_DEFAULT_CPU_FREQ_MHZ_240
# Encrypted flash writes aren't supported at 240 MHz.
# Please see SoC Errata document for details.
depends on !SECURE_FLASH_ENC_ENABLED
bool "240 MHz"
help
When 240MHz is selected, esp_flash_write_encrypted() will automatically limit CPU frequency during
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
-4
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@@ -195,10 +195,6 @@ config SOC_PMU_SUPPORTED
bool
default y
config SOC_PMU_PVT_SUPPORTED
bool
default y
config SOC_PAU_SUPPORTED
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
-1
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@@ -71,7 +71,6 @@
#define SOC_BOD_SUPPORTED 1
#define SOC_APM_SUPPORTED 1 /*!< Support for APM peripheral */
#define SOC_PMU_SUPPORTED 1
#define SOC_PMU_PVT_SUPPORTED 1
#define SOC_PAU_SUPPORTED 1
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1