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feat(esp_hw_support): use pvt to auto control digital ldo and rtc ldo for esp32c5

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This commit is contained in:
yanzihan@espressif.com
2026-01-20 14:28:35 +08:00
committed by Jack
parent 025ec41dac
commit d0b1371e34
15 changed files with 336 additions and 25 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/esp_hal_clock/esp32c5/include/hal/clk_gate_ll.h
+7 -2
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -154,9 +154,10 @@ FORCE_INLINE_ATTR void _clk_gate_ll_rtc_fast_to_lp_periph_en(bool enable)
typedef struct {
bool disable_uart0_clk; ///< Disable UART0 clock (when UART0 is not console)
bool disable_uart1_clk; ///< Disable UART1 clock (when UART1 is not console)
bool disable_mspi_flash_clk; ///< Disable MSPI flash clock (for PURE_RAM_APP)
bool disable_mspi_flash_clk; ///< Disable MSPI flash clock (for PURE_RAM_APP)
bool disable_crypto_periph_clk; ///< Disable crypto peripherals clock when TEE is not enabled
bool disable_usb_serial_jtag; ///< Disable USB-Serial-JTAG clock and pad (when not enabled)
bool disable_pvt_clk; ///< Disable PVT clock
} periph_ll_clk_gate_config_t;
/**
@@ -201,6 +202,10 @@ static inline void periph_ll_clk_gate_set_default(soc_reset_reason_t rst_reason,
PCR.uhci_conf.uhci_clk_en = 0;
PCR.tcm_mem_monitor_conf.tcm_mem_monitor_clk_en = 0;
PCR.psram_mem_monitor_conf.psram_mem_monitor_clk_en = 0;
if (config->disable_pvt_clk) {
PCR.pvt_monitor_conf.pvt_monitor_clk_en = 0;
PCR.pvt_monitor_func_clk_conf.pvt_monitor_func_clk_en = 0;
}
PCR.ctrl_clk_out_en.val = 0;
if (config->disable_usb_serial_jtag) {
components/esp_hw_support/port/esp32c5/CMakeLists.txt
+4
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@@ -14,6 +14,10 @@ if(NOT non_os_build)
list(APPEND srcs "sar_periph_ctrl.c")
endif()
if(NOT BOOTLOADER_BUILD AND CONFIG_ESP_ENABLE_PVT)
list(APPEND srcs "pmu_pvt.c")
endif()
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")
components/esp_hw_support/port/esp32c5/include/soc/rtc.h
+48 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -99,6 +99,53 @@ storing in efuse (based on ATE 5k ECO3 chips)
#define V_RTC_MID_MUL10000 10800
#define V_DIG_MID_MUL10000 10860
#if CONFIG_ESP_ENABLE_PVT
/*
set pvt default param
*/
#define PVT_CHANNEL0_SEL 33
#define PVT_CHANNEL1_SEL 37
#define PVT_CHANNEL0_CFG 0x13e80
#define PVT_CHANNEL1_CFG 0x13e80
#define PVT_CHANNEL2_CFG 0x10000
#define PVT_CMD0 0x24
#define PVT_CMD1 0x5
#define PVT_CMD2 0x427
#define PVT_TARGET 0xffff
#define PVT_CLK_DIV 1
#define PVT_DELAY_NUM_HIGH 150
#define PVT_DELAY_NUM_LOW 143
#define PVT_PUMP_CHANNEL_CODE 1
#define PVT_PUMP_BITMAP 22
#define PVT_PUMP_DRV 0
#define PVT_DELAY_NUM_PUMP 139
/**
* @brief Initialize PVT related parameters
*/
void pvt_auto_dbias_init(void);
/**
* @brief Enable or disable PVT functions
*
* @param enable true to enable, false to disable
*/
void pvt_func_enable(bool enable);
/**
* @brief Initialize charge pump related parameters
*/
void charge_pump_init(void);
/**
* @brief Enable or disable charge pump functions
*
* @param enable true to enable, false to disable
*/
void charge_pump_enable(bool enable);
#endif //#if CONFIG_ESP_ENABLE_PVT
/**
* @brief CPU clock configuration structure
*/
components/esp_hw_support/port/esp32c5/pmu_init.c
+20 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -19,6 +19,9 @@
#include "esp_private/ocode_init.h"
#include "esp_rom_sys.h"
#include "esp_hw_log.h"
#include "soc/rtc.h"
#include "hal/efuse_ll.h"
#include "hal/efuse_hal.h"
ESP_HW_LOG_ATTR_TAG(TAG, "pmu_init");
@@ -221,4 +224,20 @@ void pmu_init(void)
esp_ocode_calib_init();
}
#endif
#if CONFIG_ESP_ENABLE_PVT
/*setup pvt function*/
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
pvt_auto_dbias_init();
charge_pump_init();
pvt_func_enable(true);
charge_pump_enable(true);
esp_rom_delay_us(1000);
}
else {
ESP_HW_LOGW(TAG, "blk_version is less than 2, pvt function not supported in efuse.");
}
#endif
}
components/esp_hw_support/port/esp32c5/pmu_pvt.c
+161
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@@ -0,0 +1,161 @@
/*
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <stdint.h>
#include <stdlib.h>
#include <esp_types.h>
#include "sdkconfig.h"
#include "esp_attr.h"
#include "soc/soc.h"
#include "soc/pmu_struct.h"
#include "soc/pvt_reg.h"
#include "soc/pcr_reg.h"
#include "soc/pmu_reg.h"
#include "hal/pmu_hal.h"
#include "pmu_param.h"
#include "esp_rom_sys.h"
#include "esp_private/esp_pmu.h"
#include "soc/regi2c_dig_reg.h"
#include "regi2c_ctrl.h"
#include "soc/rtc.h"
#include "hal/efuse_ll.h"
#include "hal/efuse_hal.h"
#include "esp_hw_log.h"
static __attribute__((unused)) const char *TAG = "pmu_pvt";
#if CONFIG_ESP_ENABLE_PVT
static uint8_t get_lp_hp_gap(void)
{
int8_t lp_hp_gap = 0;
uint32_t blk_version = efuse_hal_blk_version();
uint8_t lp_hp_gap_efuse = 0;
if (blk_version >= 2) {
lp_hp_gap_efuse = efuse_ll_get_dbias_vol_gap();
bool gap_flag = lp_hp_gap_efuse >> 4;
uint8_t gap_abs_value = lp_hp_gap_efuse & 0xf;
if (gap_flag) {
lp_hp_gap = -1 * gap_abs_value;
} else {
lp_hp_gap = gap_abs_value;
}
lp_hp_gap = lp_hp_gap - 8;
assert((lp_hp_gap >= -15) && (lp_hp_gap <= 7));
if (lp_hp_gap < 0 ) {
lp_hp_gap = 16 - lp_hp_gap;
}
}
return lp_hp_gap;
}
static void set_pvt_hp_lp_gap(uint8_t value)
{
bool flag = value >> 4;
uint8_t abs_value = value & 0xf;
SET_PERI_REG_BITS(PVT_DBIAS_CMD0_REG, PVT_DBIAS_CMD0_OFFSET_FLAG, flag, PVT_DBIAS_CMD0_OFFSET_FLAG_S);
SET_PERI_REG_BITS(PVT_DBIAS_CMD0_REG, PVT_DBIAS_CMD0_OFFSET_VALUE, abs_value, PVT_DBIAS_CMD0_OFFSET_VALUE_S);
SET_PERI_REG_BITS(PVT_DBIAS_CMD1_REG, PVT_DBIAS_CMD1_OFFSET_FLAG, flag, PVT_DBIAS_CMD1_OFFSET_FLAG_S);
SET_PERI_REG_BITS(PVT_DBIAS_CMD1_REG, PVT_DBIAS_CMD1_OFFSET_VALUE, abs_value, PVT_DBIAS_CMD1_OFFSET_VALUE_S);
SET_PERI_REG_BITS(PVT_DBIAS_CMD2_REG, PVT_DBIAS_CMD2_OFFSET_FLAG, flag, PVT_DBIAS_CMD2_OFFSET_FLAG_S);
SET_PERI_REG_BITS(PVT_DBIAS_CMD2_REG, PVT_DBIAS_CMD2_OFFSET_VALUE, abs_value, PVT_DBIAS_CMD2_OFFSET_VALUE_S);
}
FORCE_INLINE_ATTR uint32_t get_pvt_hp_dbias(void)
{
return GET_PERI_REG_BITS2(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_DBIAS_VOL_V, PMU_HP_DBIAS_VOL_S);
}
FORCE_INLINE_ATTR uint32_t get_pvt_lp_dbias(void)
{
return GET_PERI_REG_BITS2(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_LP_DBIAS_VOL_V, PMU_LP_DBIAS_VOL_S);
}
void pvt_auto_dbias_init(void)
{
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
/*config for dbias func*/
CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN);
esp_rom_delay_us(1);
SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL0_SEL, PVT_CHANNEL0_SEL, PVT_DBIAS_CHANNEL0_SEL_S);
SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL_SEL0_REG, PVT_DBIAS_CHANNEL1_SEL, PVT_CHANNEL1_SEL, PVT_DBIAS_CHANNEL1_SEL_S); // Select monitor cell ,which used to monitor PVT situation
SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL0_SEL_REG, PVT_DBIAS_CHANNEL0_CFG, PVT_CHANNEL0_CFG, PVT_DBIAS_CHANNEL0_CFG_S);
SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL1_SEL_REG, PVT_DBIAS_CHANNEL1_CFG, PVT_CHANNEL1_CFG, PVT_DBIAS_CHANNEL1_CFG_S);
SET_PERI_REG_BITS(PVT_DBIAS_CHANNEL2_SEL_REG, PVT_DBIAS_CHANNEL2_CFG, PVT_CHANNEL2_CFG, PVT_DBIAS_CHANNEL2_CFG_S); // Configure filter threshold for avoiding auto-dbias overly sensitive regulation
SET_PERI_REG_BITS(PVT_DBIAS_CMD0_REG, PVT_DBIAS_CMD0_PVT, PVT_CMD0, PVT_DBIAS_CMD0_PVT_S);
SET_PERI_REG_BITS(PVT_DBIAS_CMD1_REG, PVT_DBIAS_CMD1_PVT, PVT_CMD1, PVT_DBIAS_CMD1_PVT_S);
SET_PERI_REG_BITS(PVT_DBIAS_CMD2_REG, PVT_DBIAS_CMD2_PVT, PVT_CMD2, PVT_DBIAS_CMD2_PVT_S); // Configure auto-dbias adjust property, such as adjusting step
SET_PERI_REG_BITS(PVT_DBIAS_TIMER_REG, PVT_TIMER_TARGET, PVT_TARGET, PVT_TIMER_TARGET_S); // Configure auto-dbias voltage regulation cycle
SET_PERI_REG_BITS(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM, PVT_CLK_DIV, PCR_PVT_MONITOR_FUNC_CLK_DIV_NUM_S);//pvt function clock divider number
/*config for pvt cell: unit0; site2; vt1*/
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_SEL); // choose pvt clk
SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_REG, PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0, PVT_DELAY_NUM_HIGH, PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT0_S); // The threshold for determining whether the voltage is too high
SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT1_VT1_CONF1_REG, PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1, PVT_DELAY_NUM_LOW, PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT1_S); // The threshold for determining whether the voltage is too low
SET_PERI_REG_BITS(PVT_COMB_PD_SITE2_UNIT2_VT1_CONF1_REG, PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2, PVT_DELAY_NUM_PUMP, PVT_DELAY_LIMIT_VT1_PD_SITE2_UNIT2_S); // The threshold for chargepump
/*config lp offset for pvt func*/
uint8_t lp_hp_gap = get_lp_hp_gap();
set_pvt_hp_lp_gap(lp_hp_gap);
}
}
void IRAM_ATTR pvt_func_enable(bool enable)
{
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
if (enable) {
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // start calibration @HP_CALI_DBIAS_DEFAULT
SET_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
SET_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
SET_PERI_REG_MASK(PVT_CLK_CFG_REG, PVT_MONITOR_CLK_PVT_EN); // once enable cannot be closed
SET_PERI_REG_MASK(PVT_COMB_PD_SITE2_UNIT0_VT1_CONF1_REG, PVT_MONITOR_EN_VT1_PD_SITE2_UNIT0); // enable pvt clk
esp_rom_delay_us(10);
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pvt
CLEAR_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_DBIAS_INIT); // must clear @HP_CALI_DBIAS_DEFAULT
SET_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); // enable auto dbias
} else {
uint32_t pvt_hp_dbias = get_pvt_hp_dbias();
uint32_t pvt_lp_dbias = get_pvt_lp_dbias(); // update pvt_cali_dbias
SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, pvt_hp_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, pvt_lp_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S);
CLEAR_PERI_REG_MASK(PVT_DBIAS_TIMER_REG, PVT_TIMER_EN); //disable auto dbias
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // hand over control of dbias to pmu
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_CONF_REG, PCR_PVT_MONITOR_CLK_EN);
CLEAR_PERI_REG_MASK(PCR_PVT_MONITOR_FUNC_CLK_CONF_REG, PCR_PVT_MONITOR_FUNC_CLK_EN);
}
}
}
void charge_pump_init(void)
{
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
/*config for charge pump*/
SET_PERI_REG_BITS(PVT_PMUP_CHANNEL_CFG_REG, PVT_PUMP_CHANNEL_CODE0, PVT_PUMP_CHANNEL_CODE, PVT_PUMP_CHANNEL_CODE0_S); //Set channel code
WRITE_PERI_REG(PVT_PMUP_BITMAP_LOW0_REG, (1 << PVT_PUMP_BITMAP)); // Select monitor cell for charge pump
SET_PERI_REG_BITS(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_DRV0, PVT_PUMP_DRV, PVT_PUMP_DRV0_S); //Configure the charging intensity
}
}
void IRAM_ATTR charge_pump_enable(bool enable)
{
uint32_t blk_version = efuse_hal_blk_version();
if (blk_version >= 2) {
if (enable) {
SET_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); // enable charge pump
} else {
CLEAR_PERI_REG_MASK(PVT_PMUP_DRV_CFG_REG, PVT_PUMP_EN); //disable charge pump
}
}
}
#endif
components/esp_hw_support/port/esp32c5/pmu_sleep.c
+4
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@@ -330,6 +330,10 @@ static void pmu_sleep_analog_init(pmu_context_t *ctx, const pmu_sleep_analog_con
pmu_ll_hp_set_regulator_xpd (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.xpd);
pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.dbias);
pmu_ll_hp_set_regulator_driver_bar (ctx->hal->dev, HP(SLEEP), analog->hp_sys.analog.drv_b);
#if CONFIG_ESP_ENABLE_PVT
uint32_t pvt_hp_dbias = GET_PERI_REG_BITS2(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_DBIAS_VOL_V, PMU_HP_DBIAS_VOL_S);
pmu_ll_hp_set_regulator_dbias (ctx->hal->dev, HP(MODEM), pvt_hp_dbias);
#endif
pmu_ll_lp_set_dbg_atten (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.dbg_atten);
pmu_ll_lp_set_current_power_off (ctx->hal->dev, LP(SLEEP), analog->lp_sys[LP(SLEEP)].analog.pd_cur);
components/esp_hw_support/port/esp32c5/rtc_clk.c
+20
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@@ -178,6 +178,10 @@ static FORCE_IRAM_ATTR void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
clk_ll_bus_update();
esp_rom_set_cpu_ticks_per_us(cpu_freq);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
static void rtc_clk_cpu_freq_to_rc_fast(void)
@@ -187,6 +191,10 @@ static void rtc_clk_cpu_freq_to_rc_fast(void)
clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
clk_ll_bus_update();
esp_rom_set_cpu_ticks_per_us(20);
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
charge_pump_enable(false);
pvt_func_enable(false);
#endif
}
/**
@@ -196,6 +204,12 @@ static void rtc_clk_cpu_freq_to_rc_fast(void)
*/
static void rtc_clk_cpu_freq_to_pll_240_mhz(int cpu_freq_mhz)
{
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
pvt_auto_dbias_init();
charge_pump_init();
pvt_func_enable(true);
charge_pump_enable(true);
#endif
// f_hp_root = 240MHz
uint32_t cpu_divider = CLK_LL_PLL_240M_FREQ_MHZ / cpu_freq_mhz;
clk_ll_cpu_set_divider(cpu_divider);
@@ -216,6 +230,12 @@ static void rtc_clk_cpu_freq_to_pll_240_mhz(int cpu_freq_mhz)
*/
static void rtc_clk_cpu_freq_to_pll_160_mhz(int cpu_freq_mhz)
{
#if CONFIG_ESP_ENABLE_PVT && !defined(BOOTLOADER_BUILD)
pvt_auto_dbias_init();
charge_pump_init();
pvt_func_enable(true);
charge_pump_enable(true);
#endif
// f_hp_root = 160MHz
uint32_t cpu_divider = CLK_LL_PLL_160M_FREQ_MHZ / cpu_freq_mhz;
clk_ll_cpu_set_divider(cpu_divider);
components/esp_hw_support/port/esp32c5/rtc_clk_init.c
+2
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@@ -81,6 +81,8 @@ void rtc_clk_init(rtc_clk_config_t cfg)
uint32_t hp_cali_dbias = get_act_hp_dbias();
uint32_t lp_cali_dbias = get_act_lp_dbias();
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // Hand over control of dbias to pmu
SET_PERI_REG_BITS(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_ACTIVE_HP_REGULATOR_DBIAS_S);
SET_PERI_REG_BITS(PMU_HP_MODEM_HP_REGULATOR0_REG, PMU_HP_MODEM_HP_REGULATOR_DBIAS, hp_cali_dbias, PMU_HP_MODEM_HP_REGULATOR_DBIAS_S);
SET_PERI_REG_BITS(PMU_HP_SLEEP_LP_REGULATOR0_REG, PMU_HP_SLEEP_LP_REGULATOR_DBIAS, lp_cali_dbias, PMU_HP_SLEEP_LP_REGULATOR_DBIAS_S);
components/esp_system/port/soc/esp32c5/clk.c
+3
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@@ -256,6 +256,9 @@ __attribute__((weak)) void esp_perip_clk_init(void)
#if !CONFIG_USJ_ENABLE_USB_SERIAL_JTAG && !CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED
clk_gate_config.disable_usb_serial_jtag = true;
#endif
#if !CONFIG_ESP_ENABLE_PVT
clk_gate_config.disable_pvt_clk = true;
#endif
periph_ll_clk_gate_set_default(rst_reason, &clk_gate_config);
}
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
+4
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@@ -195,6 +195,10 @@ config SOC_PMU_SUPPORTED
bool
default y
config SOC_PMU_PVT_SUPPORTED
bool
default y
config SOC_PAU_SUPPORTED
bool
default y
components/soc/esp32c5/include/soc/soc_caps.h
+1
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@@ -71,6 +71,7 @@
#define SOC_BOD_SUPPORTED 1
#define SOC_APM_SUPPORTED 1 /*!< Support for APM peripheral */
#define SOC_PMU_SUPPORTED 1
#define SOC_PMU_PVT_SUPPORTED 1
#define SOC_PAU_SUPPORTED 1
#define SOC_RTC_TIMER_V2_SUPPORTED 1
#define SOC_LP_AON_SUPPORTED 1
components/soc/esp32c5/include/soc/system_periph_retention.h
+11 -1
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -77,6 +77,16 @@ extern const regdma_entries_config_t flash_spimem_regs_retention[SPIMEM_RETENTIO
#define SYSTIMER_RETENTION_LINK_LEN 19
extern const regdma_entries_config_t systimer_regs_retention[SYSTIMER_RETENTION_LINK_LEN];
/**
* @brief Provide access to pvt configuration registers retention
* context definition.
*
* This is an internal function of the sleep retention driver, and is not
* useful for external use.
*/
#define PVT_RETENTION_LINK_LEN 1
extern const regdma_entries_config_t pvt_regs_retention[PVT_RETENTION_LINK_LEN];
#ifdef __cplusplus
}
#endif
components/soc/esp32c5/register/soc/pvt_reg.h
+19 -13
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -363,10 +363,12 @@ extern "C" {
/** PVT_DBIAS_CMD0 : R/W; bitpos: [16:0]; default: 0;
* needs field desc
*/
#define PVT_DBIAS_CMD0 0x0001FFFFU
#define PVT_DBIAS_CMD0_M (PVT_DBIAS_CMD0_V << PVT_DBIAS_CMD0_S)
#define PVT_DBIAS_CMD0_V 0x0001FFFFU
#define PVT_DBIAS_CMD0_S 0
#define PVT_DBIAS_CMD0_OFFSET_FLAG 1
#define PVT_DBIAS_CMD0_OFFSET_FLAG_S 16
#define PVT_DBIAS_CMD0_OFFSET_VALUE 0x1F
#define PVT_DBIAS_CMD0_OFFSET_VALUE_S 11
#define PVT_DBIAS_CMD0_PVT 0x7FF
#define PVT_DBIAS_CMD0_PVT_S 0
/** PVT_DBIAS_CMD1_REG register
* needs desc
@@ -375,10 +377,12 @@ extern "C" {
/** PVT_DBIAS_CMD1 : R/W; bitpos: [16:0]; default: 0;
* needs field desc
*/
#define PVT_DBIAS_CMD1 0x0001FFFFU
#define PVT_DBIAS_CMD1_M (PVT_DBIAS_CMD1_V << PVT_DBIAS_CMD1_S)
#define PVT_DBIAS_CMD1_V 0x0001FFFFU
#define PVT_DBIAS_CMD1_S 0
#define PVT_DBIAS_CMD1_OFFSET_FLAG 1
#define PVT_DBIAS_CMD1_OFFSET_FLAG_S 16
#define PVT_DBIAS_CMD1_OFFSET_VALUE 0x1F
#define PVT_DBIAS_CMD1_OFFSET_VALUE_S 11
#define PVT_DBIAS_CMD1_PVT 0x7FF
#define PVT_DBIAS_CMD1_PVT_S 0
/** PVT_DBIAS_CMD2_REG register
* needs desc
@@ -387,10 +391,12 @@ extern "C" {
/** PVT_DBIAS_CMD2 : R/W; bitpos: [16:0]; default: 0;
* needs field desc
*/
#define PVT_DBIAS_CMD2 0x0001FFFFU
#define PVT_DBIAS_CMD2_M (PVT_DBIAS_CMD2_V << PVT_DBIAS_CMD2_S)
#define PVT_DBIAS_CMD2_V 0x0001FFFFU
#define PVT_DBIAS_CMD2_S 0
#define PVT_DBIAS_CMD2_OFFSET_FLAG 1
#define PVT_DBIAS_CMD2_OFFSET_FLAG_S 16
#define PVT_DBIAS_CMD2_OFFSET_VALUE 0x1F
#define PVT_DBIAS_CMD2_OFFSET_VALUE_S 11
#define PVT_DBIAS_CMD2_PVT 0x7FF
#define PVT_DBIAS_CMD2_PVT_S 0
/** PVT_DBIAS_CMD3_REG register
* needs desc
components/soc/esp32c5/register/soc/pvt_struct.h
+31 -7
View File
@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -347,10 +347,18 @@ typedef union {
*/
typedef union {
struct {
/** dbias_cmd0 : R/W; bitpos: [16:0]; default: 0;
/** dbias_cmd0 : R/W; bitpos: [10:0]; default: 0;
* needs field desc
*/
uint32_t dbias_cmd0:17;
uint32_t dbias_cmd0_pvt:11;
/** dbias_cmd0_offset_value : R/W; bitpos: [15:11]; default: 0;
* needs field desc
*/
uint32_t dbias_cmd0_offset_value:5;
/** dbias_cmd0_offset_flag : R/W; bitpos: [16]; default: 0;
* needs field desc
*/
uint32_t dbias_cmd0_offset_flag:1;
uint32_t reserved_17:15;
};
uint32_t val;
@@ -361,10 +369,18 @@ typedef union {
*/
typedef union {
struct {
/** dbias_cmd1 : R/W; bitpos: [16:0]; default: 0;
/** dbias_cmd1 : R/W; bitpos: [10:0]; default: 0;
* needs field desc
*/
uint32_t dbias_cmd1:17;
uint32_t dbias_cmd1_pvt:11;
/** dbias_cmd1_offset_value : R/W; bitpos: [15:11]; default: 0;
* needs field desc
*/
uint32_t dbias_cmd1_offset_value:5;
/** dbias_cmd1_offset_flag : R/W; bitpos: [16]; default: 0;
* needs field desc
*/
uint32_t dbias_cmd1_offset_flag:1;
uint32_t reserved_17:15;
};
uint32_t val;
@@ -375,10 +391,18 @@ typedef union {
*/
typedef union {
struct {
/** dbias_cmd2 : R/W; bitpos: [16:0]; default: 0;
/** dbias_cmd2 : R/W; bitpos: [10:0]; default: 0;
* needs field desc
*/
uint32_t dbias_cmd2:17;
uint32_t dbias_cmd2_pvt:11;
/** dbias_cmd2_offset_value : R/W; bitpos: [15:11]; default: 0;
* needs field desc
*/
uint32_t dbias_cmd2_offset_value:5;
/** dbias_cmd2_offset_flag : R/W; bitpos: [16]; default: 0;
* needs field desc
*/
uint32_t dbias_cmd2_offset_flag:1;
uint32_t reserved_17:15;
};
uint32_t val;
components/soc/esp32c5/register/soc/reg_base.h
+1
View File
@@ -37,6 +37,7 @@
#define DR_REG_SLCHOST_BASE 0x60018000
#define DR_REG_PVT_MONITOR_BASE 0x60019000
#define DR_REG_PSRAM_MEM_MONITOR_BASE 0x6001A000
#define DR_REG_PVT_BASE DR_REG_PVT_MONITOR_BASE
/**
* @brief Peripheral 1 Modules