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Merge branch 'fix/p4_min_rev_usage_v6.0' into 'release/v6.0'

Browse Source 
P4: fix wrong rev_min usage in rom and other places (v6.0)

See merge request espressif/esp-idf!45223
This commit is contained in:
Jiang Jiang Jian
2026-01-30 10:50:51 +08:00
parent 1f2045975f 79f7427729
commit d3e1887bbc
17 changed files with 56 additions and 42 deletions
Download Patch File Download Diff File Expand all files Collapse all files
components/bootloader/subproject/CMakeLists.txt
+1 -1
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@@ -68,7 +68,7 @@ idf_build_set_property(__OUTPUT_SDKCONFIG 0)
# Define a property for the default linker script
set(LD_DEFAULT_PATH "${CMAKE_CURRENT_SOURCE_DIR}/main/ld/${IDF_TARGET}")
project(bootloader)
if(CONFIG_ESP32P4_REV_MIN_300)
if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
target_linker_script("__idf_main" INTERFACE "${LD_DEFAULT_PATH}/bootloader.rev3.ld.in")
else()
target_linker_script("__idf_main" INTERFACE "${LD_DEFAULT_PATH}/bootloader.ld.in")
components/bootloader_support/src/flash_encrypt.c
+2 -2
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@@ -214,7 +214,7 @@ void esp_flash_encryption_set_release_mode(void)
#endif // CONFIG_SOC_FLASH_ENCRYPTION_XTS_AES_128_DERIVED
#endif // !CONFIG_IDF_TARGET_ESP32
#ifdef SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
#if SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) {
uint8_t xts_pseudo_level = 0;
esp_efuse_read_field_blob(ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL, &xts_pseudo_level, ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[0]->bit_count);
@@ -505,7 +505,7 @@ bool esp_flash_encryption_cfg_verify_release_mode(void)
}
#endif
#if SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND
#if SOC_FLASH_ENCRYPTION_XTS_AES_SUPPORT_PSEUDO_ROUND && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
if (spi_flash_encrypt_ll_is_pseudo_rounds_function_supported()) {
uint8_t xts_pseudo_level = 0;
esp_efuse_read_field_blob(ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL, &xts_pseudo_level, ESP_EFUSE_XTS_DPA_PSEUDO_LEVEL[0]->bit_count);
components/efuse/esp32p4/include/esp_efuse_chip.h
+2 -2
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@@ -66,7 +66,7 @@ typedef enum {
ESP_EFUSE_KEY_PURPOSE_USER = 0, /**< User purposes (software-only use) */
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY = 1, /**< ECDSA private key (Expected in little endian order)*/
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY_P256 = ESP_EFUSE_KEY_PURPOSE_ECDSA_KEY, /**< ECDSA private key (P256) (Expected in little endian order)*/
#endif
@@ -82,7 +82,7 @@ typedef enum {
ESP_EFUSE_KEY_PURPOSE_SECURE_BOOT_DIGEST2 = 11, /**< SECURE_BOOT_DIGEST2 (Secure Boot key digest) */
ESP_EFUSE_KEY_PURPOSE_KM_INIT_KEY = 12, /**< KM_INIT_KEY */
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_1 = 13, /**< PSRAM encryption key (XTS_AES_256_KEY_1) */
ESP_EFUSE_KEY_PURPOSE_XTS_AES_256_PSRAM_KEY_2 = 14, /**< PSRAM encryption key (XTS_AES_256_KEY_2) */
ESP_EFUSE_KEY_PURPOSE_XTS_AES_128_PSRAM_KEY = 15, /**< PSRAM encryption key (XTS_AES_128_KEY) */
components/efuse/esp32p4/include/esp_efuse_table.h
+1 -1
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@@ -10,7 +10,7 @@ extern "C" {
#include "sdkconfig.h"
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
#include "esp_efuse_table_v3.0.h"
#else
#include "esp_efuse_table_v0.0_v2.0.h"
components/efuse/esp32p4/sources.cmake
+1 -1
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@@ -3,7 +3,7 @@ set(EFUSE_SOC_SRCS
"esp_efuse_fields.c"
)
if(CONFIG_ESP32P4_REV_MIN_FULL GREATER_EQUAL 300)
if(NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
list(APPEND EFUSE_SOC_SRCS
"esp_efuse_table_v3.0.c"
"esp_efuse_rtc_calib.c"
components/esp_hw_support/lowpower/port/esp32p4/Kconfig.p4_rev3_mspi_workaround
+1 -1
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@@ -1,7 +1,7 @@
config P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
bool
depends on IDF_TARGET_ESP32P4
default y if ESP32P4_REV_MIN_300
default y if ESP32P4_REV_MIN_300 # Fixed since REV3.1
config P4_REV3_MSPI_WORKAROUND_SIZE
hex
components/esp_hw_support/port/esp32p4/Kconfig.hw_support
+2 -1
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@@ -12,7 +12,8 @@ config ESP32P4_SELECTS_REV_LESS_V3
choice ESP32P4_REV_MIN
prompt "Minimum Supported ESP32-P4 Revision"
default ESP32P4_REV_MIN_1
default ESP32P4_REV_MIN_300 if IDF_CI_BUILD
default ESP32P4_REV_MIN_301
help
Required minimum chip revision. ESP-IDF will check for it and
reject to boot if the chip revision fails the check.
components/esp_hw_support/port/esp32p4/pmu_init.c
+2 -2
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@@ -177,7 +177,7 @@ static void pmu_hp_system_init_default(pmu_context_t *ctx)
pmu_hp_system_param_default(mode, &param);
pmu_hp_system_init(ctx, mode, &param);
}
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
lp_sys_ll_set_hp_mem_lowpower_mode(MEM_AUX_DEEPSLEEP);
#endif
}
@@ -196,7 +196,7 @@ static void pmu_lp_system_init_default(pmu_context_t *ctx)
pmu_lp_system_param_default(mode, &param);
pmu_lp_system_init(ctx, mode, &param);
}
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
lp_sys_ll_set_lp_mem_lowpower_mode(MEM_AUX_DEEPSLEEP);
#endif
}
components/esp_hw_support/port/esp32p4/pmu_sleep.c
+6 -2
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@@ -426,7 +426,9 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
}
} else {
#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
if (efuse_hal_chip_revision() == 300) {
lp_clkrst_ll_boot_from_lp_ram(true);
}
#endif
}
@@ -457,8 +459,10 @@ TCM_IRAM_ATTR uint32_t pmu_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt,
ldo_ll_enable(LDO_ID2UNIT(CONFIG_ESP_LDO_CHAN_PSRAM_DOMAIN), true);
#endif
#if CONFIG_P4_REV3_MSPI_CRASH_AFTER_POWER_UP_WORKAROUND
// Set reset vector back to HP ROM after deepsleep request rejected
lp_clkrst_ll_boot_from_lp_ram(false);
if (efuse_hal_chip_revision() == 300) {
// Set reset vector back to HP ROM after deepsleep request rejected
lp_clkrst_ll_boot_from_lp_ram(false);
}
#endif
}
components/esp_hw_support/port/esp32p4/rtc_clk_init.c
+3 -3
View File
@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -67,7 +67,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
hp_dcmvset = pvt_hp_dcmvset;
}
// Switch to DCDC
#if CONFIG_ESP32P4_REV_MIN_301
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
unsigned chip_version = efuse_hal_chip_revision();
if (ESP_CHIP_REV_ABOVE(chip_version, 301)) {
SET_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD);
@@ -78,7 +78,7 @@ void rtc_clk_init(rtc_clk_config_t cfg)
pmu_ll_hp_set_dcm_vset(&PMU, PMU_MODE_HP_ACTIVE, hp_dcmvset);
SET_PERI_REG_MASK(PMU_HP_ACTIVE_HP_REGULATOR0_REG, PMU_DIG_REGULATOR0_DBIAS_SEL); // Hand over control of dbias to pmu
esp_rom_delay_us(1000);
#if CONFIG_ESP32P4_REV_MIN_301
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
if (ESP_CHIP_REV_ABOVE(chip_version, 301)) {
REG_SET_FIELD(LP_SYSTEM_REG_SYS_CTRL_REG, LP_SYSTEM_REG_LP_FIB_SEL, 0xEF);// lp_fib_sel bit4 set to 0: select dig_fib_reg instead of ana_fib_reg
CLEAR_PERI_REG_MASK(PMU_DCM_CTRL_REG, PMU_DCDC_FB_RES_FORCE_PD);
components/esp_lcd/test_apps/mipi_dsi_lcd/main/test_mipi_dsi_panel.c
+1 -1
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@@ -616,7 +616,7 @@ TEST_CASE("MIPI DSI draw YUV422 image (EK79007)", "[mipi_dsi]")
test_bsp_disable_dsi_phy_power();
}
#if !(CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL < 300)
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
TEST_CASE("MIPI DSI draw Gray8 image (EK79007)", "[mipi_dsi]")
{
components/esp_psram/system_layer/esp_psram.c
+8 -3
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@@ -167,8 +167,9 @@ static void IRAM_ATTR s_mapping(int v_start, int size)
}
#endif //CONFIG_IDF_TARGET_ESP32
#if CONFIG_ESP32P4_REV_MIN_FULL == 300
#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
#include "hal/psram_ctrlr_ll.h"
#include "hal/efuse_hal.h"
static void IRAM_ATTR esp_psram_p4_rev3_workaround(void)
{
spi_mem_s_dev_t backup_reg = {};
@@ -417,8 +418,12 @@ esp_err_t esp_psram_init(void)
}
}
#if CONFIG_ESP32P4_REV_MIN_FULL == 300
esp_psram_p4_rev3_workaround();
#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
// This workaround is only needed for P4 rev 300 (3.0.0)
unsigned chip_revision = efuse_hal_chip_revision();
if (chip_revision == 300) {
esp_psram_p4_rev3_workaround();
}
#endif
uint32_t psram_available_size = 0;
components/esp_rom/CMakeLists.txt
+7 -8
View File
@@ -97,8 +97,7 @@ if(target STREQUAL "linux")
target_compile_options(${COMPONENT_LIB} PRIVATE -Wno-integer-overflow -Wno-shift-count-overflow)
endif()
else()
# TODO: IDF-13410. Update to (CONFIG_ESP32P4_REV_MIN_FULL GREATER_EQUAL 200) when chip efuse is correct.
if(CONFIG_ESP32P4_REV_MIN_300)
if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.eco5.ld")
elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
target_linker_script(${COMPONENT_LIB} INTERFACE "${target_folder}/${ld_folder}/${target}.rom.beta5.ld")
@@ -113,7 +112,7 @@ else()
endif()
if(CONFIG_COMPILER_FLOAT_LIB_FROM_GCCLIB)
if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410
if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
rom_linker_script("eco5.libgcc")
elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
rom_linker_script("beta5.libgcc")
@@ -121,7 +120,7 @@ else()
rom_linker_script("libgcc")
endif()
else()
if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410.
if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
rom_linker_script("eco5.rvfp")
else()
rom_linker_script("rvfp")
@@ -168,7 +167,7 @@ if(BOOTLOADER_BUILD)
if(target STREQUAL "esp32" OR target STREQUAL "esp32s2")
rom_linker_script("libc-funcs")
else()
if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410
if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
rom_linker_script("eco5.libc")
elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
rom_linker_script("beta5.libc")
@@ -180,7 +179,7 @@ if(BOOTLOADER_BUILD)
rom_linker_script("libc-suboptimal_for_misaligned_mem")
endif()
if(CONFIG_LIBC_NEWLIB)
if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410
if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
rom_linker_script("eco5.newlib")
elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
rom_linker_script("beta5.newlib")
@@ -339,7 +338,7 @@ else() # Regular app build
if(CONFIG_ESP_ROM_HAS_NEWLIB AND NOT target STREQUAL "esp32" AND NOT target STREQUAL "esp32s2")
# ESP32 and S2 are a bit different, keep them as special cases in the target specific include section
if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410
if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
rom_linker_script("eco5.libc")
elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
rom_linker_script("beta5.libc")
@@ -350,7 +349,7 @@ else() # Regular app build
rom_linker_script("libc-suboptimal_for_misaligned_mem")
endif()
if(CONFIG_LIBC_NEWLIB)
if(CONFIG_ESP32P4_REV_MIN_300) # TODO: IDF-13410
if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
rom_linker_script("eco5.newlib")
elseif(CONFIG_IDF_TARGET_ESP32H4 AND NOT CONFIG_ESP32H4_SELECTS_REV_MP) # TODO: ESP32H4 IDF-13835
rom_linker_script("beta5.newlib")
components/esp_system/CMakeLists.txt
+1 -1
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@@ -99,7 +99,7 @@ else()
# Generate sections.ld.in and pass it through linker script generator
set(sections_name "ld/${target}/sections.ld.in")
if(CONFIG_ESP32P4_REV_MIN_300)
if(CONFIG_IDF_TARGET_ESP32P4 AND NOT CONFIG_ESP32P4_SELECTS_REV_LESS_V3)
set(sections_name "ld/${target}/sections.rev3.ld.in")
endif()
target_linker_script(${COMPONENT_LIB} INTERFACE "${sections_name}"
components/esp_system/port/cpu_start.c
+2 -2
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@@ -686,7 +686,7 @@ NOINLINE_ATTR static void system_early_init(const soc_reset_reason_t *rst_reas)
#if SOC_CPU_CORES_NUM > 1 // there is no 'single-core mode' for natively single-core processors
#if !CONFIG_ESP_SYSTEM_SINGLE_CORE_MODE
#if CONFIG_IDF_TARGET_ESP32P4 && CONFIG_ESP32P4_REV_MIN_FULL >= 300
#if CONFIG_IDF_TARGET_ESP32P4 && !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
// Ensure autoclock gating mode for core1 is enabled, it gets disabled in single-core mode.
REG_SET_BIT(HP_SYS_CLKRST_CPU_WAITI_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN);
#endif
@@ -704,7 +704,7 @@ NOINLINE_ATTR static void system_early_init(const soc_reset_reason_t *rst_reas)
REG_CLR_BIT(SYSTEM_CORE_1_CONTROL_0_REG, SYSTEM_CONTROL_CORE_1_RESETING);
#endif
#elif CONFIG_IDF_TARGET_ESP32P4
#if CONFIG_ESP32P4_REV_MIN_FULL >= 300
#if !CONFIG_ESP32P4_SELECTS_REV_LESS_V3
// In single core mode, the CPU system should ignore the WFI state of core1 when entering WFI autoclock gating mode.
REG_CLR_BIT(HP_SYS_CLKRST_CPU_WAITI_CTRL0_REG, HP_SYS_CLKRST_REG_CORE1_WAITI_ICG_EN);
#endif
components/esp_system/port/soc/esp32p4/system_internal.c
+14 -11
View File
@@ -32,6 +32,7 @@
#include "hal/axi_dma_ll.h"
#include "hal/dw_gdma_ll.h"
#include "hal/dma2d_ll.h"
#include "hal/efuse_hal.h"
void esp_system_reset_modules_on_exit(void)
{
@@ -123,19 +124,21 @@ void esp_system_reset_modules_on_exit(void)
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_RSA);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_SHA);
#if CONFIG_ESP32P4_REV_MIN_FULL <= 100
// enable soc clk and reset parent crypto
SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_CRYPTO);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_CRYPTO);
#if CONFIG_ESP32P4_REV_MIN_FULL < 101
if (efuse_hal_chip_revision() < 101) {
// enable soc clk and reset parent crypto
SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_CRYPTO_SYS_CLK_EN);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_CRYPTO);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_CRYPTO);
// enable soc clk for key manager
SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN);
// enable soc clk for key manager
SET_PERI_REG_MASK(HP_SYS_CLKRST_SOC_CLK_CTRL1_REG, HP_SYS_CLKRST_REG_KEY_MANAGER_SYS_CLK_EN);
// enable key manager peripheral clock and reset
SET_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL25_REG, HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_KM);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_KM);
// enable key manager peripheral clock and reset
SET_PERI_REG_MASK(HP_SYS_CLKRST_PERI_CLK_CTRL25_REG, HP_SYS_CLKRST_REG_CRYPTO_KM_CLK_EN);
SET_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_KM);
CLEAR_PERI_REG_MASK(HP_SYS_CLKRST_HP_RST_EN2_REG, HP_SYS_CLKRST_REG_RST_EN_KM);
}
#endif
#if CONFIG_ESP32P4_REV_MIN_FULL == 0
components/soc/include/soc/chip_revision.h
+2
View File
@@ -29,12 +29,14 @@ extern "C" {
*/
#define ESP_CHIP_REV_ABOVE(rev, min_rev) ((min_rev) <= (rev))
#define ESP_CHIP_REV_BETWEEN(rev, min_rev, max_rev) (((min_rev) <= (rev)) && ((rev) <= (max_rev)))
#define ESP_CHIP_REV_MAJOR_AND_ABOVE(rev, min_rev) (((rev) / 100 == (min_rev) / 100) && ((rev) >= (min_rev)))
/**
* eFuse block revision strategy is same as chip revision
*/
#define ESP_EFUSE_BLK_REV_ABOVE(rev, min_rev) ESP_CHIP_REV_ABOVE(rev, min_rev)
#define ESP_EFUSE_BLK_REV_BETWEEN(rev, min_rev, max_rev) ESP_CHIP_REV_BETWEEN(rev, min_rev, max_rev)
#define ESP_EFUSE_BLK_REV_MAJOR_AND_ABOVE(rev, min_rev) ESP_CHIP_REV_MAJOR_AND_ABOVE(rev, min_rev)
#ifdef __cplusplus