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fix(tee): fix failed to configure flash on C6 v0.1 and above when REV_MIN_0 configured

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This commit is contained in:
Xiao Xufeng
2026-01-18 04:33:30 +08:00
parent 148e333495
commit dd9706564f
2 changed files with 18 additions and 16 deletions
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components/bootloader_support/bootloader_flash/src/bootloader_flash.c
+17 -15
View File
@@ -232,19 +232,20 @@ static uint32_t current_read_mapping = UINT32_MAX;
*/
static void rom_read_api_workaround(void)
{
#if CONFIG_ESP32C6_REV_MIN_0
extern void spi_common_set_dummy_output(esp_rom_spiflash_read_mode_t mode);
extern void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
#if CONFIG_ESP32C6_REV_MIN_FULL == 0
if (efuse_hal_chip_revision() == 0) {
extern void spi_common_set_dummy_output(esp_rom_spiflash_read_mode_t mode);
extern void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
static bool is_first_call = true;
if (is_first_call) {
uint32_t dummy_val = UINT32_MAX;
uint32_t dest_addr = ESP_PARTITION_TABLE_OFFSET + ESP_PARTITION_TABLE_MAX_LEN;
esp_rom_spiflash_write(dest_addr, &dummy_val, sizeof(dummy_val));
is_first_call = false;
}
static bool is_first_call = true;
if (is_first_call) {
uint32_t dummy_val = UINT32_MAX;
uint32_t dest_addr = ESP_PARTITION_TABLE_OFFSET + ESP_PARTITION_TABLE_MAX_LEN;
esp_rom_spiflash_write(dest_addr, &dummy_val, sizeof(dummy_val));
is_first_call = false;
}
uint32_t freqdiv = 0;
uint32_t freqdiv = 0;
#if CONFIG_ESPTOOLPY_FLASHFREQ_80M
freqdiv = 1;
@@ -265,10 +266,11 @@ static void rom_read_api_workaround(void)
read_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
#endif
esp_rom_spiflash_config_clk(freqdiv, 1);
spi_dummy_len_fix(1, freqdiv);
esp_rom_spiflash_config_readmode(read_mode);
spi_common_set_dummy_output(read_mode);
esp_rom_spiflash_config_clk(freqdiv, 1);
spi_dummy_len_fix(1, freqdiv);
esp_rom_spiflash_config_readmode(read_mode);
spi_common_set_dummy_output(read_mode);
}
#endif
}
components/esp_rom/patches/esp_rom_sys.c
+1 -1
View File
@@ -158,5 +158,5 @@ void __attribute__((constructor)) ets_ops_set_rom_patches(void)
ets_ops_table_ptr = &ets_ops_patch_table_ptr;
}
#endif // CONFIG_ESP32C5_REV_MIN_100 || CONFIG_ESP32C61_REV_MIN_100
#endif // CONFIG_ESP32C5_REV_MIN_FULL <= 100 || CONFIG_ESP32C61_REV_MIN_FULL <= 100
#endif // ESP_ROM_DELAY_US_PATCH && CONFIG_SECURE_ENABLE_TEE && !NON_OS_BUILD