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Merge branch 'fix/mmu_psram_anti_fi_target_condition_v6.0' into 'release/v6.0'

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Fix MMU PSRAM anti-fi MMU target check (v6.0)

See merge request espressif/esp-idf!43036
This commit is contained in:
Mahavir Jain
2025-11-13 09:36:55 +05:30
parent b6c253a3c8 beb0303ad6
commit dea7c3dcf4
3 changed files with 4 additions and 4 deletions
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components/hal/esp32c5/include/hal/mmu_ll.h
+1 -1
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@@ -233,7 +233,7 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
if (mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100) {
ESP_FAULT_ASSERT(REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_SENSITIVE);
} else {
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID && efuse_hal_chip_revision() > 100));
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100));
}
}
components/hal/esp32c61/include/hal/mmu_ll.h
+1 -1
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@@ -235,7 +235,7 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
if (mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100) {
ESP_FAULT_ASSERT(REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)) & SOC_MMU_SENSITIVE);
} else {
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID && efuse_hal_chip_revision() > 100));
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0 && efuse_hal_chip_revision() > 100));
}
}
components/hal/esp32p4/include/hal/mmu_ll.h
+2 -2
View File
@@ -294,10 +294,10 @@ __attribute__((always_inline)) static inline void mmu_ll_write_entry(uint32_t mm
// Anti-FI check to confirm the encryption status for PSRAM entry.
// This avoids a potential FI attacks to keep PSRAM unencrypted and
// hence read out plaintext in execute from PSRAM model.
if (mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID) {
if (mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0) {
ESP_FAULT_ASSERT(REG_READ(content_reg) & SOC_MMU_PSRAM_SENSITIVE);
} else {
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && mmu_id == MMU_LL_PSRAM_MMU_ID));
ESP_FAULT_ASSERT(!(mmu_ll_cache_encryption_enabled() && target == MMU_TARGET_PSRAM0));
}
}