refactor(hal): graduate systimer hal driver into esp_hal_systimer

2026-04-27 11:03:11 +00:00 · 2026-01-28 17:15:49 +08:00
parent 41f15f5329
commit eeb24057c4
93 changed files with 1006 additions and 1006 deletions
@@ -4,7 +4,6 @@
 * SPDX-License-Identifier: Apache-2.0
 */

-#include "hal/systimer_hal.h"
 #include "hal/ds_hal.h"
 #include "hal/ds_ll.h"
 #include "hal/assert.h"
@@ -0,0 +1,7 @@
+# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
+
+components/esp_hal_systimer/test_apps/systimer_rom_impl:
+  disable:
+    - if: SOC_SYSTIMER_SUPPORTED != 1
+  depends_components:
+    - esp_hal_systimer
@@ -0,0 +1,29 @@
+idf_build_get_property(target IDF_TARGET)
+
+set(srcs)
+set(public_include "include")
+if(CONFIG_SOC_SYSTIMER_SUPPORTED)
+    list(APPEND public_include "${target}/include")
+endif()
+
+if(CONFIG_SOC_SYSTIMER_SUPPORTED)
+    if(CONFIG_HAL_SYSTIMER_USE_ROM_IMPL)
+        list(APPEND srcs "rom_patch.c")
+        # ESP32C2 revision < 2.0 needs additional ROM patches
+        if(CONFIG_IDF_TARGET_ESP32C2 AND (CONFIG_ESP32C2_REV_MIN_FULL LESS 200))
+            list(APPEND srcs "esp32c2/rom_patch_rev1.c")
+        endif()
+    else()
+        list(APPEND srcs "systimer_hal.c")
+    endif()
+endif()
+
+idf_component_register(SRCS ${srcs}
+                       INCLUDE_DIRS ${public_include}
+                       REQUIRES soc hal esp_rom
+                       LDFRAGMENTS linker.lf)
+
+# Link the ROM SYSTIMER HAL implementation linker script if selected
+if(CONFIG_HAL_SYSTIMER_USE_ROM_IMPL)
+    target_linker_script(${COMPONENT_LIB} INTERFACE "${target}/rom.systimer.ld")
+endif()
@@ -0,0 +1,12 @@
+config HAL_SYSTIMER_USE_ROM_IMPL
+    bool "Use ROM implementation of SysTimer HAL driver"
+    depends on ESP_ROM_HAS_HAL_SYSTIMER
+    default y
+    help
+        Enable this flag to use HAL functions from ROM instead of ESP-IDF.
+
+        If keeping this as "n" in your project, you will have less free IRAM.
+        If making this as "y" in your project, you will increase free IRAM,
+        but you will lose the possibility to debug this module, and some new
+        features will be added and bugs will be fixed in the IDF source
+        but cannot be synced to ROM.
@@ -0,0 +1,62 @@
+# ESP Hardware Abstraction Layer for System Timer Peripheral
+
+> [!NOTE]
+> This component is currently in beta. Its API, behavior, and compatibility may change at any time and without notice; backward compatibility is not guaranteed. Use caution when integrating into production systems.
+
+## Overview
+
+The ESP Hardware Abstraction Layer for System Timer Peripheral (`esp_hal_systimer`) provides a unified interface to interact with the system timer (SYSTIMER) peripheral across all ESP chip families. This component abstracts the hardware-specific details of different SYSTIMER implementations, enabling consistent usage patterns regardless of the underlying hardware.
+
+The SYSTIMER is a high-resolution timer used for:
+- System time tracking
+- FreeRTOS tick generation
+- High-precision timing operations
+- Event timer (ETM) trigger generation
+
+## Architecture
+
+The HAL architecture consists of two primary layers:
+
+1. **HAL Layer (Upper)**: Defines the operational sequences and data structures required to interact with the SYSTIMER peripheral, including:
+   - Initialization and de-initialization functions
+   - Counter value operations
+   - Alarm configuration and management
+   - Time conversion utilities
+   - Clock source configuration
+
+2. **Low-Level Layer (Bottom)**: Acts as a translation layer between the HAL and the register definitions in the `soc` component, handling:
+   - Register access abstractions
+   - Chip-specific register configurations
+   - Hardware feature compatibility
+   - Clock and prescaler settings
+
+## Features
+
+- Unified SYSTIMER interface across all ESP chip families
+- Support for multiple counters and alarms
+- High-resolution timing (typically 16MHz resolution)
+- Flexible clock source configuration
+- ETM (Event Timer Module) support where available
+- Platform-specific optimizations
+- IRAM-safe implementation for critical sections
+- ROM implementation support for certain chips
+- Chip-specific implementations contained in separate directories
+
+## Usage
+
+This component is primarily used by ESP-IDF system services such as:
+- **esp_timer**: High-resolution timer implementation
+- **FreeRTOS**: System tick generation
+- **esp_hw_support**: System time and clock management
+
+For advanced developers implementing custom timing solutions, the HAL functions can be used directly. However, please note that the interfaces provided by this component are internal to ESP-IDF and are subject to change.
+
+## Dependencies
+
+- `soc`: Provides chip-specific register definitions
+- `hal`: Core hardware abstraction utilities and macros
+- `esp_rom`: ROM function interfaces (when using ROM implementation)
+
+## ROM Implementation
+
+Some chips support using ROM-based SYSTIMER HAL implementations for reduced code size. This is controlled by the `CONFIG_HAL_SYSTIMER_USE_ROM_IMPL` configuration option. When enabled, the component uses ROM linker scripts to link against ROM functions instead of compiling the HAL implementation.
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -19,6 +19,15 @@ extern "C" {
 // All these functions get invoked either from ISR or HAL that linked to IRAM.
 // Always inline these functions even no gcc optimization is applied.

+/******************* SYSTIMER LL CAPS *************************/
+#define SYSTIMER_LL_COUNTER_NUM             2  // Number of counter units
+#define SYSTIMER_LL_ALARM_NUM               3  // Number of alarm units
+#define SYSTIMER_LL_BIT_WIDTH_LO            32 // Bit width of systimer low part
+#define SYSTIMER_LL_BIT_WIDTH_HI            20 // Bit width of systimer high part
+#define SYSTIMER_LL_INT_LEVEL               1  // Systimer peripheral uses level interrupt
+#define SYSTIMER_LL_ALARM_MISS_COMPENSATE   1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
+#define SYSTIMER_LL_FIXED_DIVIDER           1  // Clock source divider is fixed: 2.5
+
 /******************* Clock *************************/

 __attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
@@ -11,7 +11,7 @@ PROVIDE( systimer_hal_select_alarm_mode = 0x400002d0 );
 PROVIDE( systimer_hal_connect_alarm_counter = 0x400002d4 );
 PROVIDE( systimer_hal_counter_can_stall_by_cpu = 0x400002d8 );

-/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
+/* The following ROM functions are commented out because they're patched in the rom_patch.c */
 /* PROVIDE( systimer_hal_init = 0x400002a8 ); */
 /* PROVIDE( systimer_hal_get_time = 0x400002b0 ); */
 /* PROVIDE( systimer_hal_set_alarm_target = 0x400002b4 ); */
@@ -1,18 +1,28 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */

-#include "sdkconfig.h"
+/**
+ * @brief ROM patch for ESP32C2 revision < 2.0
+ *
+ * ESP32C2 early revisions (< 2.0) have incomplete systimer HAL implementations in ROM.
+ * The ROM provides only basic functions (get_counter_value, get_alarm_value, etc.),
+ * while the following functions need to be patched in flash:
+ * - systimer_hal_init
+ * - systimer_hal_deinit
+ * - systimer_hal_set_tick_rate_ops
+ * - systimer_hal_get_time
+ * - systimer_hal_set_alarm_target
+ * - systimer_hal_set_alarm_period
+ * - systimer_hal_counter_value_advance
+ */
+
 #include <stddef.h>
-#include "esp_rom_caps.h"
 #include "hal/systimer_hal.h"
 #include "hal/systimer_ll.h"

-#if CONFIG_HAL_SYSTIMER_USE_ROM_IMPL
-
-#if CONFIG_IDF_TARGET_ESP32C2 && (CONFIG_ESP32C2_REV_MIN_FULL < 200)
 void systimer_hal_init(systimer_hal_context_t *hal)
 {
    hal->dev = &SYSTIMER;
@@ -63,22 +73,3 @@ void systimer_hal_counter_value_advance(systimer_hal_context_t *hal, uint32_t co
    systimer_ll_set_counter_value(hal->dev, counter_id, new_count.val);
    systimer_ll_apply_counter_value(hal->dev, counter_id);
 }
-#endif // CONFIG_IDF_TARGET_ESP32C2 && (CONFIG_ESP32C2_REV_MIN_FULL < 200)
-
-#if ESP_ROM_SYSTIMER_INIT_PATCH
-void systimer_hal_init(systimer_hal_context_t *hal)
-{
-    hal->dev = &SYSTIMER;
-    systimer_ll_enable_clock(hal->dev, true);
-    systimer_ll_enable_etm(&SYSTIMER, true);
-}
-
-void systimer_hal_deinit(systimer_hal_context_t *hal)
-{
-    systimer_ll_enable_etm(&SYSTIMER, false);
-    systimer_ll_enable_clock(hal->dev, false);
-    hal->dev = NULL;
-}
-#endif // ESP_ROM_SYSTIMER_INIT_PATCH
-
-#endif // CONFIG_HAL_SYSTIMER_USE_ROM_IMPL
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -19,6 +19,15 @@ extern "C" {
 // All these functions get invoked either from ISR or HAL that linked to IRAM.
 // Always inline these functions even no gcc optimization is applied.

+/******************* SYSTIMER LL CAPS *************************/
+#define SYSTIMER_LL_COUNTER_NUM             2  // Number of counter units
+#define SYSTIMER_LL_ALARM_NUM               3  // Number of alarm units
+#define SYSTIMER_LL_BIT_WIDTH_LO            32 // Bit width of systimer low part
+#define SYSTIMER_LL_BIT_WIDTH_HI            20 // Bit width of systimer high part
+#define SYSTIMER_LL_INT_LEVEL               1  // Systimer peripheral uses level interrupt
+#define SYSTIMER_LL_ALARM_MISS_COMPENSATE   1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
+#define SYSTIMER_LL_FIXED_DIVIDER           1  // Clock source divider is fixed: 2.5
+
 /******************* Clock *************************/

 __attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -19,6 +19,15 @@ extern "C" {
 // All these functions get invoked either from ISR or HAL that linked to IRAM.
 // Always inline these functions even no gcc optimization is applied.

+/******************* SYSTIMER LL CAPS *************************/
+#define SYSTIMER_LL_COUNTER_NUM             2  // Number of counter units
+#define SYSTIMER_LL_ALARM_NUM               3  // Number of alarm units
+#define SYSTIMER_LL_BIT_WIDTH_LO            32 // Bit width of systimer low part
+#define SYSTIMER_LL_BIT_WIDTH_HI            20 // Bit width of systimer high part
+#define SYSTIMER_LL_INT_LEVEL               1  // Systimer peripheral uses level interrupt
+#define SYSTIMER_LL_ALARM_MISS_COMPENSATE   1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
+#define SYSTIMER_LL_FIXED_DIVIDER           1  // Clock source divider is fixed: 2.5
+
 /******************* Clock *************************/

 __attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
@@ -9,7 +9,7 @@
 ***************************************/

 /* Functions */
-/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
+/* The following ROM functions are commented out because they're patched in the rom_patch.c */
 /* systimer_hal_init = 0x400003d0; */
 /* systimer_hal_deinit = 0x400003d4; */
 systimer_hal_set_tick_rate_ops = 0x400003d8;
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -19,6 +19,15 @@ extern "C" {
 // All these functions get invoked either from ISR or HAL that linked to IRAM.
 // Always inline these functions even no gcc optimization is applied.

+/******************* SYSTIMER LL CAPS *************************/
+#define SYSTIMER_LL_COUNTER_NUM             2  // Number of counter units
+#define SYSTIMER_LL_ALARM_NUM               3  // Number of alarm units
+#define SYSTIMER_LL_BIT_WIDTH_LO            32 // Bit width of systimer low part
+#define SYSTIMER_LL_BIT_WIDTH_HI            20 // Bit width of systimer high part
+#define SYSTIMER_LL_INT_LEVEL               1  // Systimer peripheral uses level interrupt
+#define SYSTIMER_LL_ALARM_MISS_COMPENSATE   1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
+#define SYSTIMER_LL_FIXED_DIVIDER           1  // Clock source divider is fixed: 2.5
+
 /******************* Clock *************************/

 __attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
@@ -9,7 +9,7 @@
 ***************************************/

 /* Functions */
-/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
+/* The following ROM functions are commented out because they're patched in the rom_patch.c */
 /* systimer_hal_init = 0x400003c0; */
 /* systimer_hal_deinit = 0x400003c4; */

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -19,6 +19,15 @@ extern "C" {
 // All these functions get invoked either from ISR or HAL that linked to IRAM.
 // Always inline these functions even no gcc optimization is applied.

+/******************* SYSTIMER LL CAPS *************************/
+#define SYSTIMER_LL_COUNTER_NUM             2  // Number of counter units
+#define SYSTIMER_LL_ALARM_NUM               3  // Number of alarm units
+#define SYSTIMER_LL_BIT_WIDTH_LO            32 // Bit width of systimer low part
+#define SYSTIMER_LL_BIT_WIDTH_HI            20 // Bit width of systimer high part
+#define SYSTIMER_LL_INT_LEVEL               1  // Systimer peripheral uses level interrupt
+#define SYSTIMER_LL_ALARM_MISS_COMPENSATE   1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
+#define SYSTIMER_LL_FIXED_DIVIDER           1  // Clock source divider is fixed: 2.5
+
 /******************* Clock *************************/

 __attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
@@ -10,7 +10,7 @@

 /* Functions */

-/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
+/* The following ROM functions are commented out because they're patched in the rom_patch.c */
 /* systimer_hal_init = 0x400003d0; */
 /* systimer_hal_deinit = 0x400003d4; */

@@ -0,0 +1,218 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/systimer_struct.h"
+#include "soc/clk_tree_defs.h"
+#include "soc/pcr_struct.h"
+#include "hal/assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// All these functions get invoked either from ISR or HAL that linked to IRAM.
+// Always inline these functions even no gcc optimization is applied.
+
+/******************* SYSTIMER LL CAPS *************************/
+#define SYSTIMER_LL_COUNTER_NUM             2  // Number of counter units
+#define SYSTIMER_LL_ALARM_NUM               3  // Number of alarm units
+#define SYSTIMER_LL_BIT_WIDTH_LO            32 // Bit width of systimer low part
+#define SYSTIMER_LL_BIT_WIDTH_HI            20 // Bit width of systimer high part
+#define SYSTIMER_LL_INT_LEVEL               1  // Systimer peripheral uses level interrupt
+#define SYSTIMER_LL_ALARM_MISS_COMPENSATE   1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
+#define SYSTIMER_LL_FIXED_DIVIDER           1  // Clock source divider is fixed to 2 when clock source is XTAL
+
+/******************* Clock *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
+{
+    dev->conf.clk_en = en;
+}
+
+// Set clock source: XTAL(default) or RC_FAST
+static inline void systimer_ll_set_clock_source(soc_periph_systimer_clk_src_t clk_src)
+{
+    PCR.systimer_func_clk_conf.systimer_func_clk_sel = (clk_src == SYSTIMER_CLK_SRC_RC_FAST) ? 1 : 0;
+}
+
+static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void)
+{
+    return (PCR.systimer_func_clk_conf.systimer_func_clk_sel == 1) ? SYSTIMER_CLK_SRC_RC_FAST : SYSTIMER_CLK_SRC_XTAL;
+}
+
+/**
+ * @brief Enable the bus clock for systimer module
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void systimer_ll_enable_bus_clock(bool enable)
+{
+    PCR.systimer_conf.systimer_clk_en = enable;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define systimer_ll_enable_bus_clock(...) do { \
+        (void)__DECLARE_RCC_RC_ATOMIC_ENV; \
+        systimer_ll_enable_bus_clock(__VA_ARGS__); \
+    } while(0)
+
+/**
+ * @brief Reset the systimer module
+ *
+ * @param group_id Group ID
+ */
+static inline void systimer_ll_reset_register(void)
+{
+    PCR.systimer_conf.systimer_rst_en = 1;
+    PCR.systimer_conf.systimer_rst_en = 0;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define systimer_ll_reset_register(...) do { \
+        (void)__DECLARE_RCC_RC_ATOMIC_ENV; \
+        systimer_ll_reset_register(__VA_ARGS__); \
+    } while(0)
+
+/********************** ETM *****************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_etm(systimer_dev_t *dev, bool en)
+{
+    dev->conf.etm_en = en;
+}
+
+/******************* Counter *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en)
+{
+    if (en) {
+        dev->conf.val |= 1 << (30 - counter_id);
+    } else {
+        dev->conf.val &= ~(1 << (30 - counter_id));
+    }
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(systimer_dev_t *dev, uint32_t counter_id, uint32_t cpu_id, bool can)
+{
+    if (can) {
+        dev->conf.val |= 1 << ((28 - counter_id * 2) - cpu_id);
+    } else {
+        dev->conf.val &= ~(1 << ((28 - counter_id * 2) - cpu_id));
+    }
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(systimer_dev_t *dev, uint32_t counter_id)
+{
+    dev->unit_op[counter_id].timer_unit_update = 1;
+}
+
+__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(systimer_dev_t *dev, uint32_t counter_id)
+{
+    return dev->unit_op[counter_id].timer_unit_value_valid;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(systimer_dev_t *dev, uint32_t counter_id, uint64_t value)
+{
+    dev->unit_load_val[counter_id].hi.timer_unit_load_hi = value >> 32;
+    dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF;
+}
+
+__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id)
+{
+    return dev->unit_val[counter_id].lo.timer_unit_value_lo;
+}
+
+__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(systimer_dev_t *dev, uint32_t counter_id)
+{
+    return dev->unit_val[counter_id].hi.timer_unit_value_hi;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(systimer_dev_t *dev, uint32_t counter_id)
+{
+    dev->unit_load[counter_id].val = 0x01;
+}
+
+/******************* Alarm *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value)
+{
+    dev->target_val[alarm_id].hi.timer_target_hi = value >> 32;
+    dev->target_val[alarm_id].lo.timer_target_lo = value & 0xFFFFFFFF;
+}
+
+__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    return ((uint64_t)(dev->target_val[alarm_id].hi.timer_target_hi) << 32) | dev->target_val[alarm_id].lo.timer_target_lo;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id)
+{
+    dev->target_conf[alarm_id].target_timer_unit_sel = counter_id;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->target_conf[alarm_id].target_period_mode = 0;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->target_conf[alarm_id].target_period_mode = 1;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period)
+{
+    HAL_ASSERT(period < (1 << 26));
+    dev->target_conf[alarm_id].target_period = period;
+}
+
+__attribute__((always_inline)) static inline uint32_t systimer_ll_get_alarm_period(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    return dev->target_conf[alarm_id].target_period;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->comp_load[alarm_id].val = 0x01;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en)
+{
+    if (en) {
+        dev->conf.val |= 1 << (24 - alarm_id);
+    } else {
+        dev->conf.val &= ~(1 << (24 - alarm_id));
+    }
+}
+
+/******************* Interrupt *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(systimer_dev_t *dev, uint32_t alarm_id, bool en)
+{
+    if (en) {
+        dev->int_ena.val |= 1 << alarm_id;
+    } else {
+        dev->int_ena.val &= ~(1 << alarm_id);
+    }
+}
+
+__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    return dev->int_st.val & (1 << alarm_id);
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->int_clr.val |= 1 << alarm_id;
+}
+
+#ifdef __cplusplus
+}
+#endif
@@ -9,7 +9,7 @@
 ***************************************/

 /* Functions */
-/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
+/* The following ROM functions are commented out because they're patched in the rom_patch.c */
 /* systimer_hal_init = 0x400003b8; */
 /* systimer_hal_deinit = 0x400003bc; */

@@ -0,0 +1,218 @@
+/*
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "soc/systimer_struct.h"
+#include "soc/clk_tree_defs.h"
+#include "soc/pcr_struct.h"
+#include "hal/assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// All these functions get invoked either from ISR or HAL that linked to IRAM.
+// Always inline these functions even no gcc optimization is applied.
+
+/******************* SYSTIMER LL CAPS *************************/
+#define SYSTIMER_LL_COUNTER_NUM             2  // Number of counter units
+#define SYSTIMER_LL_ALARM_NUM               3  // Number of alarm units
+#define SYSTIMER_LL_BIT_WIDTH_LO            32 // Bit width of systimer low part
+#define SYSTIMER_LL_BIT_WIDTH_HI            20 // Bit width of systimer high part
+#define SYSTIMER_LL_INT_LEVEL               1  // Systimer peripheral uses level interrupt
+#define SYSTIMER_LL_ALARM_MISS_COMPENSATE   1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
+#define SYSTIMER_LL_FIXED_DIVIDER           1  // Clock source divider is fixed to 2 when clock source is XTAL
+
+/******************* Clock *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
+{
+    dev->conf.clk_en = en;
+}
+
+// Set clock source: XTAL(default) or RC_FAST
+static inline void systimer_ll_set_clock_source(soc_periph_systimer_clk_src_t clk_src)
+{
+    PCR.systimer_func_clk_conf.systimer_func_clk_sel = (clk_src == SYSTIMER_CLK_SRC_RC_FAST) ? 1 : 0;
+}
+
+static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void)
+{
+    return (PCR.systimer_func_clk_conf.systimer_func_clk_sel == 1) ? SYSTIMER_CLK_SRC_RC_FAST : SYSTIMER_CLK_SRC_XTAL;
+}
+
+/**
+ * @brief Enable the bus clock for systimer module
+ *
+ * @param enable true to enable, false to disable
+ */
+static inline void systimer_ll_enable_bus_clock(bool enable)
+{
+    PCR.systimer_conf.systimer_clk_en = enable;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define systimer_ll_enable_bus_clock(...) do { \
+        (void)__DECLARE_RCC_RC_ATOMIC_ENV; \
+        systimer_ll_enable_bus_clock(__VA_ARGS__); \
+    } while(0)
+
+/**
+ * @brief Reset the systimer module
+ *
+ * @param group_id Group ID
+ */
+static inline void systimer_ll_reset_register(void)
+{
+    PCR.systimer_conf.systimer_rst_en = 1;
+    PCR.systimer_conf.systimer_rst_en = 0;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
+#define systimer_ll_reset_register(...) do { \
+        (void)__DECLARE_RCC_RC_ATOMIC_ENV; \
+        systimer_ll_reset_register(__VA_ARGS__); \
+    } while(0)
+
+/********************** ETM *****************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_etm(systimer_dev_t *dev, bool en)
+{
+    dev->conf.etm_en = en;
+}
+
+/******************* Counter *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en)
+{
+    if (en) {
+        dev->conf.val |= 1 << (30 - counter_id);
+    } else {
+        dev->conf.val &= ~(1 << (30 - counter_id));
+    }
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(systimer_dev_t *dev, uint32_t counter_id, uint32_t cpu_id, bool can)
+{
+    if (can) {
+        dev->conf.val |= 1 << ((28 - counter_id * 2) - cpu_id);
+    } else {
+        dev->conf.val &= ~(1 << ((28 - counter_id * 2) - cpu_id));
+    }
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(systimer_dev_t *dev, uint32_t counter_id)
+{
+    dev->unit_op[counter_id].timer_unit_update = 1;
+}
+
+__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(systimer_dev_t *dev, uint32_t counter_id)
+{
+    return dev->unit_op[counter_id].timer_unit_value_valid;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(systimer_dev_t *dev, uint32_t counter_id, uint64_t value)
+{
+    dev->unit_load_val[counter_id].hi.timer_unit_load_hi = value >> 32;
+    dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF;
+}
+
+__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id)
+{
+    return dev->unit_val[counter_id].lo.timer_unit_value_lo;
+}
+
+__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(systimer_dev_t *dev, uint32_t counter_id)
+{
+    return dev->unit_val[counter_id].hi.timer_unit_value_hi;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(systimer_dev_t *dev, uint32_t counter_id)
+{
+    dev->unit_load[counter_id].val = 0x01;
+}
+
+/******************* Alarm *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value)
+{
+    dev->target_val[alarm_id].hi.timer_target_hi = value >> 32;
+    dev->target_val[alarm_id].lo.timer_target_lo = value & 0xFFFFFFFF;
+}
+
+__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    return ((uint64_t)(dev->target_val[alarm_id].hi.timer_target_hi) << 32) | dev->target_val[alarm_id].lo.timer_target_lo;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id)
+{
+    dev->target_conf[alarm_id].target_timer_unit_sel = counter_id;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->target_conf[alarm_id].target_period_mode = 0;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->target_conf[alarm_id].target_period_mode = 1;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period)
+{
+    HAL_ASSERT(period < (1 << 26));
+    dev->target_conf[alarm_id].target_period = period;
+}
+
+__attribute__((always_inline)) static inline uint32_t systimer_ll_get_alarm_period(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    return dev->target_conf[alarm_id].target_period;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->comp_load[alarm_id].val = 0x01;
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en)
+{
+    if (en) {
+        dev->conf.val |= 1 << (24 - alarm_id);
+    } else {
+        dev->conf.val &= ~(1 << (24 - alarm_id));
+    }
+}
+
+/******************* Interrupt *************************/
+
+__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(systimer_dev_t *dev, uint32_t alarm_id, bool en)
+{
+    if (en) {
+        dev->int_ena.val |= 1 << alarm_id;
+    } else {
+        dev->int_ena.val &= ~(1 << alarm_id);
+    }
+}
+
+__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    return dev->int_st.val & (1 << alarm_id);
+}
+
+__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(systimer_dev_t *dev, uint32_t alarm_id)
+{
+    dev->int_clr.val |= 1 << alarm_id;
+}
+
+#ifdef __cplusplus
+}
+#endif
@@ -9,7 +9,7 @@
 ***************************************/

 /* Functions */
-/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
+/* The following ROM functions are commented out because they're patched in the rom_patch.c */
 /* systimer_hal_init = 0x400003b8; */
 /* systimer_hal_deinit = 0x400003bc; */
 systimer_hal_set_tick_rate_ops = 0x400003c0;
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -19,6 +19,15 @@ extern "C" {
 // All these functions get invoked either from ISR or HAL that linked to IRAM.
 // Always inline these functions even no gcc optimization is applied.

+/******************* SYSTIMER LL CAPS *************************/
+#define SYSTIMER_LL_COUNTER_NUM             2  // Number of counter units
+#define SYSTIMER_LL_ALARM_NUM               3  // Number of alarm units
+#define SYSTIMER_LL_BIT_WIDTH_LO            32 // Bit width of systimer low part
+#define SYSTIMER_LL_BIT_WIDTH_HI            20 // Bit width of systimer high part
+#define SYSTIMER_LL_INT_LEVEL               1  // Systimer peripheral uses level interrupt
+#define SYSTIMER_LL_ALARM_MISS_COMPENSATE   1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
+#define SYSTIMER_LL_FIXED_DIVIDER           1  // Clock source divider is fixed: 2.5
+
 /******************* Clock *************************/

 __attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
@@ -18,7 +18,7 @@
 ***************************************/

 /* Functions */
-/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
+/* The following ROM functions are commented out because they're patched in the rom_patch.c */
 /* systimer_hal_init = 0x4000036c; */
 /* systimer_hal_deinit = 0x40000370; */

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -19,6 +19,15 @@ extern "C" {
 // All these functions get invoked either from ISR or HAL that linked to IRAM.
 // Always inline these functions even no gcc optimization is applied.

+/******************* SYSTIMER LL CAPS *************************/
+#define SYSTIMER_LL_COUNTER_NUM             2  // Number of counter units
+#define SYSTIMER_LL_ALARM_NUM               3  // Number of alarm units
+#define SYSTIMER_LL_BIT_WIDTH_LO            32 // Bit width of systimer low part
+#define SYSTIMER_LL_BIT_WIDTH_HI            20 // Bit width of systimer high part
+#define SYSTIMER_LL_INT_LEVEL               1  // Systimer peripheral uses level interrupt
+#define SYSTIMER_LL_ALARM_MISS_COMPENSATE   1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
+#define SYSTIMER_LL_FIXED_DIVIDER           1  // Clock source divider is fixed: 2.5
+
 /******************* Clock *************************/

 __attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
@@ -10,7 +10,7 @@
 ***************************************/

 /* Functions */
-/* The following ROM functions are commented out because they're patched in the esp_rom_systimer.c */
+/* The following ROM functions are commented out because they're patched in the rom_patch.c */
 /* systimer_hal_init = 0x4fc00228; */
 /* systimer_hal_deinit = 0x4fc0022c; */
 systimer_hal_set_tick_rate_ops = 0x4fc00230;
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -19,6 +19,12 @@ extern "C" {
 // All these functions get invoked either from ISR or HAL that linked to IRAM.
 // Always inline these functions even no gcc optimization is applied.

+/******************* SYSTIMER LL CAPS *************************/
+#define SYSTIMER_LL_COUNTER_NUM             1  // Number of counter units
+#define SYSTIMER_LL_ALARM_NUM               3  // Number of alarm units
+#define SYSTIMER_LL_BIT_WIDTH_LO            32 // Bit width of systimer low part
+#define SYSTIMER_LL_BIT_WIDTH_HI            32 // Bit width of systimer high part
+
 /******************* Clock *************************/

 __attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -19,6 +19,15 @@ extern "C" {
 // All these functions get invoked either from ISR or HAL that linked to IRAM.
 // Always inline these functions even no gcc optimization is applied.

+/******************* SYSTIMER LL CAPS *************************/
+#define SYSTIMER_LL_COUNTER_NUM             2  // Number of counter units
+#define SYSTIMER_LL_ALARM_NUM               3  // Number of alarm units
+#define SYSTIMER_LL_BIT_WIDTH_LO            32 // Bit width of systimer low part
+#define SYSTIMER_LL_BIT_WIDTH_HI            20 // Bit width of systimer high part
+#define SYSTIMER_LL_INT_LEVEL               1  // Systimer peripheral uses level interrupt
+#define SYSTIMER_LL_ALARM_MISS_COMPENSATE   1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
+#define SYSTIMER_LL_FIXED_DIVIDER           1  // Clock source divider is fixed: 2.5
+
 /******************* Clock *************************/

 __attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2025-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -21,6 +21,15 @@ extern "C" {

 // TODO: [ESP32S31] IDF-14693

+/******************* SYSTIMER LL CAPS *************************/
+#define SYSTIMER_LL_COUNTER_NUM             2  // Number of counter units
+#define SYSTIMER_LL_ALARM_NUM               3  // Number of alarm units
+#define SYSTIMER_LL_BIT_WIDTH_LO            32 // Bit width of systimer low part
+#define SYSTIMER_LL_BIT_WIDTH_HI            20 // Bit width of systimer high part
+#define SYSTIMER_LL_INT_LEVEL               1  // Systimer peripheral uses level interrupt
+#define SYSTIMER_LL_ALARM_MISS_COMPENSATE   1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
+#define SYSTIMER_LL_FIXED_DIVIDER           1  // Clock source divider is fixed: 2.5
+
 /******************* Clock *************************/

 __attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -11,6 +11,9 @@
 #include "hal/systimer_types.h"
 #include "soc/soc_caps.h"
 #include "soc/clk_tree_defs.h"
+#if SOC_SYSTIMER_SUPPORTED
+#include "hal/systimer_ll.h"
+#endif

 #ifdef __cplusplus
 extern "C" {
@@ -119,7 +122,7 @@ void systimer_hal_connect_alarm_counter(systimer_hal_context_t *hal, uint32_t al
 */
 void systimer_hal_counter_can_stall_by_cpu(systimer_hal_context_t *hal, uint32_t counter_id, uint32_t cpu_id, bool can);

-#if !SOC_SYSTIMER_FIXED_DIVIDER
+#if !SYSTIMER_LL_FIXED_DIVIDER
 /**
 * @brief set increase steps for systimer counter on different clock source
 */
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -19,20 +19,20 @@ extern "C" {
 *
 */
 #if SOC_SYSTIMER_SUPPORTED
+#include "hal/systimer_ll.h"
 typedef struct {
    union {
        struct {
-            uint64_t lo : SOC_SYSTIMER_BIT_WIDTH_LO; /*!< Low part of counter value */
-            uint64_t hi : SOC_SYSTIMER_BIT_WIDTH_HI; /*!< High part of counter value */
-#if (SOC_SYSTIMER_BIT_WIDTH_LO  + SOC_SYSTIMER_BIT_WIDTH_HI) < 64
-            uint64_t reserved: (64 - (SOC_SYSTIMER_BIT_WIDTH_LO  + SOC_SYSTIMER_BIT_WIDTH_HI));
+            uint64_t lo : SYSTIMER_LL_BIT_WIDTH_LO; /*!< Low part of counter value */
+            uint64_t hi : SYSTIMER_LL_BIT_WIDTH_HI; /*!< High part of counter value */
+#if (SYSTIMER_LL_BIT_WIDTH_LO + SYSTIMER_LL_BIT_WIDTH_HI) < 64
+            uint64_t reserved: (64 - (SYSTIMER_LL_BIT_WIDTH_LO + SYSTIMER_LL_BIT_WIDTH_HI));
 #endif
        };
        uint64_t val; /*!< counter value */
    };
 } systimer_counter_value_t;

-
 /** @cond */
 ESP_STATIC_ASSERT(sizeof(systimer_counter_value_t) == 8, "systimer_counter_value_t should occupy 8 bytes in memory");
 /** @endcond */
@@ -0,0 +1,6 @@
+[mapping:esp_hal_systimer]
+archive: libesp_hal_systimer.a
+entries:
+    if SOC_SYSTIMER_SUPPORTED = y:
+        # All systimer HAL code must be in IRAM for ISR safety and cache-disabled operation
+        * (noflash)
@@ -0,0 +1,37 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @brief ROM patch for systimer HAL
+ *
+ * Some chips have systimer HAL implementations in ROM that require patches.
+ * This file provides the necessary patches when ROM implementation is used.
+ *
+ * For chips with ESP_ROM_SYSTIMER_INIT_PATCH defined (e.g., ESP32-C5, ESP32-C6,
+ * ESP32-H2, ESP32-P4), the ROM systimer_hal_init/deinit functions do not
+ * enable ETM, so we need to patch them here.
+ */
+
+#include <stddef.h>
+#include "esp_rom_caps.h"
+#include "hal/systimer_hal.h"
+#include "hal/systimer_ll.h"
+
+#if ESP_ROM_SYSTIMER_INIT_PATCH
+void systimer_hal_init(systimer_hal_context_t *hal)
+{
+    hal->dev = &SYSTIMER;
+    systimer_ll_enable_clock(hal->dev, true);
+    systimer_ll_enable_etm(&SYSTIMER, true);
+}
+
+void systimer_hal_deinit(systimer_hal_context_t *hal)
+{
+    systimer_ll_enable_etm(&SYSTIMER, false);
+    systimer_ll_enable_clock(hal->dev, false);
+    hal->dev = NULL;
+}
+#endif // ESP_ROM_SYSTIMER_INIT_PATCH
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2021-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Apache-2.0
 */
@@ -8,11 +8,9 @@
 #include <sys/param.h>
 #include "soc/soc_caps.h"
 #include "hal/systimer_hal.h"
-#include "hal/systimer_ll.h"
 #include "hal/systimer_types.h"
 #include "hal/assert.h"

-
 void systimer_hal_init(systimer_hal_context_t *hal)
 {
    hal->dev = &SYSTIMER;
@@ -74,7 +72,7 @@ uint64_t systimer_hal_get_time(systimer_hal_context_t *hal, uint32_t counter_id)
    return hal->ticks_to_us(systimer_hal_get_counter_value(hal, counter_id));
 }

-#if SOC_SYSTIMER_ALARM_MISS_COMPENSATE
+#if SYSTIMER_LL_ALARM_MISS_COMPENSATE
 void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_id, uint64_t target)
 {
    systimer_counter_value_t alarm = {
@@ -86,7 +84,7 @@ void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_i
    systimer_ll_enable_alarm(hal->dev, alarm_id, true);
 }

-#else // SOC_SYSTIMER_ALARM_MISS_COMPENSATE
+#else // SYSTIMER_LL_ALARM_MISS_COMPENSATE

 void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_id, uint64_t timestamp)
 {
@@ -110,7 +108,7 @@ void systimer_hal_set_alarm_target(systimer_hal_context_t *hal, uint32_t alarm_i
        }
    } while (1);
 }
-#endif // SOC_SYSTIMER_ALARM_MISS_COMPENSATE
+#endif // SYSTIMER_LL_ALARM_MISS_COMPENSATE

 void systimer_hal_set_alarm_period(systimer_hal_context_t *hal, uint32_t alarm_id, uint32_t period)
 {
@@ -168,7 +166,7 @@ void systimer_hal_counter_can_stall_by_cpu(systimer_hal_context_t *hal, uint32_t
    systimer_ll_counter_can_stall_by_cpu(hal->dev, counter_id, cpu_id, can);
 }

-#if !SOC_SYSTIMER_FIXED_DIVIDER
+#if !SYSTIMER_LL_FIXED_DIVIDER

 void systimer_hal_set_steps_per_tick(systimer_hal_context_t *hal, int clock_source, uint32_t steps)
 {
@@ -203,4 +201,4 @@ void systimer_hal_on_apb_freq_update(systimer_hal_context_t *hal, uint32_t apb_t
        systimer_ll_set_step_for_xtal(hal->dev, hal->us_to_ticks(1) / apb_ticks_per_us);
    }
 }
-#endif // !SOC_SYSTIMER_FIXED_DIVIDER
+#endif // !SYSTIMER_LL_FIXED_DIVIDER
@@ -0,0 +1,9 @@
+# This is the project CMakeLists.txt file for the test subproject
+cmake_minimum_required(VERSION 3.22)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+
+# "Trim" the build. Include the minimal set of components, main, and anything it depends on.
+set(COMPONENTS main)
+
+project(systimer_rom_impl)
@@ -0,0 +1,26 @@
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
+
+# esp_hal_systimer ROM implementation test app
+
+This test app verifies that the systimer HAL is correctly linked from either ROM or the component implementation, depending on `CONFIG_HAL_SYSTIMER_USE_ROM_IMPL`.
+
+## Configurations
+
+- **rom_impl**: Builds with `CONFIG_HAL_SYSTIMER_USE_ROM_IMPL=y`, tests that `systimer_hal_get_counter_value` is in ROM.
+- **no_rom_impl**: Builds with `CONFIG_HAL_SYSTIMER_USE_ROM_IMPL=n`, tests that the function is not in ROM.
+
+## Building and running
+
+```bash
+idf.py set-target <target>
+idf.py build flash monitor
+```
+
+To run with pytest:
+
+```bash
+idf.py set-target <target>
+idf.py build
+pytest --target=<target>
+```
@@ -0,0 +1,7 @@
+set(srcs "test_app_main.c")
+
+# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
+# the component can be registered as WHOLE_ARCHIVE
+idf_component_register(SRCS ${srcs}
+                       PRIV_REQUIRES unity esp_hal_systimer
+                       WHOLE_ARCHIVE)
@@ -0,0 +1,62 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+
+#include "unity.h"
+#include "unity_test_runner.h"
+#include "esp_heap_caps.h"
+#include "soc/soc.h"
+#include "soc/soc_caps.h"
+#include "hal/systimer_hal.h"
+
+static bool fn_in_rom(void *fn)
+{
+    const int fnaddr = (int)fn;
+    return (fnaddr >= SOC_IROM_MASK_LOW && fnaddr < SOC_IROM_MASK_HIGH);
+}
+
+#if CONFIG_HAL_SYSTIMER_USE_ROM_IMPL
+TEST_CASE("Test that systimer implementation from ROM is used", "[systimer-rom-impl]")
+{
+    TEST_ASSERT_TRUE(fn_in_rom(systimer_hal_get_counter_value));
+}
+
+#else
+TEST_CASE("Test that systimer implementation from ROM is NOT used", "[systimer-rom-impl]")
+{
+    TEST_ASSERT_FALSE(fn_in_rom(systimer_hal_get_counter_value));
+}
+#endif // CONFIG_HAL_SYSTIMER_USE_ROM_IMPL
+
+#define TEST_MEMORY_LEAK_THRESHOLD (-100)
+
+static size_t before_free_8bit;
+static size_t before_free_32bit;
+
+static void check_leak(size_t before_free, size_t after_free, const char *type)
+{
+    ssize_t delta = after_free - before_free;
+    printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta);
+    TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak");
+}
+
+void setUp(void)
+{
+    before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
+    before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
+}
+
+void tearDown(void)
+{
+    size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
+    size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
+    check_leak(before_free_8bit, after_free_8bit, "8BIT");
+    check_leak(before_free_32bit, after_free_32bit, "32BIT");
+}
+
+void app_main(void)
+{
+    unity_run_menu();
+}
@@ -0,0 +1,20 @@
+# SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+import pytest
+from pytest_embedded import Dut
+from pytest_embedded_idf.utils import idf_parametrize
+from pytest_embedded_idf.utils import soc_filtered_targets
+
+
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'no_rom_impl',
+        'rom_impl',
+    ],
+    indirect=True,
+)
+@idf_parametrize('target', soc_filtered_targets('SOC_SYSTIMER_SUPPORTED == 1'), indirect=['target'])
+def test_esp_hal_systimer_rom_impl(dut: Dut) -> None:
+    dut.run_all_single_board_cases()
@@ -0,0 +1 @@
+CONFIG_HAL_SYSTIMER_USE_ROM_IMPL=n
@@ -0,0 +1 @@
+CONFIG_HAL_SYSTIMER_USE_ROM_IMPL=y
@@ -0,0 +1,7 @@
+# Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
+
+components/esp_hal_wdt/test_apps/wdt_rom_impl:
+  disable:
+    - if: SOC_WDT_SUPPORTED != 1
+  depends_components:
+    - esp_hal_wdt
@@ -0,0 +1,9 @@
+# This is the project CMakeLists.txt file for the test subproject
+cmake_minimum_required(VERSION 3.22)
+
+include($ENV{IDF_PATH}/tools/cmake/project.cmake)
+
+# "Trim" the build. Include the minimal set of components, main, and anything it depends on.
+set(COMPONENTS main)
+
+project(wdt_rom_impl)
@@ -0,0 +1,26 @@
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+
+# esp_hal_wdt ROM implementation test app
+
+This test app verifies that the WDT HAL is correctly linked from either ROM or the component implementation, depending on `CONFIG_HAL_WDT_USE_ROM_IMPL`.
+
+## Configurations
+
+- **rom_impl**: Builds with `CONFIG_HAL_WDT_USE_ROM_IMPL=y`, tests that `wdt_hal_feed` is in ROM.
+- **no_rom_impl**: Builds with `CONFIG_HAL_WDT_USE_ROM_IMPL=n`, tests that the function is not in ROM.
+
+## Building and running
+
+```bash
+idf.py set-target <target>
+idf.py build flash monitor
+```
+
+To run with pytest:
+
+```bash
+idf.py set-target <target>
+idf.py build
+pytest --target=<target>
+```
@@ -0,0 +1,7 @@
+set(srcs "test_app_main.c")
+
+# In order for the cases defined by `TEST_CASE` to be linked into the final elf,
+# the component can be registered as WHOLE_ARCHIVE
+idf_component_register(SRCS ${srcs}
+                       PRIV_REQUIRES unity esp_hal_wdt
+                       WHOLE_ARCHIVE)
@@ -0,0 +1,61 @@
+/*
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Unlicense OR CC0-1.0
+ */
+
+#include "unity.h"
+#include "unity_test_runner.h"
+#include "esp_heap_caps.h"
+#include "soc/soc_caps.h"
+#include "hal/wdt_hal.h"
+
+static bool fn_in_rom(void *fn)
+{
+    const int fnaddr = (int)fn;
+    return (fnaddr >= SOC_IROM_MASK_LOW && fnaddr < SOC_IROM_MASK_HIGH);
+}
+
+#if CONFIG_HAL_WDT_USE_ROM_IMPL
+TEST_CASE("Test that WDT implementation from ROM is used", "[wdt-rom-impl]")
+{
+    TEST_ASSERT_TRUE(fn_in_rom(wdt_hal_feed));
+}
+
+#else
+TEST_CASE("Test that WDT implementation from ROM is NOT used", "[wdt-rom-impl]")
+{
+    TEST_ASSERT_FALSE(fn_in_rom(wdt_hal_feed));
+}
+#endif // CONFIG_HAL_WDT_USE_ROM_IMPL
+
+#define TEST_MEMORY_LEAK_THRESHOLD (-100)
+
+static size_t before_free_8bit;
+static size_t before_free_32bit;
+
+static void check_leak(size_t before_free, size_t after_free, const char *type)
+{
+    ssize_t delta = after_free - before_free;
+    printf("MALLOC_CAP_%s: Before %u bytes free, After %u bytes free (delta %d)\n", type, before_free, after_free, delta);
+    TEST_ASSERT_MESSAGE(delta >= TEST_MEMORY_LEAK_THRESHOLD, "memory leak");
+}
+
+void setUp(void)
+{
+    before_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
+    before_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
+}
+
+void tearDown(void)
+{
+    size_t after_free_8bit = heap_caps_get_free_size(MALLOC_CAP_8BIT);
+    size_t after_free_32bit = heap_caps_get_free_size(MALLOC_CAP_32BIT);
+    check_leak(before_free_8bit, after_free_8bit, "8BIT");
+    check_leak(before_free_32bit, after_free_32bit, "32BIT");
+}
+
+void app_main(void)
+{
+    unity_run_menu();
+}
@@ -0,0 +1,20 @@
+# SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
+# SPDX-License-Identifier: CC0-1.0
+import pytest
+from pytest_embedded import Dut
+from pytest_embedded_idf.utils import idf_parametrize
+from pytest_embedded_idf.utils import soc_filtered_targets
+
+
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'no_rom_impl',
+        'rom_impl',
+    ],
+    indirect=True,
+)
+@idf_parametrize('target', soc_filtered_targets('SOC_WDT_SUPPORTED == 1'), indirect=['target'])
+def test_esp_hal_wdt_rom_impl(dut: Dut) -> None:
+    dut.run_all_single_board_cases()
@@ -0,0 +1 @@
+CONFIG_HAL_WDT_USE_ROM_IMPL=n
@@ -0,0 +1 @@
+CONFIG_HAL_WDT_USE_ROM_IMPL=y
@@ -12,7 +12,7 @@ endif()
 set(requires esp_hal_gpio esp_hal_usb esp_hal_pmu)
 # only esp_hw_support/adc_share_hw_ctrl.c requires efuse component
 set(priv_requires efuse spi_flash bootloader_support esp_hal_wdt esp_hal_rtc_timer
-    esp_hal_clock esp_hal_security)
+    esp_hal_clock esp_hal_security esp_hal_systimer)

 set(srcs "cpu.c" "port/${IDF_TARGET}/esp_cpu_intr.c" "esp_memory_utils.c" "port/${IDF_TARGET}/cpu_region_protect.c")
 if(NOT non_os_build)
@@ -603,7 +603,7 @@ static SLEEP_FN_ATTR void suspend_timers(uint32_t sleep_flags) {
        }
 #endif
 #if SOC_SLEEP_SYSTIMER_STALL_WORKAROUND
-        for (uint32_t counter_id = 0; counter_id < SOC_SYSTIMER_COUNTER_NUM; ++counter_id) {
+        for (uint32_t counter_id = 0; counter_id < SYSTIMER_LL_COUNTER_NUM; ++counter_id) {
            systimer_ll_enable_counter(&SYSTIMER, counter_id, false);
        }
 #endif
@@ -614,7 +614,7 @@ static SLEEP_FN_ATTR void suspend_timers(uint32_t sleep_flags) {
 static SLEEP_FN_ATTR void resume_timers(uint32_t sleep_flags) {
    if (!(sleep_flags & RTC_SLEEP_PD_XTAL)) {
 #if SOC_SLEEP_SYSTIMER_STALL_WORKAROUND
-        for (uint32_t counter_id = 0; counter_id < SOC_SYSTIMER_COUNTER_NUM; ++counter_id) {
+        for (uint32_t counter_id = 0; counter_id < SYSTIMER_LL_COUNTER_NUM; ++counter_id) {
            systimer_ll_enable_counter(&SYSTIMER, counter_id, true);
        }
 #endif
@@ -51,10 +51,6 @@ if(CONFIG_IDF_TARGET_ARCH_XTENSA)
    list(APPEND sources "patches/esp_rom_longjmp.S")
 endif()

-if(CONFIG_SOC_SYSTIMER_SUPPORTED)
-    list(APPEND sources "patches/esp_rom_systimer.c")
-endif()
-
 if(CONFIG_ESP_ROM_CLIC_INT_TYPE_PATCH)
    list(APPEND sources "patches/esp_rom_clic.c")
 endif()
@@ -126,10 +122,6 @@ endif()

 # Common API which is linked both for bootloader and app builds

-if(CONFIG_HAL_SYSTIMER_USE_ROM_IMPL)
-    rom_linker_script("systimer")
-endif()
-
 if(CONFIG_ESP_ROM_HAS_VERSION)
    rom_linker_script("version")
 endif()
@@ -9,5 +9,3 @@ entries:
        esp_rom_cache_esp32s2_esp32s3 (noflash)
    if ESP_ROM_HAS_CACHE_WRITEBACK_BUG = y:
        esp_rom_cache_writeback_esp32s3 (noflash)
-    if SOC_SYSTIMER_SUPPORTED = y:
-        esp_rom_systimer (noflash)
@@ -9,9 +9,8 @@ components/esp_rom/test_apps/linux_rom_apis:
 components/esp_rom/test_apps/rom_impl_components:
  disable:
    # For ROM impl build tests, disable them if none of the tested features are supported in the ROM
-    - if: CONFIG_NAME == "rom_impl_components" and ((ESP_ROM_HAS_HAL_WDT != 1  and ESP_ROM_HAS_HAL_SYSTIMER != 1) and (ESP_ROM_HAS_HEAP_TLSF != 1 and ESP_ROM_HAS_SPI_FLASH != 1))
-    - if: CONFIG_NAME == "no_rom_impl_components" and ((ESP_ROM_HAS_HAL_WDT != 1 and ESP_ROM_HAS_HAL_SYSTIMER != 1) and (ESP_ROM_HAS_HEAP_TLSF != 1 and ESP_ROM_HAS_SPI_FLASH != 1))
-    - if: SOC_WDT_SUPPORTED != 1
+    - if: CONFIG_NAME == "rom_impl_components" and (ESP_ROM_HAS_HEAP_TLSF != 1 and ESP_ROM_HAS_SPI_FLASH != 1)
+    - if: CONFIG_NAME == "no_rom_impl_components" and (ESP_ROM_HAS_HEAP_TLSF != 1 and ESP_ROM_HAS_SPI_FLASH != 1)
  depends_components:
    - esp_rom

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 | ESP32-S31 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- | -------- | --------- |
@@ -3,5 +3,5 @@ set(srcs "test_app_main.c")
 # In order for the cases defined by `TEST_CASE` to be linked into the final elf,
 # the component can be registered as WHOLE_ARCHIVE
 idf_component_register(SRCS ${srcs}
-                       PRIV_REQUIRES unity esp_hal_wdt
+                       PRIV_REQUIRES unity
                       WHOLE_ARCHIVE)
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
 *
 * SPDX-License-Identifier: Unlicense OR CC0-1.0
 */
@@ -7,9 +7,8 @@
 #include "unity.h"
 #include "unity_test_runner.h"
 #include "esp_heap_caps.h"
+#include "soc/soc.h"
 #include "soc/soc_caps.h"
-#include "hal/wdt_hal.h"
-#include "hal/systimer_hal.h"

 static bool fn_in_rom(void *fn)
 {
@@ -17,33 +16,6 @@ static bool fn_in_rom(void *fn)
    return (fnaddr >= SOC_IROM_MASK_LOW && fnaddr < SOC_IROM_MASK_HIGH);
 }

-#if CONFIG_HAL_WDT_USE_ROM_IMPL
-TEST_CASE("Test that WDT implementation from ROM is used", "[rom-impl-components]")
-{
-    TEST_ASSERT_TRUE(fn_in_rom(wdt_hal_feed));
-}
-
-#else
-TEST_CASE("Test that WDT implementation from ROM is NOT used", "[rom-impl-components]")
-{
-    TEST_ASSERT_FALSE(fn_in_rom(wdt_hal_feed));
-}
-#endif // CONFIG_HAL_WDT_USE_ROM_IMPL
-
-
-#if CONFIG_HAL_SYSTIMER_USE_ROM_IMPL
-TEST_CASE("Test that systimer implementation from ROM is used", "[rom-impl-components]")
-{
-    TEST_ASSERT_TRUE(fn_in_rom(systimer_hal_get_counter_value));
-}
-
-#else
-TEST_CASE("Test that systimer implementation from ROM is NOT used", "[rom-impl-components]")
-{
-    TEST_ASSERT_FALSE(fn_in_rom(systimer_hal_get_counter_value));
-}
-#endif // CONFIG_HAL_SYSTIMER_USE_ROM_IMPL
-
 extern uint32_t tlsf_create;
 #if CONFIG_HEAP_TLSF_USE_ROM_IMPL
 TEST_CASE("Test that HEAP implementation from ROM is used", "[rom-impl-components]")
@@ -1,5 +1,3 @@
-CONFIG_HAL_WDT_USE_ROM_IMPL=n
-CONFIG_HAL_SYSTIMER_USE_ROM_IMPL=n
 CONFIG_HEAP_TLSF_USE_ROM_IMPL=n
 CONFIG_SPI_FLASH_ROM_IMPL=n

@@ -1,5 +1,3 @@
-CONFIG_HAL_WDT_USE_ROM_IMPL=y
-CONFIG_HAL_SYSTIMER_USE_ROM_IMPL=y
 CONFIG_HEAP_TLSF_USE_ROM_IMPL=y
 CONFIG_SPI_FLASH_ROM_IMPL=y

@@ -21,7 +21,7 @@ else()

    idf_component_register(SRCS "${srcs}"
                           INCLUDE_DIRS include
-                           PRIV_REQUIRES esp_hal_timg
+                           PRIV_REQUIRES esp_hal_timg esp_hal_systimer
                           PRIV_INCLUDE_DIRS private_include)

    # Forces the linker to include esp_timer_init.c
@@ -162,7 +162,7 @@ esp_err_t esp_timer_impl_early_init(void)
    systimer_hal_init(&systimer_hal);
    systimer_hal_set_tick_rate_ops(&systimer_hal, &ops);

-#if !SOC_SYSTIMER_FIXED_DIVIDER
+#if !SYSTIMER_LL_FIXED_DIVIDER
    assert(esp_clk_xtal_freq() == (40 * 1000000) &&
           "update the step for xtal to support other XTAL:APB frequency ratios");
    systimer_hal_set_steps_per_tick(&systimer_hal, 0, 2); // for xtal
@@ -190,7 +190,7 @@ esp_err_t esp_timer_impl_init(intr_handler_t alarm_handler)

    int isr_flags = ESP_INTR_FLAG_INTRDISABLED
                    | ((1 << CONFIG_ESP_TIMER_INTERRUPT_LEVEL) & ESP_INTR_FLAG_LEVELMASK)
-#if !SOC_SYSTIMER_INT_LEVEL
+#if !SYSTIMER_LL_INT_LEVEL
                    | ESP_INTR_FLAG_EDGE
 #endif
 #if CONFIG_ESP_TIMER_IN_IRAM
@@ -50,6 +50,10 @@ set(private_include_dirs "")
 set(private_requirements "")
 set(ldfragments "")

+# ---------------------------------------------------- Set Private Requirements ----------------------------------------
+
+list(APPEND private_requirements esp_hal_systimer)
+
 # ---------------------------------------------------- Set Sources -----------------------------------------------------

 # Add common source files
@@ -44,7 +44,7 @@ BaseType_t xPortSysTickHandler(void);
 #include "esp_private/pm_trace.h"
 #endif //CONFIG_PM_TRACE

-_Static_assert(SOC_CPU_CORES_NUM <= SOC_SYSTIMER_ALARM_NUM - 1, "the number of cores must match the number of core alarms in SYSTIMER");
+_Static_assert(SOC_CPU_CORES_NUM <= SYSTIMER_LL_ALARM_NUM - 1, "the number of cores must match the number of core alarms in SYSTIMER");

 void SysTickIsrHandler(void *arg);

@@ -36,10 +36,6 @@ endif()
 if(NOT esp_tee_build AND NOT BOOTLOADER_BUILD)
    list(APPEND srcs "color_hal.c")

-    if(CONFIG_SOC_SYSTIMER_SUPPORTED AND NOT CONFIG_HAL_SYSTIMER_USE_ROM_IMPL)
-        list(APPEND srcs "systimer_hal.c")
-    endif()
-
    if(CONFIG_SOC_ETM_SUPPORTED)
        list(APPEND srcs "etm_hal.c" "${target}/etm_periph.c")
    endif()
@@ -65,21 +65,10 @@ menu "Hardware Abstraction Layer (HAL) and Low Level (LL)"
        default 4 if HAL_LOG_LEVEL_DEBUG
        default 5 if HAL_LOG_LEVEL_VERBOSE

-    config HAL_SYSTIMER_USE_ROM_IMPL
-        bool "Use ROM implementation of SysTimer HAL driver"
-        depends on ESP_ROM_HAS_HAL_SYSTIMER
-        default y
-        help
-            Enable this flag to use HAL functions from ROM instead of ESP-IDF.
-
-            If keeping this as "n" in your project, you will have less free IRAM.
-            If making this as "y" in your project, you will increase free IRAM,
-            but you will lose the possibility to debug this module, and some new
-            features will be added and bugs will be fixed in the IDF source
-            but cannot be synced to ROM.
-
    orsource "../esp_hal_wdt/Kconfig.hal_wdt"

+    orsource "../esp_hal_systimer/Kconfig.hal_systimer"
+
    orsource "../esp_hal_gpio/Kconfig.hal_gpio"

    orsource "../esp_hal_security/Kconfig.hal_security"
@@ -1,210 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "soc/systimer_struct.h"
-#include "soc/clk_tree_defs.h"
-#include "soc/pcr_struct.h"
-#include "hal/assert.h"
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// All these functions get invoked either from ISR or HAL that linked to IRAM.
-// Always inline these functions even no gcc optimization is applied.
-
-/******************* Clock *************************/
-
-__attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
-{
-    dev->conf.clk_en = en;
-}
-
-// Set clock source: XTAL(default) or RC_FAST
-static inline void systimer_ll_set_clock_source(soc_periph_systimer_clk_src_t clk_src)
-{
-    PCR.systimer_func_clk_conf.systimer_func_clk_sel = (clk_src == SYSTIMER_CLK_SRC_RC_FAST) ? 1 : 0;
-}
-
-static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void)
-{
-    return (PCR.systimer_func_clk_conf.systimer_func_clk_sel == 1) ? SYSTIMER_CLK_SRC_RC_FAST : SYSTIMER_CLK_SRC_XTAL;
-}
-
-/**
- * @brief Enable the bus clock for systimer module
- *
- * @param enable true to enable, false to disable
- */
-static inline void systimer_ll_enable_bus_clock(bool enable)
-{
-    PCR.systimer_conf.systimer_clk_en = enable;
-}
-
-/// use a macro to wrap the function, force the caller to use it in a critical section
-/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
-#define systimer_ll_enable_bus_clock(...) do { \
-        (void)__DECLARE_RCC_RC_ATOMIC_ENV; \
-        systimer_ll_enable_bus_clock(__VA_ARGS__); \
-    } while(0)
-
-/**
- * @brief Reset the systimer module
- *
- * @param group_id Group ID
- */
-static inline void systimer_ll_reset_register(void)
-{
-    PCR.systimer_conf.systimer_rst_en = 1;
-    PCR.systimer_conf.systimer_rst_en = 0;
-}
-
-/// use a macro to wrap the function, force the caller to use it in a critical section
-/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
-#define systimer_ll_reset_register(...) do { \
-        (void)__DECLARE_RCC_RC_ATOMIC_ENV; \
-        systimer_ll_reset_register(__VA_ARGS__); \
-    } while(0)
-
-/********************** ETM *****************************/
-
-__attribute__((always_inline)) static inline void systimer_ll_enable_etm(systimer_dev_t *dev, bool en)
-{
-    dev->conf.etm_en = en;
-}
-
-/******************* Counter *************************/
-
-__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en)
-{
-    if (en) {
-        dev->conf.val |= 1 << (30 - counter_id);
-    } else {
-        dev->conf.val &= ~(1 << (30 - counter_id));
-    }
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(systimer_dev_t *dev, uint32_t counter_id, uint32_t cpu_id, bool can)
-{
-    if (can) {
-        dev->conf.val |= 1 << ((28 - counter_id * 2) - cpu_id);
-    } else {
-        dev->conf.val &= ~(1 << ((28 - counter_id * 2) - cpu_id));
-    }
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(systimer_dev_t *dev, uint32_t counter_id)
-{
-    dev->unit_op[counter_id].timer_unit_update = 1;
-}
-
-__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(systimer_dev_t *dev, uint32_t counter_id)
-{
-    return dev->unit_op[counter_id].timer_unit_value_valid;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(systimer_dev_t *dev, uint32_t counter_id, uint64_t value)
-{
-    dev->unit_load_val[counter_id].hi.timer_unit_load_hi = value >> 32;
-    dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF;
-}
-
-__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id)
-{
-    return dev->unit_val[counter_id].lo.timer_unit_value_lo;
-}
-
-__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(systimer_dev_t *dev, uint32_t counter_id)
-{
-    return dev->unit_val[counter_id].hi.timer_unit_value_hi;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(systimer_dev_t *dev, uint32_t counter_id)
-{
-    dev->unit_load[counter_id].val = 0x01;
-}
-
-/******************* Alarm *************************/
-
-__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value)
-{
-    dev->target_val[alarm_id].hi.timer_target_hi = value >> 32;
-    dev->target_val[alarm_id].lo.timer_target_lo = value & 0xFFFFFFFF;
-}
-
-__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(systimer_dev_t *dev, uint32_t alarm_id)
-{
-    return ((uint64_t)(dev->target_val[alarm_id].hi.timer_target_hi) << 32) | dev->target_val[alarm_id].lo.timer_target_lo;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id)
-{
-    dev->target_conf[alarm_id].target_timer_unit_sel = counter_id;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(systimer_dev_t *dev, uint32_t alarm_id)
-{
-    dev->target_conf[alarm_id].target_period_mode = 0;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(systimer_dev_t *dev, uint32_t alarm_id)
-{
-    dev->target_conf[alarm_id].target_period_mode = 1;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period)
-{
-    HAL_ASSERT(period < (1 << 26));
-    dev->target_conf[alarm_id].target_period = period;
-}
-
-__attribute__((always_inline)) static inline uint32_t systimer_ll_get_alarm_period(systimer_dev_t *dev, uint32_t alarm_id)
-{
-    return dev->target_conf[alarm_id].target_period;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id)
-{
-    dev->comp_load[alarm_id].val = 0x01;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en)
-{
-    if (en) {
-        dev->conf.val |= 1 << (24 - alarm_id);
-    } else {
-        dev->conf.val &= ~(1 << (24 - alarm_id));
-    }
-}
-
-/******************* Interrupt *************************/
-
-__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(systimer_dev_t *dev, uint32_t alarm_id, bool en)
-{
-    if (en) {
-        dev->int_ena.val |= 1 << alarm_id;
-    } else {
-        dev->int_ena.val &= ~(1 << alarm_id);
-    }
-}
-
-__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(systimer_dev_t *dev, uint32_t alarm_id)
-{
-    return dev->int_st.val & (1 << alarm_id);
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(systimer_dev_t *dev, uint32_t alarm_id)
-{
-    dev->int_clr.val |= 1 << alarm_id;
-}
-
-#ifdef __cplusplus
-}
-#endif
@@ -1,209 +0,0 @@
-/*
- * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
- *
- * SPDX-License-Identifier: Apache-2.0
- */
-#pragma once
-
-#include <stdint.h>
-#include <stdbool.h>
-#include "soc/systimer_struct.h"
-#include "soc/clk_tree_defs.h"
-#include "soc/pcr_struct.h"
-#include "hal/assert.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// All these functions get invoked either from ISR or HAL that linked to IRAM.
-// Always inline these functions even no gcc optimization is applied.
-
-/******************* Clock *************************/
-
-__attribute__((always_inline)) static inline void systimer_ll_enable_clock(systimer_dev_t *dev, bool en)
-{
-    dev->conf.clk_en = en;
-}
-
-// Set clock source: XTAL(default) or RC_FAST
-static inline void systimer_ll_set_clock_source(soc_periph_systimer_clk_src_t clk_src)
-{
-    PCR.systimer_func_clk_conf.systimer_func_clk_sel = (clk_src == SYSTIMER_CLK_SRC_RC_FAST) ? 1 : 0;
-}
-
-static inline soc_periph_systimer_clk_src_t systimer_ll_get_clock_source(void)
-{
-    return (PCR.systimer_func_clk_conf.systimer_func_clk_sel == 1) ? SYSTIMER_CLK_SRC_RC_FAST : SYSTIMER_CLK_SRC_XTAL;
-}
-
-/**
- * @brief Enable the bus clock for systimer module
- *
- * @param enable true to enable, false to disable
- */
-static inline void systimer_ll_enable_bus_clock(bool enable)
-{
-    PCR.systimer_conf.systimer_clk_en = enable;
-}
-
-/// use a macro to wrap the function, force the caller to use it in a critical section
-/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
-#define systimer_ll_enable_bus_clock(...) do { \
-        (void)__DECLARE_RCC_RC_ATOMIC_ENV; \
-        systimer_ll_enable_bus_clock(__VA_ARGS__); \
-    } while(0)
-
-/**
- * @brief Reset the systimer module
- *
- * @param group_id Group ID
- */
-static inline void systimer_ll_reset_register(void)
-{
-    PCR.systimer_conf.systimer_rst_en = 1;
-    PCR.systimer_conf.systimer_rst_en = 0;
-}
-
-/// use a macro to wrap the function, force the caller to use it in a critical section
-/// the critical section needs to declare the __DECLARE_RCC_RC_ATOMIC_ENV variable in advance
-#define systimer_ll_reset_register(...) do { \
-        (void)__DECLARE_RCC_RC_ATOMIC_ENV; \
-        systimer_ll_reset_register(__VA_ARGS__); \
-    } while(0)
-
-/********************** ETM *****************************/
-
-__attribute__((always_inline)) static inline void systimer_ll_enable_etm(systimer_dev_t *dev, bool en)
-{
-    dev->conf.etm_en = en;
-}
-
-/******************* Counter *************************/
-
-__attribute__((always_inline)) static inline void systimer_ll_enable_counter(systimer_dev_t *dev, uint32_t counter_id, bool en)
-{
-    if (en) {
-        dev->conf.val |= 1 << (30 - counter_id);
-    } else {
-        dev->conf.val &= ~(1 << (30 - counter_id));
-    }
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_counter_can_stall_by_cpu(systimer_dev_t *dev, uint32_t counter_id, uint32_t cpu_id, bool can)
-{
-    if (can) {
-        dev->conf.val |= 1 << ((28 - counter_id * 2) - cpu_id);
-    } else {
-        dev->conf.val &= ~(1 << ((28 - counter_id * 2) - cpu_id));
-    }
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_counter_snapshot(systimer_dev_t *dev, uint32_t counter_id)
-{
-    dev->unit_op[counter_id].timer_unit_update = 1;
-}
-
-__attribute__((always_inline)) static inline bool systimer_ll_is_counter_value_valid(systimer_dev_t *dev, uint32_t counter_id)
-{
-    return dev->unit_op[counter_id].timer_unit_value_valid;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_set_counter_value(systimer_dev_t *dev, uint32_t counter_id, uint64_t value)
-{
-    dev->unit_load_val[counter_id].hi.timer_unit_load_hi = value >> 32;
-    dev->unit_load_val[counter_id].lo.timer_unit_load_lo = value & 0xFFFFFFFF;
-}
-
-__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_low(systimer_dev_t *dev, uint32_t counter_id)
-{
-    return dev->unit_val[counter_id].lo.timer_unit_value_lo;
-}
-
-__attribute__((always_inline)) static inline uint32_t systimer_ll_get_counter_value_high(systimer_dev_t *dev, uint32_t counter_id)
-{
-    return dev->unit_val[counter_id].hi.timer_unit_value_hi;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_apply_counter_value(systimer_dev_t *dev, uint32_t counter_id)
-{
-    dev->unit_load[counter_id].val = 0x01;
-}
-
-/******************* Alarm *************************/
-
-__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(systimer_dev_t *dev, uint32_t alarm_id, uint64_t value)
-{
-    dev->target_val[alarm_id].hi.timer_target_hi = value >> 32;
-    dev->target_val[alarm_id].lo.timer_target_lo = value & 0xFFFFFFFF;
-}
-
-__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(systimer_dev_t *dev, uint32_t alarm_id)
-{
-    return ((uint64_t)(dev->target_val[alarm_id].hi.timer_target_hi) << 32) | dev->target_val[alarm_id].lo.timer_target_lo;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_connect_alarm_counter(systimer_dev_t *dev, uint32_t alarm_id, uint32_t counter_id)
-{
-    dev->target_conf[alarm_id].target_timer_unit_sel = counter_id;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_oneshot(systimer_dev_t *dev, uint32_t alarm_id)
-{
-    dev->target_conf[alarm_id].target_period_mode = 0;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_period(systimer_dev_t *dev, uint32_t alarm_id)
-{
-    dev->target_conf[alarm_id].target_period_mode = 1;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_set_alarm_period(systimer_dev_t *dev, uint32_t alarm_id, uint32_t period)
-{
-    HAL_ASSERT(period < (1 << 26));
-    dev->target_conf[alarm_id].target_period = period;
-}
-
-__attribute__((always_inline)) static inline uint32_t systimer_ll_get_alarm_period(systimer_dev_t *dev, uint32_t alarm_id)
-{
-    return dev->target_conf[alarm_id].target_period;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_apply_alarm_value(systimer_dev_t *dev, uint32_t alarm_id)
-{
-    dev->comp_load[alarm_id].val = 0x01;
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_enable_alarm(systimer_dev_t *dev, uint32_t alarm_id, bool en)
-{
-    if (en) {
-        dev->conf.val |= 1 << (24 - alarm_id);
-    } else {
-        dev->conf.val &= ~(1 << (24 - alarm_id));
-    }
-}
-
-/******************* Interrupt *************************/
-
-__attribute__((always_inline)) static inline void systimer_ll_enable_alarm_int(systimer_dev_t *dev, uint32_t alarm_id, bool en)
-{
-    if (en) {
-        dev->int_ena.val |= 1 << alarm_id;
-    } else {
-        dev->int_ena.val &= ~(1 << alarm_id);
-    }
-}
-
-__attribute__((always_inline)) static inline bool systimer_ll_is_alarm_int_fired(systimer_dev_t *dev, uint32_t alarm_id)
-{
-    return dev->int_st.val & (1 << alarm_id);
-}
-
-__attribute__((always_inline)) static inline void systimer_ll_clear_alarm_int(systimer_dev_t *dev, uint32_t alarm_id)
-{
-    dev->int_clr.val |= 1 << alarm_id;
-}
-
-#ifdef __cplusplus
-}
-#endif
@@ -7,5 +7,3 @@ entries:
            cache_hal_esp32 (noflash)
        else:
            cache_hal (noflash)
-    if SOC_SYSTIMER_SUPPORTED = y && HAL_SYSTIMER_USE_ROM_IMPL = n:
-        systimer_hal (noflash)
@@ -479,34 +479,6 @@ config SOC_MEMSPI_IS_INDEPENDENT
    bool
    default y

-config SOC_SYSTIMER_COUNTER_NUM
-    int
-    default 2
-
-config SOC_SYSTIMER_ALARM_NUM
-    int
-    default 3
-
-config SOC_SYSTIMER_BIT_WIDTH_LO
-    int
-    default 32
-
-config SOC_SYSTIMER_BIT_WIDTH_HI
-    int
-    default 20
-
-config SOC_SYSTIMER_FIXED_DIVIDER
-    bool
-    default y
-
-config SOC_SYSTIMER_INT_LEVEL
-    bool
-    default y
-
-config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
-    bool
-    default y
-
 config SOC_LP_TIMER_BIT_WIDTH_LO
    int
    default 32
@@ -226,15 +226,6 @@
 #define SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT      1
 #define SOC_MEMSPI_IS_INDEPENDENT                 1

-/*-------------------------- SYSTIMER CAPS ----------------------------------*/
-#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
-#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
-#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
-#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
-#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed: 2.5
-#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
-#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
-
 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
 #define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part
 #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part
@@ -667,34 +667,6 @@ config SOC_MEMSPI_IS_INDEPENDENT
    bool
    default y

-config SOC_SYSTIMER_COUNTER_NUM
-    int
-    default 2
-
-config SOC_SYSTIMER_ALARM_NUM
-    int
-    default 3
-
-config SOC_SYSTIMER_BIT_WIDTH_LO
-    int
-    default 32
-
-config SOC_SYSTIMER_BIT_WIDTH_HI
-    int
-    default 20
-
-config SOC_SYSTIMER_FIXED_DIVIDER
-    bool
-    default y
-
-config SOC_SYSTIMER_INT_LEVEL
-    bool
-    default y
-
-config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
-    bool
-    default y
-
 config SOC_LP_TIMER_BIT_WIDTH_LO
    int
    default 32
@@ -302,15 +302,6 @@
 #define SOC_MEMSPI_SUPPORT_CONTROL_DUMMY_OUT      1
 #define SOC_MEMSPI_IS_INDEPENDENT                 1

-/*-------------------------- SYSTIMER CAPS ----------------------------------*/
-#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
-#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
-#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
-#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
-#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed: 2.5
-#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
-#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
-
 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
 #define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part
 #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part
@@ -1035,38 +1035,6 @@ config SOC_SPI_MEM_FLASH_SUPPORT_HPM
    bool
    default y

-config SOC_SYSTIMER_COUNTER_NUM
-    int
-    default 2
-
-config SOC_SYSTIMER_ALARM_NUM
-    int
-    default 3
-
-config SOC_SYSTIMER_BIT_WIDTH_LO
-    int
-    default 32
-
-config SOC_SYSTIMER_BIT_WIDTH_HI
-    int
-    default 20
-
-config SOC_SYSTIMER_FIXED_DIVIDER
-    bool
-    default y
-
-config SOC_SYSTIMER_SUPPORT_RC_FAST
-    bool
-    default y
-
-config SOC_SYSTIMER_INT_LEVEL
-    bool
-    default y
-
-config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
-    bool
-    default y
-
 config SOC_SYSTIMER_SUPPORT_ETM
    bool
    default y
@@ -427,14 +427,6 @@
 #define SOC_SPI_MEM_FLASH_SUPPORT_HPM                         (1) /*!< Support High Performance Mode */

 /*-------------------------- SYSTIMER CAPS ----------------------------------*/
-#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
-#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
-#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
-#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
-#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed: 2.5
-#define SOC_SYSTIMER_SUPPORT_RC_FAST        1  // Systimer can use RC_FAST clock source
-#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
-#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
 #define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event

 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
@@ -863,38 +863,6 @@ config SOC_MEMSPI_IS_INDEPENDENT
    bool
    default y

-config SOC_SYSTIMER_COUNTER_NUM
-    int
-    default 2
-
-config SOC_SYSTIMER_ALARM_NUM
-    int
-    default 3
-
-config SOC_SYSTIMER_BIT_WIDTH_LO
-    int
-    default 32
-
-config SOC_SYSTIMER_BIT_WIDTH_HI
-    int
-    default 20
-
-config SOC_SYSTIMER_FIXED_DIVIDER
-    bool
-    default y
-
-config SOC_SYSTIMER_SUPPORT_RC_FAST
-    bool
-    default y
-
-config SOC_SYSTIMER_INT_LEVEL
-    bool
-    default y
-
-config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
-    bool
-    default y
-
 config SOC_SYSTIMER_SUPPORT_ETM
    bool
    default y
@@ -366,14 +366,6 @@
 #define SOC_MEMSPI_IS_INDEPENDENT                 1

 /*-------------------------- SYSTIMER CAPS ----------------------------------*/
-#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
-#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
-#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
-#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
-#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed: 2.5
-#define SOC_SYSTIMER_SUPPORT_RC_FAST        1  // Systimer can use RC_FAST clock source
-#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
-#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
 #define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event

 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
@@ -795,38 +795,6 @@ config SOC_SPI_MEM_FLASH_SUPPORT_HPM
    bool
    default y

-config SOC_SYSTIMER_COUNTER_NUM
-    int
-    default 2
-
-config SOC_SYSTIMER_ALARM_NUM
-    int
-    default 3
-
-config SOC_SYSTIMER_BIT_WIDTH_LO
-    int
-    default 32
-
-config SOC_SYSTIMER_BIT_WIDTH_HI
-    int
-    default 20
-
-config SOC_SYSTIMER_FIXED_DIVIDER
-    bool
-    default y
-
-config SOC_SYSTIMER_SUPPORT_RC_FAST
-    bool
-    default y
-
-config SOC_SYSTIMER_INT_LEVEL
-    bool
-    default y
-
-config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
-    bool
-    default y
-
 config SOC_SYSTIMER_SUPPORT_ETM
    bool
    default y
@@ -334,14 +334,6 @@
 #define SOC_SPI_MEM_FLASH_SUPPORT_HPM                         (1) /*!< Support High Performance Mode */

 /*-------------------------- SYSTIMER CAPS ----------------------------------*/
-#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
-#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
-#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
-#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
-#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed: 2.5
-#define SOC_SYSTIMER_SUPPORT_RC_FAST        1  // Systimer can use RC_FAST clock source
-#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
-#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
 #define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event

 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
@@ -867,38 +867,6 @@ config SOC_MEMSPI_IS_INDEPENDENT
    bool
    default y

-config SOC_SYSTIMER_COUNTER_NUM
-    int
-    default 2
-
-config SOC_SYSTIMER_ALARM_NUM
-    int
-    default 3
-
-config SOC_SYSTIMER_BIT_WIDTH_LO
-    int
-    default 32
-
-config SOC_SYSTIMER_BIT_WIDTH_HI
-    int
-    default 20
-
-config SOC_SYSTIMER_FIXED_DIVIDER
-    bool
-    default y
-
-config SOC_SYSTIMER_SUPPORT_RC_FAST
-    bool
-    default y
-
-config SOC_SYSTIMER_INT_LEVEL
-    bool
-    default y
-
-config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
-    bool
-    default y
-
 config SOC_SYSTIMER_SUPPORT_ETM
    bool
    default y
@@ -384,14 +384,6 @@
 #define SOC_MEMSPI_IS_INDEPENDENT                 1

 /*-------------------------- SYSTIMER CAPS ----------------------------------*/
-#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
-#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
-#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
-#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
-#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed to 2 when clock source is XTAL
-#define SOC_SYSTIMER_SUPPORT_RC_FAST        1  // Systimer can use RC_FAST clock source
-#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
-#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
 #define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event

 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
@@ -687,38 +687,6 @@ config SOC_MEMSPI_IS_INDEPENDENT
    bool
    default y

-config SOC_SYSTIMER_COUNTER_NUM
-    int
-    default 2
-
-config SOC_SYSTIMER_ALARM_NUM
-    int
-    default 3
-
-config SOC_SYSTIMER_BIT_WIDTH_LO
-    int
-    default 32
-
-config SOC_SYSTIMER_BIT_WIDTH_HI
-    int
-    default 20
-
-config SOC_SYSTIMER_FIXED_DIVIDER
-    bool
-    default y
-
-config SOC_SYSTIMER_SUPPORT_RC_FAST
-    bool
-    default y
-
-config SOC_SYSTIMER_INT_LEVEL
-    bool
-    default y
-
-config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
-    bool
-    default y
-
 config SOC_SYSTIMER_SUPPORT_ETM
    bool
    default y
@@ -361,14 +361,6 @@
 #define SOC_MEMSPI_IS_INDEPENDENT                          1

 /*-------------------------- SYSTIMER CAPS ----------------------------------*/
-#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
-#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
-#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
-#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
-#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed to 2 when clock source is XTAL
-#define SOC_SYSTIMER_SUPPORT_RC_FAST        1  // Systimer can use RC_FAST clock source
-#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
-#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
 #define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event

 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
@@ -767,38 +767,6 @@ config SOC_MEMSPI_IS_INDEPENDENT
    bool
    default y

-config SOC_SYSTIMER_COUNTER_NUM
-    int
-    default 2
-
-config SOC_SYSTIMER_ALARM_NUM
-    int
-    default 3
-
-config SOC_SYSTIMER_BIT_WIDTH_LO
-    int
-    default 32
-
-config SOC_SYSTIMER_BIT_WIDTH_HI
-    int
-    default 20
-
-config SOC_SYSTIMER_FIXED_DIVIDER
-    bool
-    default y
-
-config SOC_SYSTIMER_SUPPORT_RC_FAST
-    bool
-    default y
-
-config SOC_SYSTIMER_INT_LEVEL
-    bool
-    default y
-
-config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
-    bool
-    default y
-
 config SOC_SYSTIMER_SUPPORT_ETM
    bool
    default y
@@ -383,14 +383,6 @@
 #define SOC_MEMSPI_IS_INDEPENDENT                          1

 /*-------------------------- SYSTIMER CAPS ----------------------------------*/
-#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
-#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
-#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
-#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
-#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed: 2.5
-#define SOC_SYSTIMER_SUPPORT_RC_FAST        1  // Systimer can use RC_FAST clock source
-#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
-#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
 #define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event

 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
@@ -1415,38 +1415,6 @@ config SOC_SPI_MEM_FLASH_SUPPORT_HPM
    bool
    default y

-config SOC_SYSTIMER_COUNTER_NUM
-    int
-    default 2
-
-config SOC_SYSTIMER_ALARM_NUM
-    int
-    default 3
-
-config SOC_SYSTIMER_BIT_WIDTH_LO
-    int
-    default 32
-
-config SOC_SYSTIMER_BIT_WIDTH_HI
-    int
-    default 20
-
-config SOC_SYSTIMER_FIXED_DIVIDER
-    bool
-    default y
-
-config SOC_SYSTIMER_SUPPORT_RC_FAST
-    bool
-    default y
-
-config SOC_SYSTIMER_INT_LEVEL
-    bool
-    default y
-
-config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
-    bool
-    default y
-
 config SOC_SYSTIMER_SUPPORT_ETM
    bool
    default y
@@ -542,14 +542,6 @@
 #define SOC_SPI_MEM_FLASH_SUPPORT_HPM                         (1) /*!< Support High Performance Mode */

 /*-------------------------- SYSTIMER CAPS ----------------------------------*/
-#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
-#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
-#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
-#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
-#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed: 2.5
-#define SOC_SYSTIMER_SUPPORT_RC_FAST        1  // Systimer can use RC_FAST clock source
-#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
-#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
 #define SOC_SYSTIMER_SUPPORT_ETM            1  // Systimer comparator can generate ETM event

 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
@@ -579,22 +579,6 @@ config SOC_MEMSPI_IS_INDEPENDENT
    bool
    default y

-config SOC_SYSTIMER_COUNTER_NUM
-    int
-    default 1
-
-config SOC_SYSTIMER_ALARM_NUM
-    int
-    default 3
-
-config SOC_SYSTIMER_BIT_WIDTH_LO
-    int
-    default 32
-
-config SOC_SYSTIMER_BIT_WIDTH_HI
-    int
-    default 32
-
 config SOC_LP_TIMER_BIT_WIDTH_LO
    int
    default 32
@@ -271,10 +271,6 @@
 #define SOC_MEMSPI_IS_INDEPENDENT                 1

 /*-------------------------- SYSTIMER CAPS ----------------------------------*/
-#define SOC_SYSTIMER_COUNTER_NUM  (1U)  // Number of counter units
-#define SOC_SYSTIMER_ALARM_NUM    3  // Number of alarm units
-#define SOC_SYSTIMER_BIT_WIDTH_LO 32 // Bit width of systimer low part
-#define SOC_SYSTIMER_BIT_WIDTH_HI 32 // Bit width of systimer high part

 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
 #define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part
@@ -691,34 +691,6 @@ config SOC_SPIRAM_XIP_SUPPORTED
    bool
    default y

-config SOC_SYSTIMER_COUNTER_NUM
-    int
-    default 2
-
-config SOC_SYSTIMER_ALARM_NUM
-    int
-    default 3
-
-config SOC_SYSTIMER_BIT_WIDTH_LO
-    int
-    default 32
-
-config SOC_SYSTIMER_BIT_WIDTH_HI
-    int
-    default 20
-
-config SOC_SYSTIMER_FIXED_DIVIDER
-    bool
-    default y
-
-config SOC_SYSTIMER_INT_LEVEL
-    bool
-    default y
-
-config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
-    bool
-    default y
-
 config SOC_LP_TIMER_BIT_WIDTH_LO
    int
    default 32
@@ -293,15 +293,6 @@
 #define SOC_SPIRAM_SUPPORTED            1
 #define SOC_SPIRAM_XIP_SUPPORTED        1

-/*-------------------------- SYS TIMER CAPS ----------------------------------*/
-#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
-#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
-#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
-#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
-#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed: 2.5
-#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level
-#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)
-
 /*-------------------------- LP_TIMER CAPS ----------------------------------*/
 #define SOC_LP_TIMER_BIT_WIDTH_LO           32 // Bit width of lp_timer low part
 #define SOC_LP_TIMER_BIT_WIDTH_HI           16 // Bit width of lp_timer high part
@@ -287,38 +287,6 @@ config SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT
    bool
    default y

-config SOC_SYSTIMER_COUNTER_NUM
-    int
-    default 2
-
-config SOC_SYSTIMER_ALARM_NUM
-    int
-    default 3
-
-config SOC_SYSTIMER_BIT_WIDTH_LO
-    int
-    default 32
-
-config SOC_SYSTIMER_BIT_WIDTH_HI
-    int
-    default 20
-
-config SOC_SYSTIMER_FIXED_DIVIDER
-    bool
-    default y
-
-config SOC_SYSTIMER_SUPPORT_RC_FAST
-    bool
-    default y
-
-config SOC_SYSTIMER_INT_LEVEL
-    bool
-    default y
-
-config SOC_SYSTIMER_ALARM_MISS_COMPENSATE
-    bool
-    default y
-
 config SOC_TIMER_SUPPORT_ETM
    bool
    default y
@@ -222,14 +222,6 @@

 /*-------------------------- SYSTIMER CAPS ----------------------------------*/
 // TODO: [ESP32S31] IDF-14693
-#define SOC_SYSTIMER_COUNTER_NUM            2  // Number of counter units
-#define SOC_SYSTIMER_ALARM_NUM              3  // Number of alarm units
-#define SOC_SYSTIMER_BIT_WIDTH_LO           32 // Bit width of systimer low part
-#define SOC_SYSTIMER_BIT_WIDTH_HI           20 // Bit width of systimer high part
-#define SOC_SYSTIMER_FIXED_DIVIDER          1  // Clock source divider is fixed: 2.5
-#define SOC_SYSTIMER_SUPPORT_RC_FAST        1  // Systimer can use RC_FAST clock source
-#define SOC_SYSTIMER_INT_LEVEL              1  // Systimer peripheral uses level interrupt
-#define SOC_SYSTIMER_ALARM_MISS_COMPENSATE  1  // Systimer peripheral can generate interrupt immediately if t(target) > t(current)

 /*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
 #define SOC_TIMER_SUPPORT_ETM             (1)
@@ -25,6 +25,7 @@ set(esp_hal_components
    esp_hal_rtc_timer
    esp_hal_clock
    esp_hal_security
+    esp_hal_systimer
 )
 set(COMPONENTS ${g0_components} ${g1_components} ${esp_hal_components} main)