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fix(rmt): alloc channel memory from internal
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -195,14 +195,14 @@ esp_err_t rmt_new_rx_channel(const rmt_rx_channel_config_t *config, rmt_channel_
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ESP_GOTO_ON_FALSE(config->flags.with_dma == 0, ESP_ERR_NOT_SUPPORTED, err, TAG, "DMA not supported");
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#endif // SOC_RMT_SUPPORT_DMA
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// malloc channel memory
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uint32_t mem_caps = RMT_MEM_ALLOC_CAPS;
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// allocate channel memory from internal memory because it contains atomic variable
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uint32_t mem_caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT;
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rx_channel = heap_caps_calloc(1, sizeof(rmt_rx_channel_t), mem_caps);
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ESP_GOTO_ON_FALSE(rx_channel, ESP_ERR_NO_MEM, err, TAG, "no mem for rx channel");
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// create DMA descriptor
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size_t num_dma_nodes = 0;
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if (config->flags.with_dma) {
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mem_caps |= MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA;
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mem_caps |= MALLOC_CAP_DMA;
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num_dma_nodes = config->mem_block_symbols * sizeof(rmt_symbol_word_t) / RMT_DMA_DESC_BUF_MAX_SIZE + 1;
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// DMA descriptors must be placed in internal SRAM
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rx_channel->dma_nodes = heap_caps_aligned_calloc(RMT_DMA_DESC_ALIGN, num_dma_nodes, sizeof(rmt_dma_descriptor_t), mem_caps);
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@@ -579,7 +579,7 @@ static bool IRAM_ATTR rmt_isr_handle_rx_done(rmt_rx_channel_t *rx_chan)
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portENTER_CRITICAL_ISR(&channel->spinlock);
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rmt_ll_rx_set_mem_owner(hal->regs, channel_id, RMT_LL_MEM_OWNER_SW);
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// copy the symbols to user space
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// Start from C6, the actual pulse count is the number of input pulses N - 1.
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// Resulting in the last threshold interrupts may not be triggered correctly when the number of received symbols is a multiple of the memory block size.
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// As shown in the figure below, So we special handle the offset
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@@ -233,14 +233,14 @@ esp_err_t rmt_new_tx_channel(const rmt_tx_channel_config_t *config, rmt_channel_
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ESP_GOTO_ON_FALSE(config->flags.with_dma == 0, ESP_ERR_NOT_SUPPORTED, err, TAG, "DMA not supported");
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#endif
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// malloc channel memory
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uint32_t mem_caps = RMT_MEM_ALLOC_CAPS;
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// allocate channel memory from internal memory because it contains atomic variable
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uint32_t mem_caps = MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT;
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tx_channel = heap_caps_calloc(1, sizeof(rmt_tx_channel_t) + sizeof(rmt_tx_trans_desc_t) * config->trans_queue_depth, mem_caps);
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ESP_GOTO_ON_FALSE(tx_channel, ESP_ERR_NO_MEM, err, TAG, "no mem for tx channel");
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// create DMA descriptors
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if (config->flags.with_dma) {
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// DMA descriptors must be placed in internal SRAM
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mem_caps |= MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA;
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mem_caps |= MALLOC_CAP_DMA;
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tx_channel->dma_nodes = heap_caps_aligned_calloc(RMT_DMA_DESC_ALIGN, RMT_DMA_NODES_PING_PONG, sizeof(rmt_dma_descriptor_t), mem_caps);
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ESP_GOTO_ON_FALSE(tx_channel->dma_nodes, ESP_ERR_NO_MEM, err, TAG, "no mem for tx DMA nodes");
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// we will use the non-cached address to manipulate the DMA descriptor, for simplicity
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