fix(mspi): fixed mspi dma burst timing issue

components/esp_mm/esp_cache_msync.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/esp_mm/include/esp_cache.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/esp_mm/include/esp_private/esp_cache_private.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/esp_psram/CMakeLists.txt

@@ -15,7 +15,7 @@ if(${target} STREQUAL "esp32")
     list(APPEND priv_requires bootloader_support esp_driver_spi esp_driver_gpio)
 endif()
 
-set(srcs)
+set(srcs "system_layer/esp_psram_mspi.c")
 
 if(CONFIG_SPIRAM)
     list(APPEND srcs "system_layer/esp_psram.c")

components/esp_psram/include/esp_private/esp_psram_mspi.h

@@ -0,0 +1,34 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stddef.h>
+#include <stdbool.h>
+#include "sdkconfig.h"
+#include "esp_err.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define ESP_PSRAM_MSPI_MB_WORKAROUND    (CONFIG_IDF_TARGET_ESP32C5 && CONFIG_ESP32C5_REV_MIN_FULL < 102) || (CONFIG_IDF_TARGET_ESP32C61 && CONFIG_ESP32C61_REV_MIN_FULL < 101)
+
+/**
+ * @brief Initialize PSRAM MSPI memory barrier
+ *
+ * @return ESP_OK on success, otherwise an error code
+ */
+esp_err_t esp_psram_mspi_mb_init(void);
+
+/**
+ * @brief PSRAM MSPI memory barrier
+ */
+void esp_psram_mspi_mb(void);
+
+#ifdef __cplusplus
+}
+#endif

components/esp_psram/system_layer/esp_psram.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2026 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -29,6 +29,7 @@
 #include "esp_private/esp_psram_extram.h"
 #include "esp_private/esp_mmu_map_private.h"
 #include "esp_private/esp_psram_impl.h"
+#include "esp_private/esp_psram_mspi.h"
 #include "esp_private/startup_internal.h"
 #if SOC_SPIRAM_XIP_SUPPORTED
 #include "esp_private/mmu_psram_flash.h"
@@ -114,6 +115,8 @@ static const DRAM_ATTR char TAG[] = "esp_psram";
 
 ESP_SYSTEM_INIT_FN(add_psram_to_heap, CORE, BIT(0), 103)
 {
+    esp_err_t ret = ESP_FAIL;
+
 #if CONFIG_SPIRAM_BOOT_INIT && (CONFIG_SPIRAM_USE_CAPS_ALLOC || CONFIG_SPIRAM_USE_MALLOC)
 
 #if (CONFIG_IDF_TARGET_ESP32C5 && CONFIG_ESP32C5_REV_MIN_FULL <= 100) || (CONFIG_IDF_TARGET_ESP32C61 && CONFIG_ESP32C61_REV_MIN_FULL <= 100)
@@ -123,17 +126,24 @@ ESP_SYSTEM_INIT_FN(add_psram_to_heap, CORE, BIT(0), 103)
     }
 #endif
     if (esp_psram_is_initialized()) {
-        esp_err_t r = esp_psram_extram_add_to_heap_allocator();
-        if (r != ESP_OK) {
+        ret = esp_psram_extram_add_to_heap_allocator();
+        if (ret != ESP_OK) {
             ESP_EARLY_LOGE(TAG, "External RAM could not be added to heap!");
-            abort();
+            return ret;
         }
 #if CONFIG_SPIRAM_USE_MALLOC
         heap_caps_malloc_extmem_enable(CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL);
 #endif
     }
 #endif
-    return ESP_OK;
+
+    ret = esp_psram_mspi_mb_init();
+    if (ret != ESP_OK) {
+        ESP_EARLY_LOGE(TAG, "Failed to initialize PSRAM MSPI memory barrier!");
+        return ret;
+    }
+
+    return ret;
 }
 
 #if CONFIG_IDF_TARGET_ESP32

components/esp_psram/system_layer/esp_psram_mspi.c

@@ -0,0 +1,50 @@
+/*
+ * SPDX-FileCopyrightText: 2026 Espressif Systems (Shanghai) CO LTD
+*
+* SPDX-License-Identifier: Apache-2.0
+*/
+
+#include <stdint.h>
+#include <string.h>
+#include <sys/param.h>
+#include <inttypes.h>
+#include "sdkconfig.h"
+#include "esp_attr.h"
+#include "esp_log.h"
+#include "esp_check.h"
+#include "esp_intr_alloc.h"
+#include "esp_cache.h"
+#include "esp_heap_caps.h"
+#include "esp_private/esp_psram_mspi.h"
+
+__attribute__((unused)) ESP_LOG_ATTR_TAG_DRAM(TAG, "psram_mspi");
+
+#if ESP_PSRAM_MSPI_MB_WORKAROUND
+static void *s_psram_mb_dummy_cacheline;  //dummy cacheline for cache memory barrier
+#endif
+
+esp_err_t esp_psram_mspi_mb_init(void)
+{
+#if ESP_PSRAM_MSPI_MB_WORKAROUND
+    s_psram_mb_dummy_cacheline = heap_caps_calloc(1, CONFIG_CACHE_L1_CACHE_LINE_SIZE, MALLOC_CAP_SPIRAM | MALLOC_CAP_CACHE_ALIGNED);
+    if (!s_psram_mb_dummy_cacheline) {
+        ESP_EARLY_LOGE(TAG, "Failed to allocate dummy cacheline for PSRAM memory barrier!");
+    }
+#endif
+
+    return ESP_OK;
+}
+
+void IRAM_ATTR esp_psram_mspi_mb(void)
+{
+#if ESP_PSRAM_MSPI_MB_WORKAROUND
+    if (s_psram_mb_dummy_cacheline) {
+        uint32_t *p = (uint32_t *)s_psram_mb_dummy_cacheline;
+        *p = (*p + 1) % UINT32_MAX;
+        __attribute__((unused)) esp_err_t ret = ESP_FAIL;
+        ret = esp_cache_msync(s_psram_mb_dummy_cacheline, sizeof(uint32_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED); //malloc is aligned, no need to writeback all
+        assert(ret == ESP_OK);
+        asm volatile("fence");
+    }
+#endif
+}

components/esp_psram/test_apps/psram/pytest_psram.py

@@ -1,4 +1,4 @@
-# SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
+# SPDX-FileCopyrightText: 2021-2026 Espressif Systems (Shanghai) CO LTD
 # SPDX-License-Identifier: CC0-1.0
 import pytest
 from pytest_embedded import Dut