feat(gpio): add fast gpio && sdm && filter support on esp32h21

components/esp_driver_gpio/test_apps/gpio_extensions/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |

components/esp_driver_sdm/test_apps/sigma_delta/README.md

@@ -1,2 +1,2 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |

components/hal/esp32h21/include/hal/dedic_gpio_cpu_ll.h

@@ -0,0 +1,58 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdint.h>
+#include "riscv/csr.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*fast gpio*/
+#define CSR_GPIO_OEN_USER   0x803
+#define CSR_GPIO_IN_USER    0x804
+#define CSR_GPIO_OUT_USER   0x805
+
+/*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
+#define DEDIC_GPIO_CPU_LL_PERIPH_ALWAYS_ENABLE  1
+
+__attribute__((always_inline))
+static inline void dedic_gpio_cpu_ll_enable_output(uint32_t mask)
+{
+    RV_WRITE_CSR(CSR_GPIO_OEN_USER, mask);
+}
+
+static inline void dedic_gpio_cpu_ll_write_all(uint32_t value)
+{
+    RV_WRITE_CSR(CSR_GPIO_OUT_USER, value);
+}
+
+__attribute__((always_inline))
+static inline uint32_t dedic_gpio_cpu_ll_read_in(void)
+{
+    uint32_t value = RV_READ_CSR(CSR_GPIO_IN_USER);
+    return value;
+}
+
+__attribute__((always_inline))
+static inline uint32_t dedic_gpio_cpu_ll_read_out(void)
+{
+    uint32_t value = RV_READ_CSR(CSR_GPIO_OUT_USER);
+    return value;
+}
+
+__attribute__((always_inline))
+static inline void dedic_gpio_cpu_ll_write_mask(uint32_t mask, uint32_t value)
+{
+    RV_SET_CSR(CSR_GPIO_OUT_USER, mask & value);
+    RV_CLEAR_CSR(CSR_GPIO_OUT_USER, mask & ~(value));
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h21/include/hal/gpio_glitch_filter_ll.h

@@ -0,0 +1,60 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include "hal/assert.h"
+#include "soc/gpio_ext_struct.h"
+
+#define GPIO_LL_GLITCH_FILTER_MAX_WINDOW  64
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Enable GPIO glitch filter
+ *
+ * @param hw Glitch filter register base address
+ * @param filter_idx Glitch filter index
+ * @param enable True to enable, false to disable
+ */
+static inline void gpio_ll_glitch_filter_enable(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, bool enable)
+{
+    hw->ext_glitch_filter_chn[filter_idx].ext_filter_chn_en = enable;
+}
+
+/**
+ * @brief Set the input GPIO for the glitch filter
+ *
+ * @param hw Glitch filter register base address
+ * @param filter_idx Glitch filter index
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_glitch_filter_set_gpio(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, uint32_t gpio_num)
+{
+    hw->ext_glitch_filter_chn[filter_idx].ext_filter_chn_input_io_num = gpio_num;
+}
+
+/**
+ * @brief Set the coefficient of the glitch filter window
+ *
+ * @param hw Glitch filter register base address
+ * @param filter_idx Glitch filter index
+ * @param window_width Window width, in IOMUX clock ticks
+ * @param window_threshold Window threshold, in IOMUX clock ticks
+ */
+static inline void gpio_ll_glitch_filter_set_window_coeff(gpio_glitch_filter_dev_t *hw, uint32_t filter_idx, uint32_t window_width, uint32_t window_thres)
+{
+    HAL_ASSERT(window_thres <= window_width);
+    hw->ext_glitch_filter_chn[filter_idx].ext_filter_chn_window_width = window_width - 1;
+    hw->ext_glitch_filter_chn[filter_idx].ext_filter_chn_window_thres = window_thres - 1;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32h21/include/hal/sdm_ll.h

@@ -0,0 +1,64 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+#include <stdbool.h>
+#include "hal/misc.h"
+#include "hal/assert.h"
+#include "soc/gpio_ext_struct.h"
+#include "soc/gpio_ext_reg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// Get SDM register base address with giving group number
+#define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL)
+
+#define SDM_LL_PRESCALE_MAX     (GPIO_EXT_SD0_PRESCALE_V + 1)
+
+/**
+ * @brief Set Sigma-delta enable
+ *
+ * @param hw Peripheral SIGMADELTA hardware instance address.
+ * @param en Sigma-delta enable value
+ */
+static inline void sdm_ll_enable_clock(gpio_sd_dev_t *hw, bool en)
+{
+    hw->misc.ext_sigmadelta_clk_en = en;
+}
+
+/**
+ * @brief Set Sigma-delta channel duty.
+ *
+ * @param hw Peripheral SIGMADELTA hardware instance address.
+ * @param channel Sigma-delta channel number
+ * @param density Sigma-delta quantized density of one channel, the value ranges from -128 to 127, recommended range is -90 ~ 90.
+ *             The waveform is more like a random one in this range.
+ */
+__attribute__((always_inline))
+static inline void sdm_ll_set_pulse_density(gpio_sd_dev_t *hw, int channel, int8_t density)
+{
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], ext_sdn_in, (uint32_t)density);
+}
+
+/**
+ * @brief Set Sigma-delta channel's clock pre-scale value.
+ *
+ * @param hw Peripheral SIGMADELTA hardware instance address.
+ * @param channel Sigma-delta channel number
+ * @param prescale The divider of source clock, ranges from 1 to 256
+ */
+static inline void sdm_ll_set_prescale(gpio_sd_dev_t *hw, int channel, uint32_t prescale)
+{
+    HAL_ASSERT(prescale && prescale <= SDM_LL_PRESCALE_MAX);
+    HAL_FORCE_MODIFY_U32_REG_FIELD(hw->channel[channel], ext_sdn_prescale, prescale - 1);
+}
+
+#ifdef __cplusplus
+}
+#endif

components/soc/esp32h21/dedic_gpio_periph.c

@@ -0,0 +1,36 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/gpio_sig_map.h"
+#include "soc/dedic_gpio_periph.h"
+
+const dedic_gpio_signal_conn_t dedic_gpio_periph_signals = {
+    .irq = -1,
+    .cores = {
+        [0] = {
+            .in_sig_per_channel = {
+                [0] = CPU_GPIO_IN0_IDX,
+                [1] = CPU_GPIO_IN1_IDX,
+                [2] = CPU_GPIO_IN2_IDX,
+                [3] = CPU_GPIO_IN3_IDX,
+                [4] = CPU_GPIO_IN4_IDX,
+                [5] = CPU_GPIO_IN5_IDX,
+                [6] = CPU_GPIO_IN6_IDX,
+                [7] = CPU_GPIO_IN7_IDX,
+            },
+            .out_sig_per_channel = {
+                [0] = CPU_GPIO_OUT0_IDX,
+                [1] = CPU_GPIO_OUT1_IDX,
+                [2] = CPU_GPIO_OUT2_IDX,
+                [3] = CPU_GPIO_OUT3_IDX,
+                [4] = CPU_GPIO_OUT4_IDX,
+                [5] = CPU_GPIO_OUT5_IDX,
+                [6] = CPU_GPIO_OUT6_IDX,
+                [7] = CPU_GPIO_OUT7_IDX,
+            }
+        },
+    },
+};

components/soc/esp32h21/include/soc/Kconfig.soc_caps.in

@@ -3,6 +3,10 @@
 # using gen_soc_caps_kconfig.py, do not edit manually
 #####################################################
 
+config SOC_DEDICATED_GPIO_SUPPORTED
+    bool
+    default y
+
 config SOC_UART_SUPPORTED
     bool
     default y
@@ -47,6 +51,10 @@ config SOC_I2S_SUPPORTED
     bool
     default y
 
+config SOC_SDM_SUPPORTED
+    bool
+    default y
+
 config SOC_GPSPI_SUPPORTED
     bool
     default y
@@ -371,6 +379,14 @@ config SOC_GPIO_PIN_COUNT
     int
     default 26
 
+config SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER
+    bool
+    default y
+
+config SOC_GPIO_FLEX_GLITCH_FILTER_NUM
+    int
+    default 8
+
 config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
     bool
     default y

components/soc/esp32h21/include/soc/clk_tree_defs.h

@@ -188,6 +188,39 @@ typedef enum {
 #endif
 } soc_periph_gptimer_clk_src_t;
 
+//////////////////////////////////////////////////SDM///////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of SDM
+ */
+#define SOC_SDM_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Sigma Delta Modulator clock source
+ */
+typedef enum {
+    SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,                        /*!< Select XTAL clock as the source clock */
+    SDM_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M,                /*!< Select PLL_F48M clock as the source clock */
+    SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M,                 /*!< Select PLL_F48M as the default clock choice */
+} soc_periph_sdm_clk_src_t;
+
+//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////
+
+/**
+ * @brief Array initializer for all supported clock sources of Glitch Filter
+ */
+#define SOC_GLITCH_FILTER_CLKS {SOC_MOD_CLK_PLL_F48M, SOC_MOD_CLK_XTAL}
+
+/**
+ * @brief Glitch filter clock source
+ */
+
+typedef enum {
+    GLITCH_FILTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,         /*!< Select XTAL clock as the source clock */
+    GLITCH_FILTER_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the source clock */
+    GLITCH_FILTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M,  /*!< Select PLL_F48M clock as the default clock choice */
+} soc_periph_glitch_filter_clk_src_t;
+
 //////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
 
 /**

components/soc/esp32h21/include/soc/retention_periph_defs.h

@@ -46,6 +46,7 @@ typedef enum periph_retention_module {
     SLEEP_RETENTION_MODULE_GPSPI2       = 22,
     SLEEP_RETENTION_MODULE_LEDC         = 23,
     SLEEP_RETENTION_MODULE_MCPWM0       = 24,
+    SLEEP_RETENTION_MODULE_SDM0         = 25,
 
     /* Modem module, which includes BLE and 802.15.4 */
     SLEEP_RETENTION_MODULE_BLE_MAC      = 28,
@@ -80,6 +81,7 @@ typedef enum periph_retention_module {
     : ((m) == SLEEP_RETENTION_MODULE_GPSPI2)       ? true \
     : ((m) == SLEEP_RETENTION_MODULE_LEDC)         ? true \
     : ((m) == SLEEP_RETENTION_MODULE_MCPWM0)       ? true \
+    : ((m) == SLEEP_RETENTION_MODULE_SDM0)         ? true \
     : false)
 
 #ifdef __cplusplus

components/soc/esp32h21/include/soc/soc_caps.h

@@ -25,7 +25,7 @@
 /*-------------------------- COMMON CAPS ---------------------------------------*/
 // #define SOC_ADC_SUPPORTED               1    //TODO: [ESP32H21] IDF-11589, IDF-11592
 // #define SOC_ANA_CMPR_SUPPORTED          1
-// #define SOC_DEDICATED_GPIO_SUPPORTED    1    //TODO: [ESP32H21] IDF-11621
+#define SOC_DEDICATED_GPIO_SUPPORTED    1
 #define SOC_UART_SUPPORTED              1
 #define SOC_GDMA_SUPPORTED              1
 #define SOC_AHB_GDMA_SUPPORTED          1
@@ -43,7 +43,7 @@
 #define SOC_RTC_FAST_MEM_SUPPORTED      1
 #define SOC_RTC_MEM_SUPPORTED           1       //TODO: [ESP32H21] IDF-11548
 #define SOC_I2S_SUPPORTED               1
-// #define SOC_SDM_SUPPORTED               1    //TODO: [ESP32H21] IDF-11573
+#define SOC_SDM_SUPPORTED               1
 #define SOC_GPSPI_SUPPORTED             1
 #define SOC_LEDC_SUPPORTED              1
 #define SOC_I2C_SUPPORTED               1
@@ -194,8 +194,8 @@
 // ESP32-H21 has 1 GPIO peripheral
 #define SOC_GPIO_PORT                           1U
 #define SOC_GPIO_PIN_COUNT                      26
-// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER      1
-// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM         8
+#define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER      1
+#define SOC_GPIO_FLEX_GLITCH_FILTER_NUM         8
 #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER         1
 
 // GPIO peripheral has the ETM extension

components/soc/esp32h21/include/soc/soc_caps_full.h

@@ -9,6 +9,10 @@
 #include "soc/soc_caps.h"
 #include "soc/soc_caps_eval.h"
 
+/*------------------------------- Dedicated GPIO ------------------------------*/
+#define _SOC_CAPS_DEDIC_GPIO_OUT_CHANS_PER_CPU     8 /*!< 8 outward channels on each CPU core */
+#define _SOC_CAPS_DEDIC_GPIO_IN_CHANS_PER_CPU      8 /*!< 8 inward channels on each CPU core */
+
 /*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
 #define _SOC_CAPS_SDM_INST_NUM                    1  // Number of SDM instances
 #define _SOC_CAPS_SDM_CHANS_PER_INST              4  // Number of channels in each SDM instance

components/soc/esp32h21/ld/esp32h21.peripherals.ld

@@ -39,6 +39,8 @@ PROVIDE ( ECDSA               = 0x6008E000 );
 PROVIDE ( IO_MUX              = 0x60090000 );
 PROVIDE ( GPIO                = 0x60091000 );
 PROVIDE ( GPIO_EXT            = 0x60091E00 );
+PROVIDE ( SDM                 = 0x60091E04 );
+PROVIDE ( GLITCH_FILTER       = 0x60091ED8 );
 PROVIDE ( GPIO_ETM            = 0x60091F18 );
 PROVIDE ( MEM_MONITOR         = 0x60092000 );
 PROVIDE ( PAU                 = 0x60093000 );

components/soc/esp32h21/register/soc/gpio_ext_struct.h

@@ -113,23 +113,23 @@ typedef union {
  */
 typedef union {
     struct {
-        /** ext_filter_ch0_en : R/W; bitpos: [0]; default: 0;
+        /** ext_filter_chn_en : R/W; bitpos: [0]; default: 0;
          *  Glitch Filter channel enable bit.
          */
-        uint32_t ext_filter_ch0_en:1;
-        /** ext_filter_ch0_input_io_num : R/W; bitpos: [5:1]; default: 0;
+        uint32_t ext_filter_chn_en:1;
+        /** ext_filter_chn_input_io_num : R/W; bitpos: [5:1]; default: 0;
          *  Glitch Filter input io number.
          */
-        uint32_t ext_filter_ch0_input_io_num:5;
+        uint32_t ext_filter_chn_input_io_num:5;
         uint32_t reserved_6:2;
-        /** ext_filter_ch0_window_thres : R/W; bitpos: [13:8]; default: 0;
+        /** ext_filter_chn_window_thres : R/W; bitpos: [13:8]; default: 0;
          *  Glitch Filter window threshold.
          */
-        uint32_t ext_filter_ch0_window_thres:6;
-        /** ext_filter_ch0_window_width : R/W; bitpos: [19:14]; default: 0;
+        uint32_t ext_filter_chn_window_thres:6;
+        /** ext_filter_chn_window_width : R/W; bitpos: [19:14]; default: 0;
          *  Glitch Filter window width.
          */
-        uint32_t ext_filter_ch0_window_width:6;
+        uint32_t ext_filter_chn_window_width:6;
         uint32_t reserved_20:12;
     };
     uint32_t val;
@@ -556,6 +556,15 @@ typedef union {
     uint32_t val;
 } gpio_ext_version_reg_t;
 
+typedef struct gpio_sd_dev_t {
+    volatile gpio_ext_sigmadelta_misc_reg_t misc;
+    volatile gpio_ext_sigmadeltan_reg_t channel[4];
+} gpio_sd_dev_t;
+
+typedef struct {
+    volatile gpio_ext_glitch_filter_chn_reg_t ext_glitch_filter_chn[8];
+} gpio_glitch_filter_dev_t;
+
 typedef struct {
     volatile gpio_ext_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
     uint32_t reserved_080[8];
@@ -564,13 +573,12 @@ typedef struct {
 
 typedef struct {
     uint32_t reserved_000;
-    volatile gpio_ext_sigmadelta_misc_reg_t ext_sigmadelta_misc;
-    volatile gpio_ext_sigmadeltan_reg_t ext_sigmadeltan[4];
+    volatile gpio_sd_dev_t sigma_delta;
     uint32_t reserved_018[16];
     volatile gpio_ext_pad_comp_config_0_reg_t ext_pad_comp_config_0;
     volatile gpio_ext_pad_comp_filter_0_reg_t ext_pad_comp_filter_0;
     uint32_t reserved_060[30];
-    volatile gpio_ext_glitch_filter_chn_reg_t ext_glitch_filter_chn[8];
+    volatile gpio_glitch_filter_dev_t glitch_filter;
     uint32_t reserved_0f8[8];
     volatile gpio_etm_dev_t etm;
     uint32_t reserved_170[24];
@@ -583,6 +591,8 @@ typedef struct {
     volatile gpio_ext_version_reg_t ext_version;
 } gpio_ext_dev_t;
 
+extern gpio_sd_dev_t SDM;
+extern gpio_glitch_filter_dev_t GLITCH_FILTER;
 extern gpio_etm_dev_t GPIO_ETM;
 extern gpio_ext_dev_t GPIO_EXT;
 

components/soc/esp32h21/sdm_periph.c

@@ -0,0 +1,58 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include "soc/sdm_periph.h"
+#include "soc/gpio_sig_map.h"
+#include "soc/gpio_ext_reg.h"
+
+const soc_sdm_signal_desc_t soc_sdm_signals[1] = {
+    [0] = {
+        .module_name = "SDM0",
+        .channels = {
+            [0] = {
+                .sig_id_matrix = GPIO_SD0_OUT_IDX
+            },
+            [1] = {
+                .sig_id_matrix = GPIO_SD1_OUT_IDX
+            },
+            [2] = {
+                .sig_id_matrix = GPIO_SD2_OUT_IDX
+            },
+            [3] = {
+                .sig_id_matrix = GPIO_SD3_OUT_IDX
+            }
+        }
+    }
+};
+
+/**
+ * @brief Registers in retention context:
+ *        GPIO_EXT_SIGMADELTA[x]_REG
+ *        GPIO_EXT_SIGMADELTA_MISC_REG
+ */
+#define GPIO_EXT_RETENTION_REGS_CNT 5
+#define GPIO_EXT_RETENTION_REGS_BASE (DR_REG_GPIO_EXT_BASE + 0x0)
+static const uint32_t gpio_ext_regs_map[4] = {0x20f, 0x0, 0x0, 0x0};
+static const regdma_entries_config_t gpio_ext_regdma_entries[] = {
+    // backup stage: save configuration and status registers
+    // restore stage: restore the configuration and status registers
+    [0] = {
+        .config = REGDMA_LINK_ADDR_MAP_INIT(REGDMA_SDM_LINK(0x00),
+                                            GPIO_EXT_RETENTION_REGS_BASE, GPIO_EXT_RETENTION_REGS_BASE,
+                                            GPIO_EXT_RETENTION_REGS_CNT, 0, 0,
+                                            gpio_ext_regs_map[0], gpio_ext_regs_map[1],
+                                            gpio_ext_regs_map[2], gpio_ext_regs_map[3]),
+        .owner = ENTRY(0) | ENTRY(2),
+    },
+};
+
+const soc_sdm_retention_desc_t soc_sdm_retention_infos[1] = {
+    [0] = {
+        .module = SLEEP_RETENTION_MODULE_SDM0,
+        .regdma_entry_array = gpio_ext_regdma_entries,
+        .array_size = ARRAY_SIZE(gpio_ext_regdma_entries)
+    }
+};

docs/docs_not_updated/esp32h21.txt

@@ -117,17 +117,14 @@ api-reference/bluetooth/esp_hf_defs.rst
 api-reference/peripherals/cap_touch_sens.rst
 api-reference/peripherals/index.rst
 api-reference/peripherals/sdio_slave.rst
-api-reference/peripherals/bitscrambler.rst
 api-reference/peripherals/temp_sensor.rst
 api-reference/peripherals/usb_device.rst
-api-reference/peripherals/jpeg.rst
 api-reference/peripherals/mcpwm.rst
 api-reference/peripherals/usb_host.rst
 api-reference/peripherals/camera_driver.rst
 api-reference/peripherals/adc_oneshot.rst
 api-reference/peripherals/sdspi_share.rst
 api-reference/peripherals/ana_cmpr.rst
-api-reference/peripherals/i2c_slave_v1.rst
 api-reference/peripherals/adc_continuous.rst
 api-reference/peripherals/sdspi_host.rst
 api-reference/peripherals/vad.rst
@@ -140,24 +137,14 @@ api-reference/peripherals/usb_host/usb_host_notes_ext_port.rst
 api-reference/peripherals/usb_host/usb_host_notes_design.rst
 api-reference/peripherals/usb_host/usb_host_notes_enum.rst
 api-reference/peripherals/usb_host/usb_host_notes_dwc_otg.rst
-api-reference/peripherals/dedic_gpio.rst
 api-reference/peripherals/parlio.rst
 api-reference/peripherals/adc_calibration.rst
 api-reference/peripherals/lp_i2s.rst
-api-reference/peripherals/dac.rst
 api-reference/peripherals/spi_flash/index.rst
 api-reference/peripherals/spi_flash/spi_flash_concurrency.rst
 api-reference/peripherals/spi_flash/spi_flash_override_driver.rst
 api-reference/peripherals/spi_flash/spi_flash_optional_feature.rst
 api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst
-api-reference/peripherals/sdm.rst
-api-reference/peripherals/lcd/i80_lcd.rst
-api-reference/peripherals/lcd/index.rst
-api-reference/peripherals/lcd/dsi_lcd.rst
-api-reference/peripherals/lcd/i2c_lcd.rst
-api-reference/peripherals/lcd/spi_lcd.rst
-api-reference/peripherals/lcd/rgb_lcd.rst
-api-reference/peripherals/lcd/parl_lcd.rst
 api-reference/peripherals/spi_features.rst
 api-reference/system/random.rst
 api-reference/system/app_trace.rst

examples/peripherals/dedicated_gpio/soft_i2c/README.md

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
 
 # Example: Software I2C Master via Dedicated/Fast GPIOs
 

examples/peripherals/dedicated_gpio/soft_spi/README.md

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- |
 
 # Example: SPI software emulation using dedicated/fast GPIOs
 

examples/peripherals/dedicated_gpio/soft_uart/README.md

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32-C2 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-C61 | ESP32-H2 | ESP32-H21 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | -------- | -------- | -------- | -------- | --------- | -------- | --------- | -------- | -------- | -------- |
 
 # Example: UART software emulation using dedicated/fast GPIOs
 

examples/peripherals/sigma_delta/sdm_dac/README.md

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 # Sigma Delta Modulation DAC Example
 

examples/peripherals/sigma_delta/sdm_led/README.md

@@ -1,5 +1,5 @@
-| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
-| ----------------- | ----- | -------- | -------- | -------- | -------- | -------- | -------- | -------- | -------- |
+| Supported Targets | ESP32 | ESP32-C3 | ESP32-C5 | ESP32-C6 | ESP32-H2 | ESP32-H21 | ESP32-H4 | ESP32-P4 | ESP32-S2 | ESP32-S3 |
+| ----------------- | ----- | -------- | -------- | -------- | -------- | --------- | -------- | -------- | -------- | -------- |
 
 # Sigma Delta Modulation LED Example